JP2005223477A5

JP2005223477A5 -

Info

Publication number: JP2005223477A5
Application number: JP2004027550A
Authority: JP
Filing date: 2004-02-04
Publication date: 2006-08-17
Anticipated expiration: 2024-02-04

Claims

An arithmetic unit;
A storage device for storing data transmitted from the arithmetic device;
(N + r) -bit data bus connecting the arithmetic unit and the storage device;
A random number generator;
A data converter,
The data converter encrypts the N-bit data transmitted from the arithmetic unit using the data consisting of the r-bit random number generated by the random number generator as a key and encrypts the N-bit data. An (N + r) -bit data is generated by concatenating the encrypted data and the random number, and the (N + r) -bit data is output to a data bus.

The information processing apparatus according to claim 1,
The data converter further performs nonlinear conversion on the (N + r) -bit data and outputs the result to a data bus.

An arithmetic unit;
A storage device for storing data transmitted from the arithmetic device;
(N + r) -bit data bus connecting the arithmetic unit and the storage device;
A random number generator;
A data converter,
The data converter generates (N + r) -bit data by concatenating the N-bit data transmitted from the arithmetic unit and the r-bit random number generated by the random number generator, and generates the (N + r) An information processing apparatus that performs non-linear conversion on bit data and outputs the data to a data bus.

In the information processing according to claim 2 or 3,
The non-linear transformation is a process for obtaining an inverse element of the (N + r) -bit data.

The information processing apparatus according to claim 1 Symbol placement,
The information processing apparatus , wherein the random number generation apparatus generates a random number for each transfer of the data bus .

The information processing apparatus according to claim 5 Symbol mounting,
The information processing apparatus , wherein the random number generation device is a pseudo random number generation device.

The information processing apparatus according to claim 1 ,
Having a second data converter,
The second data converter determines whether each bit transferred from the arithmetic unit to the storage device via each bus line of the data bus corresponds to the N bit or the r bit. Then, the N bits are extracted from the (N + r) bits, and the r bits are discarded .

The information processing apparatus according to claim 7 ,
The data conversion device and the second data order conversion device receive (N + r) -bit data as input, and use irreducible polynomials m (x) and m ′ (x) in GF (2 ⁿ ) as modulo values. An information processing apparatus, which is a conversion apparatus that outputs a reverse element of N bits .

The information processing apparatus according to claim 8.
An information processing apparatus configured to satisfy m (x) = m ′ (x) with respect to the irreducible polynomial used in the data conversion apparatus and the second data inverse conversion apparatus.

The information processing apparatus according to claim 9.
A data comparison device;
A second data bus for transmitting r bits obtained from the random number generator to a data comparator;
The data comparison device compares the r bit obtained from the second data conversion device with the r bit obtained through the second data bus, and discards the r bit if the two bits match. An information processing apparatus that outputs an error signal if they do not match .

The information processing apparatus according to claim 9 .
A data comparison device;
A second random number generator,
The random number generation device and the second random number generation device are both pseudorandom number generation devices, the random number generation device has a synchronization signal line with the second random number generation device, and the random number generation device Connected to a conversion device, the second random number generation device is connected to the data comparison device, and the comparison device obtains r bits obtained from the second data conversion device and the second random number generation device. An information processing apparatus that compares the received r bits .

The information processing apparatus according to claim 7 ,
A plurality of the data converter and the second data converter;
One of the outputs of the plurality of data converters is a first output, the first output is input to the plurality of second data converters via the data bus, and the plurality of second data converters An information processing apparatus characterized by discarding the output except the first output .

An arithmetic unit;
A storage device for storing data transmitted from the arithmetic device;
An N-bit data bus connecting the arithmetic unit and the storage device;
A random number generator;
A data converter,
The data converter receives N-bit data as an input, and outputs an N-bit inverse element modulo the irreducible polynomial m (x) in GF (2 ⁿ ) to the data bus. Information processing apparatus.

The information processing apparatus according to claim 13,
A second data converter connected to the data bus;
The N-bit data input to the data bus is configured as a concatenation of d-bit data output from the arithmetic unit and r-bit data output from the random number generator,
The second data converter outputs an N-bit inverse element modulo the irreducible polynomial for N-bit data transferred by each bus line of the data bus, and each bit of the output is An information processing apparatus that determines which of the d bits and the r bits corresponds, extracts the d bits from (d + r) bits, and discards the r bits .

The information processing apparatus according to claim 14.
The data converter comprises a converter that outputs an inverse element modulo an irreducible polynomial in a plurality of different GF (2 ⁿ ), and the second data converter is the same as the data converter. An information processing apparatus characterized by that.