JP2005223085A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To optimize characteristics of both MOS transistors in a semiconductor device where the MOS transistor having a silicide layer on a semiconductor substrate and the MOS transistor which does not have the silicide layer are mix-loaded, and in a manufacturing method of the device. <P>SOLUTION: The first MOS transistors Tr1 and Tr2 where the silicide layer 99 is formed, and the second MOS transistors Tr3 and Tr4 where the silicide layer is not formed, are formed on the semiconductor substrate 61. Depth Xj3 of source/drain regions 91 to 94 of the first MOS transistors Tr1 and Tr2 and the second MOS transistors Tr3 and Tr4 is set to be equal to depth Xj4 of source/drain regions 95 to 98. Silicide block layers 81 and 82 inhibiting silicide reaction are formed in the second field effect transistors Tr3 and Tr4. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device such as a CMOS image sensor, a semiconductor device typified by a DRAM-embedded logic LSI, and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device having a field effect transistor in which a refractory metal silicide layer is formed and a field effect transistor in which a refractory metal silicide layer is not formed, and a method for manufacturing the same.

  In recent years, in a process of a semiconductor device having a CMOS logic circuit, a method of forming a refractory metal silicide layer in a source / drain region of a MOS transistor by using a salicide technique in order to reduce parasitic resistance as elements are miniaturized. It is common to use. The side-side technology is a step of forming a refractory metal silicide layer on the surface of the silicon gate electrode and the source / drain region of the MOS transistor. As a device having such a CMOS logic circuit, for example, there are functional devices such as a CMOS image sensor and a DRAM-embedded logic LSI.

  On the other hand, a field effect transistor (ie, MOS transistor) region for forming a refractory metal silicide layer in the source / drain region and a field effect transistor (ie, MOS transistor) region in which junction leakage is a problem are formed in one silicon semiconductor chip. It is technically difficult to do. The refractory metal silicide layer is formed by forming a refractory metal on the surface of the source / drain region and reacting silicon with the refractory metal. However, when silicon and the refractory metal do not react completely, and the unreacted refractory metal diffuses and remains in the vicinity of the junction with some probability, the remaining refractory metal serves as a nucleus to increase junction leakage. cause.

A semiconductor device having a refractory metal silicide layer is described in Patent Document 1, for example.
JP-A-2-142127

  By the way, in order to form a MOS transistor for forming a refractory metal silicide layer and a MOS transistor in which junction leakage is a problem in one silicon semiconductor chip, junction leakage is a problem before forming the refractory metal silicide layer. A manufacturing method is conceivable in which the MOS transistor side to be formed is covered with a silicide block layer that inhibits the silicide reaction.

  FIG. 19 shows an example of this manufacturing method. As shown in FIG. 19A, the silicon gate electrode 6 is formed through the gate insulating film 5 in the first region 2 where the refractory metal silicide layer of the silicon semiconductor substrate 1 is not formed, and the etching after the insulating film is formed. A side wall 7 is formed on the side wall of the silicon gate electrode 6 by the back. Further, a silicon gate electrode 6 is formed in the second region 3 where the refractory metal silicide layer is formed in the same process via the gate insulating film 5, and the silicon gate electrode 6 is etched back after the insulating film is formed. Side walls 7 are formed on the side walls. Next, a silicide block layer 8 made of, for example, an insulating film is formed on the entire surface of the first region. Next, an impurity 9 is introduced into the first region 2 and the second region 3 by simultaneous ion implantation in a self-aligning manner using the silicon gate electrode 6 and the side wall 7 as a mask, and the source / drain regions 11 are respectively formed. , 12 and 13, 14 are formed.

  Next, as shown in FIG. 19B, a refractory metal is deposited on the surface of the silicon gate electrode 6 and the source / drain regions 13 and 14 in the second region, and the refractory metal and silicon are reacted to cause a high melting point. A metal silicide layer 10 is formed. As a result, the MOS transistor Tr1 in which the refractory metal silicide layer 10 is not formed is formed in the first region 2, and the MOS transistor Tr2 in which the refractory metal silicide layer 10 is formed is formed in the second region 3.

  However, in this manufacturing method, the refractory metal silicide layer 10 is formed in the first region 2 where the refractory metal silicide layer 10 is not formed at the time of ion implantation when forming the source / drain regions 11 and 12. Since the silicide block layer 8 which is a laminated film thicker than the second region 3 exists, there is a problem that impurities are not implanted deeply. As a result, the source / drain regions 12 and 13 in the first region 2 and the source / drain regions 13 and 14 in the second region 3 have different depths. That is, the depth h1 of the source / drain regions 11, 12 in the first region is shallower than the depth h2 of the source / drain regions 13, 14 in the second region, and the MOS transistor does not have the refractory metal silicide layer 10. The transistor characteristics (that is, parasitic resistance of the source / drain region, contact resistance between the source / drain region and the electrode, etc.) of the MOS transistor Tr2 having Tr1 and the refractory metal silicide layer 10 are deteriorated.

  When the above manufacturing method is applied to, for example, a DRAM embedded logic LSI or a CMOS image sensor having a sensor unit using a DRAM sensor or a photodiode in which junction leakage is a problem, the same inconvenience occurs.

  In view of the above, the present invention enables optimization of transistor characteristics in a field effect transistor having a refractory metal silicide layer mounted on one semiconductor chip and a field effect transistor having no refractory metal silicide layer. A semiconductor device and a method for manufacturing the same are provided.

The semiconductor device according to the present invention includes a first field effect transistor in which a silicide layer is formed on a semiconductor substrate, and a second field effect transistor in which no silicide layer is formed, and the first field effect transistor and the second field effect transistor The depths of the source and drain regions of the field effect transistor are set to be equal to each other.
As a preferred embodiment of the semiconductor device of the present invention, it is appropriate to form a silicide block layer for preventing the silicide reaction in the second field effect transistor.

In the semiconductor device according to the present invention, a first field effect transistor that forms a logic circuit is formed in a first region, and a second field effect transistor in which a silicide layer is not formed in a second region and a pixel including a sensor unit The first field effect transistor has a field effect transistor with a silicide layer, and each of the source / drain regions of the first field effect transistor and the second field effect transistor is formed. The depth is set to be equal, and the device is used as a CMOS type solid-state imaging device.
In a preferred embodiment of the semiconductor device of the present invention, it is appropriate to form a silicide block layer for preventing a silicide reaction in a field effect transistor in which no silicide layer is formed.

In the method for manufacturing a semiconductor device according to the present invention, the silicide block layer for preventing the silicide reaction is not formed in the first region where the first field effect transistor having the silicide layer is formed, and the first layer without the silicide layer is formed. The step of forming the silicide block layer in the second region where the field effect transistor of 2 is formed, and the ion selectively through the mask formed selectively in the first region and the second region. The method includes a step of introducing impurities to form source / drain regions, respectively, and a step of forming a silicide layer in the first field effect transistor.
As a preferable mode in the method of manufacturing a semiconductor device of the present invention, it is appropriate to make the ion implantation conditions for the first region and the second region different.
As a preferable mode in the method for manufacturing a semiconductor device of the present invention, it is appropriate to set the implantation energy for ion implantation into the second region to be larger than the implantation energy for ion implantation into the first region. .

The method for manufacturing a semiconductor device according to the present invention prevents a silicide reaction in a region where a field effect transistor having a silicide layer is formed in a first region where a first field effect transistor constituting a logic circuit is formed. A step of forming a silicide block layer in an imaging region in which a pixel including a second field effect transistor and a sensor portion without forming a silicide block layer and having a silicide layer is formed; A step of selectively introducing an impurity by ion implantation into a region in which the silicide layer is not formed and a region in which the silicide layer is formed in the region 2 and selectively forming a source / drain through a mask; Forming a silicide layer on a field effect transistor to form a silicide layer of one field effect transistor; It includes, characterized in that to produce a CMOS type solid-state imaging device.
As a preferable mode in the method of manufacturing a semiconductor device of the present invention, it is appropriate to make the ion implantation conditions for the first region and the second region different.
As a preferable mode in the method for manufacturing a semiconductor device of the present invention, it is appropriate to set the implantation energy for ion implantation into the second region to be larger than the implantation energy for ion implantation into the first region. .

According to the semiconductor device of the present invention, since the silicide layer is formed in the first field effect transistor, the parasitic resistance of the source / drain region can be reduced along with the miniaturization of the element. Accordingly, the first field effect transistor can operate at high speed and reduce power consumption. On the other hand, since the silicide layer is not formed in the second field effect transistor, junction leakage due to the metal that is not silicided is suppressed. By setting the depths of the source / drain regions of the first and second field effect transistors to be equal, the impurity concentrations of the source / drain regions are also equal. Thereby, the parasitic resistance of the source / drain region of the second field effect transistor having no silicide layer can be reduced, and the contact resistance between the source / drain region and the electrode can be reduced. Therefore, it is possible to provide a high-performance semiconductor device in which the first field effect transistor having the silicide layer and the second field effect transistor not having the silicide layer are both mounted.
Since the second field effect transistor has the silicide block layer for preventing the silicide reaction, formation of the silicide layer on the silicon gate electrode and the source / drain regions of the second field effect transistor can be surely prevented.

According to the semiconductor device according to the present invention, that is, the CMOS type solid-state imaging device, since the silicide layer is formed in the first field effect transistor constituting the logic circuit around the imaging region, the device is miniaturized. The parasitic resistance of the source / drain regions can be reduced. Accordingly, the first field effect transistor can operate at high speed and reduce power consumption. On the other hand, since the silicide layer is not formed in the second field effect transistor on the pixel side, junction leakage due to the metal that is not silicided is suppressed. Then, by setting the depths of the source / drain regions of the first field effect transistor on the logic circuit side and the second field effect transistor on the pixel side to be equal, the impurity concentration of each source / drain region is also increased. It becomes equivalent. Thereby, the parasitic resistance of the source / drain region of the second field effect transistor having no silicide layer on the pixel side can be reduced, and the contact resistance between the source / drain region and the electrode can be reduced. Therefore, a field effect transistor with optimized transistor characteristics can be obtained on both the logic circuit side and the pixel side, and a high-performance CMOS solid-state imaging device can be provided.
The formation of a silicide layer on the silicon gate electrode and the source / drain regions of the second field effect transistor is reliably prevented by having the silicide block layer for preventing the silicide reaction in the second field effect transistor on the pixel side. Can do.

  According to the semiconductor device manufacturing method of the present invention, the silicide block layer is not formed in the first region, the silicide block layer is formed in the second region, and the first and second regions are formed. By selectively implanting ions of impurities, source / drain regions can be formed in the first and second regions under optimum conditions. That is, the depths and impurity concentrations of the source / drain regions of the first and second field effect transistors formed in the first and second regions can be made substantially the same. In addition, since the silicide block layer is provided in the second region, the silicide layer can be formed only in the first field effect transistor in the first region. Thereby, both the transistor characteristics of the field effect transistor having the silicide layer and the transistor not having the silicide layer can be optimized, and a high-performance semiconductor device in which both field effect transistors are mounted can be manufactured.

By making the ion implantation conditions for the first region and the second region different, the transistor characteristics of the first and second field effect transistors can be optimized.
By forming the ion implantation energy into the second region having the silicide block layer larger than the ion implantation energy into the first region not having the silicide block layer, the energy is formed in the first and second regions. The depth and impurity concentration in the source / drain regions can be made equal. Therefore, the transistor characteristics of the first and second field effect transistors can be optimized.

  According to the manufacturing method of the semiconductor device according to the present invention, that is, the manufacturing method of the CMOS type solid-state imaging device, the silicide block layer is not formed in the first region on the logic circuit side, and the second region on the pixel side is formed. Forms a silicide block layer and selectively ion-implants impurities into the first and second regions, so that the first region on the logic circuit side and the second region on the pixel side are sourced under optimum conditions. -A drain region can be formed. That is, the depth of the source / drain regions and the impurity concentration of the first field effect transistor on the logic circuit side and the second field effect transistor on the pixel side can be made substantially the same. Then, by having the silicide block layer on the pixel side, the silicide layer can be formed only on the first field effect transistor on the logic circuit side. As a result, both the transistor characteristics of the field effect transistor having the silicide layer on the logic circuit side and the field effect transistor not having the silicide layer on the pixel side can be optimized, and a high-performance CMOS solid-state imaging device is manufactured. be able to.

By making different ion implantation conditions for the first region on the logic circuit side and the second region on the pixel side, the transistor characteristics of the first and second field effect transistors on the logic circuit side and the pixel side can be changed. Can be optimized.
By setting the ion implantation energy to the second region on the pixel side having the silicide block layer to be larger than the ion implantation energy to the first region on the logic circuit side having no silicide block layer, And the depth and impurity concentration in the source / drain regions formed in the second region can be made equal. Therefore, the transistor characteristics of the field effect transistors on the logic circuit side and the pixel side can be optimized.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

  First, in order to facilitate understanding of the present embodiment, a method for manufacturing a semiconductor device according to a comparative example will be described with reference to FIGS. This semiconductor device is applied to a semiconductor device in which a CMOS transistor having a refractory metal silicide layer and a CMOS transistor not having a refractory metal silicide layer on the same semiconductor substrate are mounted together.

  As shown in FIG. 15A, a first conductivity type, for example, n-type silicon semiconductor substrate 11 is prepared, and a first region 12 in which a MOS transistor having a refractory metal silicide layer of the semiconductor substrate 11 is formed, Second conductivity type, for example, p-type semiconductor well regions 14 and 15 are formed in regions where n-channel MOS transistors are to be formed, respectively, with respect to second regions 13 where MOS transistors having no melting point metal silicide layer are formed. To do. Further, after an element isolation region, for example, a field insulating film 16 by selective oxidation is formed on the semiconductor substrate 11, a gate made of polysilicon is formed at a position corresponding to each MOS transistor via a gate insulating film (for example, silicon oxide film) 17. Electrodes 18, 19, 20, and 21 are formed.

Next, as shown in FIG. 15B, the gate electrodes 18 to 21 are formed on the p-type semiconductor well regions 14 and 15 where the n-channel MOS transistors are to be formed and the n-type semiconductor regions 22 and 23 where the p-channel MOS transistors are to be formed. As a mask, low impurity concentration regions 25, 26, 27, and 28 having an LDD structure are formed in a self-aligning manner. That is, for example, the n-type semiconductor regions 22 and 23 are covered with, for example, a photoresist mask, phosphorus (p) is implanted, the energy is 20 KeV, and the dose amount is 4 × 10 ¹³ / cm ^2. Then, n @-semiconductor regions 25 and 27 are formed. Next, the p-type semiconductor regions 14 and 15 are covered with a photoresist mask, and boron (B) (BF ₂ ) is implanted with an energy of 25 KeV and a dose of 3.5 × 10 ¹⁴ / cm ² . 23, p @-semiconductor regions 26 and 28 are formed.

Next, as shown in FIG. 16C, a silicon oxide (SiO ₂ ) film 31 and a silicon nitride (SiN) film 32 are deposited on the entire surface of the substrate including on the gate electrodes 18 to 21 by a CVD (chemical vapor deposition) method. . The thickness of the silicon oxide film 31 can be about 10 nm, and the thickness of the silicon nitride film 32 can be about 30 nm.

  Next, as shown in FIG. 16D, a resist mask 33 is selectively formed on the region 13 where the refractory metal silicide layer is not formed, and the refractory metal silicide layer is formed by anisotropic etching through the resist mask 33. The silicon oxide film 31 and the silicon nitride film 32 on the region 12 side to be formed are removed. At this time, two-layer side wall portions 34 of the silicon oxide film 31 and the silicon nitride film 32 are formed on the side walls of the gate electrodes 18 and 19 on the refractory metal silicide formation region 12 side.

  Next, as shown in FIG. 17E, after removing the resist mask 33, a silicon oxide film 36 having a thickness of, for example, about 90 nm is deposited on the entire surface of the substrate by a CVD method.

  Next, as shown in FIG. 17F, the silicon oxide film 36 on the substrate is removed by anisotropic etching. At this time, on the side of the refractory metal silicide formation region 12, three side walls 37 of the silicon oxide film 31, the silicon nitride film 32, and the silicon oxide film 36 are formed on the side walls of the gate electrodes 18 and 19. On the side of the region 13 where refractory metal silicide is not formed, a side wall 38 made of a silicon oxide film 36 is formed on the silicon nitride film 32 corresponding to the side walls of the gate electrodes 20 and 21.

Next, as shown in FIG. 18G, n-type impurities are ion-implanted into the n-channel MOS region using the sidewalls 37 and 38 as masks to selectively select the n + source / drain regions 43, 44, 47, and 48. Form. As the ion implantation conditions for the n-type impurity, for example, phosphorus (P) is implanted, and ion implantation is performed with an energy of 20 keV and a dose of 2 × 10 ¹⁵ / cm ² . At this time, in the region 13 where the refractory metal silicide is not formed, the silicide block layer formed by the laminated film of the silicon oxide film 31 and the silicon nitride film 32 remains on the entire surface including the gate electrode. Is formed shallower than the n + source / drain regions 41 and 42 of the refractory metal silicide formation region 12.
Further, p + source / drain regions 43, 44, 47, and 48 are selectively formed by ion implantation of p-type impurities using the sidewalls 37 and 38 as masks in the p-channel MOS region. The ion implantation conditions for the p-type impurity are, for example, boron (B) implantation with an energy of 7 keV and a dose of 2 × 10 ¹⁵ / cm ² . At this time, in the region 13 where the refractory metal silicide is not formed, the silicide block layer formed by the laminated film of the silicon oxide film 31 and the silicon nitride film 32 remains on the entire surface including the gate electrode. Is formed shallower than the p + source / drain regions 43 and 44 of the refractory metal silicide formation region 12. Although not shown, ion implantation into these n-type impurity and p-type impurity is selectively performed through a resist mask.

  Next, as shown in FIG. 18H, a refractory metal such as a cobalt (Co) film is formed on the entire surface of the substrate and heat-treated to form polysilicon gate electrodes 18 and 19, n + source / drain regions 41 and 42, and A cobalt silicide (CoSi) layer 49 is formed on the p + source / drain regions 43 and 44 by reaction. At this time, since the cobalt (Co) film is not in contact with silicon (Si) on the region 13 side covered with the silicon oxide film 31 and the silicon nitride film 32, no cobalt silicide layer is generated. Thereafter, the excess cobalt film is removed. In this way, a CMOS transistor composed of an n-channel MOS transistor Tr1 and a p-channel MOS transistor Tr2 having a refractory metal silicide layer 49 in one region 12 is formed, and no refractory metal silicide layer is formed in the other region 13. A semiconductor device 51 is obtained in which a CMOS transistor composed of an n-channel MOS transistor Tr3 and a p-channel MOS transistor Tr4 is formed.

  According to the semiconductor device 51 having the CMOS transistor manufactured by the manufacturing method of FIGS. 15 to 18, n + source / drain regions (41, 42) on the side where the refractory metal silicide layer is formed and the side where the refractory metal silicide layer is not formed, and The (45, 46) comrades and the p + source / drain regions (43, 44) and (47, 48) are formed in the same ion implantation step. For this reason, in the region where ions are directly implanted into the silicon substrate and the region where ions are implanted through the two-layer films of the first and second insulating films 31 and 32 along the silicide block which inhibits the silicidation, ion implantation is mutually performed. The peak position Rp is different, the impurity concentration of the source / drain region and the diffusion depth (so-called junction depth) of the source / drain region are different, resulting in a difference in transistor characteristics.

  That is, the junction depth Xj2 of the source / drain regions 45 to 48 of the MOS transistors Tr3 and Tr4 having no refractory metal silicide layer 49 is equal to the source / drain region 41 of the MOS transistors Tr1 and Tr2 having the refractory metal silicide layer 49. It becomes shallower than the junction depth Xj1 of .about.44. Further, the impurity concentration of the source / drain regions of the MOS transistors Tr3, Tr4 tends to be lower than the impurity concentration of the source / drain regions of the MOS transistors Tr1, Tr2. Furthermore, the contact resistance between the source / drain electrode and the source / drain region is also different due to the difference in the impurity concentration of the source / drain region. For this reason, the transistor characteristics of the MOS transistors (Tr1, Tr2) and the MOS transistors (Tr3, Tr4) are different from each other, and when either the semiconductor device 51 is viewed as a whole, the element characteristics are deteriorated.

  Next, an embodiment of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to FIGS. This example is applied to the manufacture of a semiconductor device in which a CMOS transistor having a refractory metal silicide layer and a CMOS transistor not having a refractory metal silicide layer are mounted on the same semiconductor substrate as in the comparative example described above. is there.

  As shown in FIG. 1A, a first conductivity type, for example, n-type silicon semiconductor substrate 61 is prepared, and a first region 62 in which a MOS transistor having a refractory metal silicide layer of the semiconductor substrate 61 is formed, Second conductivity type, for example, p-type semiconductor well regions 64 and 65 are formed in regions where n-channel MOS transistors are to be formed, respectively, with respect to second region 63 where MOS transistors having no melting point metal silicide layer are formed. To do. Further, after an element isolation region, for example, a field insulating film 66 by selective oxidation is formed on the semiconductor substrate 61, a gate made of polysilicon is formed at a position corresponding to each MOS transistor via a gate insulating film (for example, silicon oxide film) 67. Electrodes 68, 69, 70, 71 are formed.

Next, as shown in FIG. 1B, gate electrodes 68 to 71 are formed on p-type semiconductor well regions 64 and 65 where n-channel MOS transistors are to be formed and n-type semiconductor regions 72 and 73 where p-channel MOS transistors are to be formed. The low impurity concentration regions 75, 76, 77 and 78 of the LDD structure are formed in a self-aligning manner using the mask as a mask. That is, for example, the n-type semiconductor regions 72 and 73 are covered with, for example, a photoresist mask, phosphorus (p) is implanted, the energy is 20 KeV, and the dose amount is 4 × 10 ¹³ / cm ^2. N @-regions 75 and 77 are formed in Next, the p-type semiconductor regions 64 and 65 are covered with a photoresist mask, and boron (B) (BF ₂ ) is implanted with an energy of 25 KeV and a dose of 3.5 × 10 ¹⁴ / cm ² . 73, p @-regions 76 and 78 are formed.

Next, as shown in FIG. 2C, a first insulating film such as a silicon oxide (SiO ₂ ) film 81 and a second insulating film such as silicon nitride (SiN) are formed on the entire surface of the substrate including on the gate electrodes 68 to 71. A film 82 is deposited by a CVD (chemical vapor deposition) method. The thickness of the silicon oxide film 81 can be about 10 nm, and the thickness of the silicon nitride film 82 can be about 30 nm. As will be described later, the first and second insulating films 81 and 82 become silicide block layers that prevent silicide anti-king.

  Next, as shown in FIG. 2D, a resist mask 83 is selectively formed on the region 63 where the refractory metal silicide layer is not formed, and the refractory metal silicide layer is formed by anisotropic etching through the resist mask 83. The first insulating film 81 and the second insulating film 82 on the region 62 side to be formed are removed. At this time, a two-layer side wall portion 84 of the first insulating film 81 and the second insulating film 82 is formed on the side walls of the gate electrodes 68 and 69 on the refractory metal silicide formation region 62 side.

  Next, as shown in FIG. 3E, after removing the resist mask 83, a third insulating film, for example, a silicon oxide film 86 having a thickness of about 90 nm is deposited on the entire surface of the substrate by a CVD method.

  Next, as shown in FIG. 3F, the third insulating film 86 on the substrate is removed by anisotropic etching. At this time, on the refractory metal silicide formation region 62 side, three side walls 87 of the first insulating film 81, the second insulating film 82, and the third insulating film 86 are formed on the side walls of the gate electrodes 68 and 69. It is formed. On the side of the region 63 where refractory metal silicide is not formed, a side wall 88 made of the third insulating film 86 is formed on the second insulating film 32 corresponding to the side walls of the gate electrodes 70 and 71.

Next, as shown in FIG. 4G, a resist mask 103 is formed so that only the n-channel MOS region 621 on the region 62 side where the refractory metal silicide layer is to be formed is opened and the other regions are covered. N-type impurities are ion-implanted into the n-channel MOS region 621 using the side wall 87 as a mask, and high impurity concentration regions of the source / drain regions of the LDD structure, that is, n + regions 91 and 92 are formed in a self-aligned manner. As the ion implantation conditions for the n-type impurity, for example, phosphorus (P) is implanted, and ion implantation is performed with an energy of 20 keV and a dose of 2 × 10 ¹⁵ / cm ² .

Next, as shown in FIG. 4H, a resist mask 104 is formed so that only the n-channel MOS region 631 on the region 63 side where the refractory metal silicide layer is not formed is opened and the other regions are covered. N-type impurities are ion-implanted into the n-channel MOS region 631 using the side wall 88 as a mask, and high impurity concentration regions of the source / drain regions of the LDD structure, that is, n + regions 95 and 96 are formed in a self-aligned manner. As the ion implantation conditions for the n-type impurity, for example, phosphorus (P) is implanted, and ion implantation is performed with an energy of 55 keV and a dose of 2 × 10 ¹⁵ / cm ² .

Next, as shown in FIG. 5I, a resist mask 105 is formed so that only the p-channel MOS region 622 on the region 62 side where the refractory metal silicide layer is to be formed is opened and the other regions are covered. A p-type impurity is ion-implanted into the p-channel MOS region 622 as a mask to form high impurity concentration regions of the source / drain regions of the LDD structure, that is, p + regions 93 and 94 in a self-aligned manner. The ion implantation conditions for the p-type impurity are, for example, boron (B) implantation with an energy of 7 keV and a dose of 2 × 10 ¹⁵ / cm ² .

Next, as shown in FIG. 5J, a resist mask 106 is formed so that only the p-channel MOS region 632 on the region 63 side where the refractory metal silicide layer is not formed is opened and the other regions are covered. A p-type impurity is ion-implanted into the p-channel MOS region 632 using the side wall 88 as a mask, and high impurity concentration regions of the source / drain regions of the LDD structure, that is, p + regions 97 and 98 are formed in a self-aligning manner. The ion implantation conditions for the p-type impurity are, for example, boron (B) implantation with an energy of 18 keV and a dose of 2 × 10 ¹⁵ / cm ² .

  Next, as shown in FIG. 6, a refractory metal film, such as a cobalt (Co) film, is formed on the entire surface of the substrate, and heat-treated to form on the polysilicon gate electrodes 68 and 69 and n @ + regions 91 and 92. A cobalt silicide (CoSi) layer 99 is formed on the p + regions 93 and 94 by reaction. At this time, since the cobalt (Co) film is not in contact with silicon (Si) on the region 63 side covered with the silicide block layer composed of the first insulating film 81 and the second insulating film 82, the cobalt silicide layer Does not generate. Thereafter, the excess cobalt film is removed. In this way, a CMOS transistor composed of an n-channel MOS transistor Tr1 and a p-channel MOS transistor Tr2 having a refractory metal silicide layer 99 in one region 62 is formed, and no refractory metal silicide layer is formed in the other region 63. A target semiconductor device 101 in which a CMOS transistor comprising an n-channel MOS transistor Tr3 and a p-channel MOS transistor Tr4 is formed is obtained.

  According to the semiconductor device 101 according to the present embodiment, since the MOS transistors Tr1 and Tr2 have the refractory metal silicide layer, the parasitic resistance can be reduced along with the miniaturization of the element, enabling high-speed operation and low power consumption. To. Since the MOS transistors Tr3 and Tr4 do not have a refractory metal silicide layer, junction leakage due to the refractory metal is suppressed. The transistor characteristics can be optimized by making the junction depths Xj3 and Xj4 and impurity concentrations of the MOS transistors Tr1 to Tr4 the same. Accordingly, it is possible to provide a semiconductor device 101 in which both a CMOS transistor having a refractory metal silicide layer with optimized transistor characteristics and a CMOS transistor having no refractory metal silicide are mounted.

  According to the method of manufacturing the semiconductor device 101 according to the present embodiment, the ion implantation step for forming the n + regions 91 and 92 and the p + regions 93 and 94 in the source / drain regions on the side where the refractory metal silicide layer is to be formed. And an ion implantation step for forming the n + regions 95 and 96 and the p + regions 97 and 98 of the source / drain regions on the side where the refractory metal silicide layer is not formed are separately performed by optimizing the ion implantation conditions. Yes. By selectively performing the ion implantation in this manner, the junction depth Xj3 of the source / drain regions 91 to 94 of the MOS transistors Tr1 and Tr2 having the refractory metal silicide layer and the MOS transistor having no refractory metal silicide layer are provided. The junction depth Xj4 of the source / drain regions 95 to 98 of Tr3 and Tr4 can be made the same. Further, the impurity concentration of the source / drain regions 91 to 94 of the MOS transistors Tr1 and Tr2 can be made equal to the impurity concentration of the source / drain regions 95 to 98 of the MOS transistors Tr3 and Tr4. Further, since the impurity concentrations of the source / drain regions can be made the same, in particular, the resistance of the source / drain regions 95 to 98 of the MOS transistors Tr3 and Tr4 on the side not having the refractory metal silicide layer, the source of the MOS transistors Tr3 and Tr4 The contact resistance between the drain regions 95 to 98 and the source / drain electrodes (not shown) connected thereto can be reduced to the same extent as the MOS transistors Tr1 and Tr2 on the side having the refractory metal silicide layer. .

Next, another embodiment in which the semiconductor device and the manufacturing method thereof according to the present invention are applied to a CMOS type solid-state imaging device will be described with reference to FIGS.
As shown in FIG. 7, the solid-state imaging device 111 according to the present embodiment includes an imaging region 113 in which a plurality of pixels 112 composed of a photodiode serving as a sensor unit and a plurality of MOS transistors are arranged in a matrix. The CMOS logic circuit portions 114 and 115 and the analog circuit portions 116 and 117 formed around the imaging region 113 are configured. Although the number of MOS transistors constituting the pixel 112 varies depending on the configuration of the pixel, at least the photodiode driving MOS transistor, that is, the readout MOS transistor for reading the photodiode signal charge and the photodiode signal are output. For example, a signal output MOS transistor is provided. The solid-state imaging device 111 is configured by mounting the imaging region 113, peripheral CMOS logic circuit units 114 and 115, and analog circuit units 116 and 117 on a common semiconductor substrate configured as one chip.

FIG. 8 shows a cross-sectional structure on the line AA corresponding to the CMOS logic circuit portion 114 and one pixel 112 in the imaging region 113 of FIG.
In the CMOS type solid-state imaging device 111 of the present embodiment, as shown in FIG. 8, an element isolation region 122 is formed on a common semiconductor substrate 121 of the first conductivity type, in this example n-type, A pixel 112 constituting the imaging region 113 is formed in a required region, and a CMOS logic circuit unit 114 is formed in another required region of the semiconductor substrate 121. In the MOS transistor on the pixel 112 side, a refractory metal silicide layer is not formed so as to prevent junction leakage in the source / drain region, and in the MOS transistor on the CMOS logic circuit portion 114 side, a refractory metal silicide is formed to reduce resistance. Configured to form a layer.

  The CMOS logic circuit portion 114 includes a p-type semiconductor well region 130 in which a second conductivity type, and thus a p-type impurity, is introduced over the first and second MOS transistor formation regions 125 to 126 at a deep position of the n-type semiconductor substrate 121. It is formed. An n-type semiconductor well region 131 that reaches the p-type semiconductor well region 130 from the substrate surface is formed in the first MOS transistor formation region 125. In the second MOS transistor formation region 126, a p-type semiconductor well region 132 reaching the p-type semiconductor well region 130 from the substrate surface is formed.

  On the n-type semiconductor well region 131 and the p-type semiconductor well region 132, gate electrodes 303 and 304 made of a polysilicon film are formed via a gate insulating film 133, respectively. In the n-type semiconductor well region 131, a source / drain region having an LDD structure including a p− region 313 and a p + region 323 is formed with a gate electrode 303 interposed therebetween, and a p-channel MOS transistor Tr13 is formed. In the p-type semiconductor well region 132, a source / drain region having an LDD structure composed of an n− region 314 and an n + region 324 is formed with a gate electrode 304 interposed therebetween, and an n-channel MOS transistor Tr14 is formed. The p-type channel MOS transistor Tr13 and the n-type channel MOS transistor Tr14 constitute a CMOS transistor.

  On the side walls of the gate electrodes 303 and 304 of the MOS transistors Tr13 and Tr14, a side wall 138 [135A, 135A, 135] having a first insulating film 135, a second insulating film 136, and a third insulating film 137 is formed. 136A, 137A] are formed. The first and third insulating films 135 and 137 can be formed of, for example, a silicon oxide film, and the second insulating film 136 can be formed of, for example, a silicon nitride film.

  The p − region 313 and n − region 314 constituting the source / drain regions are formed by self-alignment by ion implantation using the gate electrodes 303 and 30 as masks. The p + region 323 and the n + region 324 are formed by self-alignment by ion implantation using the sidewall 138 and the gate electrodes 303 and 304 as a mask. A refractory metal silicide layer, for example, a cobalt silicide (CoSi) layer 140 is formed on the surfaces of the gate electrodes 303 and 304 of the MOS transistors Tr3 and Tr4 and on the surface of the p + region 323 and the n + region 324 of the source / drain region. Is done. The CMOS logic circuit unit 115 side is similarly configured.

  In the pixel 112, a p-type semiconductor well region 142 in which a p-type impurity is introduced is formed in a deep position of the n-type semiconductor substrate 121 over the sensor portion formation region 123 and the MOS transistor formation region 124. Further, a p-type semiconductor well region 143 reaching the p-type semiconductor well region 142 from the surface is formed in the MOS transistor formation region 124. In the sensor portion forming region 123 surrounded by the p-type semiconductor well regions 142 and 143, an n-type semiconductor region 144 having an impurity concentration higher than that of the n-type semiconductor region 121A is formed. The n-type semiconductor region 121A is a part of the semiconductor substrate 121 separated by a p-type semiconductor well region 142 formed by ion implantation deep in the semiconductor substrate 121. A p + semiconductor region 145 having a high impurity concentration is formed on the surface of the substrate so as to be in contact with the n-type semiconductor region 144 for the purpose of reducing dark current. The p-type semiconductor well region 142, the n-type semiconductor regions 121A and 144, and the p + semiconductor region 145 form a photodiode sensor portion 146, that is, a HAD (Hole Accumulation Diode) sensor.

  On the other hand, in the MOS transistor formation region 124, gate electrodes 301 and 302 made of, for example, a polysilicon film are formed via a gate insulating film 148, and an LDD structure composed of an n− region 311 and an n + region 321 sandwiching each gate electrode. A source / drain region having an LDD structure including a source / drain region, an n− region 312 and n + regions 321 and 322 is formed. Thus, a plurality of n-channel MOS transistors, for example, a read MOS transistor Tr11 for reading signal charges of the sensor unit 146 and a signal output MOS transistor Tr12 for outputting signals are formed.

  In the region of the pixel 112, the first insulating film 135 and the second insulating film 136 are formed so as to cover the sensor unit 146 and the gate electrodes 301 and 302 of the MOS transistors Tr11 and Tr12 and the source / drain regions. Is deposited, and sidewalls 137A of the third insulating film 137 are formed on the sidewalls of the gate electrodes 301 and 302, respectively. The n − regions 311 and 312 constituting the source / drain regions are formed by self-alignment using the gate electrodes 301 and 302 as masks. The n + regions 321 and 322 are formed by self-alignment using the sidewall 137A and the gate electrodes 301 and 302 as a mask.

  On the MOS transistor Tr11, Tr12 side of the pixel 112, the refractory metal silicide layer is not formed on the gate electrodes 301, 302 and the n + regions 321 and 322.

  The n + regions 321 and 322 in the source / drain region of the pixel 112 and the p + region 323 and the n + region 324 in the source / drain region of the CMOS logic circuit unit 114 have the same depth, that is, the junction depth Xj11. It is formed.

According to the CMOS type solid-state imaging device 111 according to the present embodiment, the MOS transistors Tr13 and Tr14 in the CMOS logic circuit portions 114 and 115 have the refractory metal silicide layer 140. Reduction is achieved, enabling high-speed operation and reduction of power consumption. On the other hand, since the MOS transistors Tr11 and Tr12 constituting the pixel 112 do not have a refractory metal silicide layer, junction leakage due to the refractory metal in the MOS transistors Tr11 and Tr12 is suppressed.
Then, the junction depth Xj11 of the high concentration regions (n + region, p + region) of the source / drain regions of the MOS transistors Tr11, Tr12, Tr13, Tr14 on the pixel 112 side and the CMOS logic circuit portions 114, 115 side are made the same. By configuring the impurity concentrations, that is, the impurity concentrations of the same channel MOS transistors, to be the same, the characteristics of the MOS transistors Tr11 to Tr14 can be optimized. In particular, the parasitic resistance of the source / drain region where the refractory metal silicide layer is not formed and the contact resistance between the source / drain region and the electrode can be reduced. Therefore, a high-performance CMOS solid-state imaging device 111 can be provided.

Next, a method for manufacturing the CMOS solid-state imaging device 111 according to the above-described embodiment will be described with reference to FIGS.
First, as shown in FIG. 9A, a common silicon semiconductor substrate 121 of the first conductivity type, for example, n-type, is prepared, and an element isolation region is formed in the semiconductor substrate 121. The element isolation region 122 is formed by a field insulating film (silicon oxide film) by selective oxidation formed on the surface of the semiconductor substrate 121. In the CMOS logic circuit portion 114, an element isolation region 122 is formed so as to form a region for forming a plurality of MOS transistors, in this example, a first MOS transistor formation region 125 and a second MOS transistor formation region 126. In the imaging region, an element isolation region 122 is formed so as to form a sensor portion (photodiode) formation region 123 and a MOS transistor formation region 124 corresponding to each pixel 112.

  On the CMOS logic circuit portion 114 side, a p-type semiconductor well region 130 of the second conductivity type and the same impurity concentration is formed deep in the MOS transistor formation regions 125 and 126. Further, in the second MOS transistor formation region 126, a p-type semiconductor well region 132 reaching the p-type semiconductor well region 130 from the substrate surface is formed. In the first MOS transistor formation region 125, an n-type semiconductor well region 131 surrounded by p-type semiconductor well regions 130 and 132 is formed.

On the pixel 112 side, a p-type semiconductor well region 142 is formed deep in the n-type semiconductor substrate 121. Further, in the MOS transistor formation region 124, a p-type semiconductor well region 143 reaching the p-type semiconductor well region 142 from the substrate surface is formed. In the sensor portion formation region 123, an n-type semiconductor well region 112A surrounded by the p-type semiconductor well regions 142 and 143 is formed, and an n + semiconductor region 144 having a high impurity concentration is formed on the surface of the region 112A.
The semiconductor well regions and the semiconductor regions described above are selectively formed by ion implantation.

  Further, as shown in FIG. 9A, in the same process, the gate insulating film 133 is formed on the substrate surface of the first and second MOS transistor formation regions 125 and 126 on the CMOS logic circuit portion 114 side, and the sensor portion on the pixel 112 side. A gate insulating film 148 is formed on the substrate surface of the formation region 123 and the MOS transistor formation region 124, respectively. Next, in the same process, gate electrodes 303 and 304 made of polysilicon films are formed on the gate insulating film 124 in the first and second MOS transistor formation regions 125 and 126 on the CMOS logic circuit side, and the MOS on the pixel 112 side is formed. Gate electrodes 301 and 302 are formed on the gate insulating film 148 in the transistor formation region 124. Next, with respect to the MOS transistor formation region 124 on the pixel side and the second MOS transistor formation region 126 on the CMOS logic circuit portion side, the LDD structure is formed in a self-aligned manner by ion implantation using each gate electrode 301, 302, 304 as a mask. Low concentration regions constituting the source / drain regions, that is, n − regions 312, 314 are formed.

  Next, as illustrated in FIG. 9B, the first insulating film 135 and the second insulating film 136 are sequentially formed on the entire surface including the tops of the gate electrodes 301 to 304 over the pixel 112 and the CMOS logic circuit unit 114 by, for example, the CVD method. accumulate. The first insulating film 135 is formed of, for example, a silicon oxide film, and the second insulating film 136 is formed of, for example, a silicon nitride film. As will be described later, the first and second insulating films 135 and 136 serve as a silicide block layer for preventing a silicide reaction on the pixel side.

  Next, as shown in FIG. 10C, after a resist mask 151 is selectively formed on the pixel 112 side, the first and second insulating films 135 and 136 on the CMOS logic circuit portion 114 side are etched by anisotropic etching. Then, a two-layer side wall 152 is formed by both insulating films 135 and 136 on the side walls of the gate electrodes 303 and 304.

  Next, as shown in FIG. 10D, after removing the resist mask 151, a third insulating film 137 is deposited on the entire surface including the pixel 112 side and the CMOS logic circuit portion 114 side by, eg, CVD. The third insulating film 137 is formed of, for example, a silicon oxide film. Next, the third insulating film 137 is etched back by anisotropic etching. At this time, a single-layer side wall 137A is formed of the third insulating film 137 on the second insulating film 136 corresponding to the side walls of the gate electrodes 301 and 302 on the pixel 112 side. Further, a three-layer sidewall 138 is formed by the first, second and third insulating films 135A, 136A and 137A on the sidewalls of the gate electrodes 303 and 304 on the CMOS logic circuit portion 114 side.

  Next, as shown in FIG. 11E, for example, an n-channel MOS transistor region on the CMOS logic circuit portion 114 side, for example, only the second MOS transistor formation region 126 is opened, and all other regions are covered. Such a resist mask 153 is selectively formed. High-concentration n-type impurities are ion-implanted into the second MOS transistor formation region 126 through the resist mask 153. As a result, the gate electrode 304 and the sidewall 138 are used as a mask to form a high impurity concentration region, that is, an n + region 324 constituting the source / drain region of the LDD structure on the substrate surface in a self-aligned manner.

  Next, as shown in FIG. 11F, the resist mask 153 is removed, and a region where a new n-channel MOS transistor on the pixel 112 side is to be formed, only the MOS transistor formation region 124 is opened, and all other regions are opened. A resist mask 154 is selectively formed so as to be coated. High concentration n-type impurities are ion-implanted into the MOS transistor formation region 124 through the resist mask 154. As a result, high impurity concentration regions constituting the source / drain regions of the LDD structure, that is, n + regions 321 and 322 are formed on the substrate surface in a self-aligned manner using the gate electrodes 301 and 302 and the sidewalls 137A as a mask. At this time, the ion implantation conditions are optimized so that the junction depth Xj11 and impurity concentration of the n + regions 321 and 322 are the same as the junction depth and impurity concentration of the n + region 324 on the CMOS logic circuit portion side.

  Next, as shown in FIG. 12G, the resist mask 154 is removed, and only a region where a p-channel MOS transistor on the CMOS logic circuit side is to be newly formed, in the figure, only the first MOS transistor formation region 125 is opened, A resist mask 155 is formed so as to cover all other regions. High concentration p-type impurities are ion-implanted into the MOS transistor formation region 125 through the resist mask 155. As a result, a high impurity concentration region, that is, a p + region 323 constituting the source / drain region of the LDD structure is formed on the substrate surface in a self-aligning manner using the gate electrode 303 and the sidewall 138 as a mask.

  Next, as shown in FIG. 12H, the resist mask 155 is removed, and a resist mask 156 that newly opens only the sensor portion formation region 123 of the pixel 112 and covers all other regions is formed. High concentration p-type impurities are ion-implanted into the sensor portion formation region 123 through the resist mask 156. Thereby, a p + semiconductor region 145 is formed on the surface of the n + semiconductor region 144 of the sensor portion. The p + semiconductor region 145, the n + semiconductor region 144, the n semiconductor region 121A, and the p semiconductor well region 142 constitute an HAD sensor.

  Next, as shown in FIG. 13, a refractory metal, for example, a cobalt (Co) film is formed on the entire surface of the substrate, and heat-treated to form a polysilicon film on the CMOS logic circuit portion side over the gate electrodes 303 and 304 and the source A cobalt silicide (CoSi) layer 140 is formed by reaction on the high concentration regions (n + region, p + region) 323 and 324 of the drain region. At this time, since the cobalt (Co) film is not in contact with silicon (Si) in the pixel-side MOS transistor formation region 124 covered with the silicide block layer made of the first and second insulating films 135 and 136, A cobalt silicide layer is not formed. Thereafter, the excess cobalt film that does not react is removed. In this manner, n-channel MOS transistors Tr11 and Tr12 having no refractory metal silicide layer are formed in the MOS transistor formation region 124 on the pixel 112 side, and the refractory metal silicide layer 140 is provided on the CMOS logic circuit portion 114 side. A target CMOS type solid-state imaging device 111 is obtained, in which a CMOS transistor including a p-channel MOS transistor Tr13 and an N-channel MOS transistor Tr14 is formed.

  According to the manufacturing method of the CMOS type solid-state imaging device 111 according to the present embodiment, the p + region and the n + region of the source / drain region for forming the refractory metal silicide layer 140 on the CMOS logic circuit portions 114 and 115 side are formed. The ion implantation process for forming the n + regions of the source / drain regions where the refractory metal silicide layer on the pixel 112 side is not formed is separately performed with the ion implantation conditions optimized. By selectively performing the ion implantation process in this manner, the high-concentration regions (p + region, n + region) of the source / drain regions of the MOS transistors Tr13 and Tr14 having the refractory metal silicide layer 140 on the CMOS logic circuit side are obtained. The junction depth Xj11 of the high concentration region (n + region) of the source / drain regions of the MOS transistors Tr11, Tr12 having no refractory metal silicide layer on the pixel side can be made the same. Further, the impurity concentrations of the MOS transistors Tr13 and Tr14 and the MOS transistors Tr11 and Tr12, that is, the impurity concentrations of the same channel MOS transistors can be made the same. Further, by making the impurity concentration of each high concentration region (p + region, n + region) the same, the parasitic resistance of the source / drain regions of the MOS transistors Tr11, Tr12 not having the refractory metal silicide layer on the pixel 112 side, The contact resistance between the source / drain regions and the source / drain electrodes connected thereto can be reduced to the same extent as the MOS transistors Tr13 and Tr14 on the CMOS logic circuit portions 114 and 115 side. Therefore, it is possible to manufacture a CMOS type solid-state imaging device in which the transistor characteristics of each MOS transistor are optimized.

  In the above-described embodiment, the present invention is applied to a semiconductor device mounted with a CMOS transistor and a CMOS solid-state imaging device, but the present invention is not limited to this. For example, in the present invention, as shown in FIG. 14, a DRAM cell 162 in which one memory cell is composed of a MOS transistor and a capacitor, CMOS logic circuit portions 163 and 164 and analog circuit portions 165 and 166 around the DRAM cell 162, The present invention can also be applied to a semiconductor device 161 in which a semiconductor device 161 is integrated, that is, a so-called DRAM embedded logic semiconductor integrated circuit (LSI). In this case, the refractory metal silicide layer is not formed on the MOS transistor on the DRAM cell 162 side, but the refractory metal silicide layer is formed on the CMOS transistor on the CMOS logic circuit portions 163 and 164 side. Also in this DRAM-embedded logic LSI 161, the characteristics of each MOS transistor with or without a refractory metal silicide layer can be optimized, and high performance can be achieved.

1A and 1B are sectional views (part 1) in the order of a manufacturing process showing an embodiment of a semiconductor device and a manufacturing method thereof according to the present invention. C, D It is sectional drawing (the 2) of the order of a manufacturing process which shows one Embodiment of the semiconductor device which concerns on this invention, and its manufacturing method. E, F It is sectional drawing (the 3) of the order of a manufacturing process which shows one Embodiment of the semiconductor device which concerns on this invention, and its manufacturing method. G and H are cross-sectional views (part 4) in the order of the manufacturing steps showing an embodiment of the semiconductor device and the manufacturing method thereof according to the present invention. I, J It is sectional drawing (the 5) of the order of a manufacturing process which shows one Embodiment of the semiconductor device which concerns on this invention, and its manufacturing method. It is sectional drawing (the 6) of the order of a manufacturing process which shows one Embodiment of the semiconductor device which concerns on this invention, and its manufacturing method. It is a schematic block diagram which shows embodiment which applied the semiconductor device based on this invention to the CMOS type solid-state imaging device. It is sectional drawing of the principal part on the AA line of FIG. A, B It is a manufacturing process figure (the 1) so that embodiment of the manufacturing method of the CMOS type solid-state imaging device concerning this invention may be shown. C and D are manufacturing process diagrams (part 2) showing the embodiment of the manufacturing method of the CMOS type solid-state imaging device according to the present invention. E and F are manufacturing process diagrams (part 3) showing the embodiment of the manufacturing method of the CMOS type solid-state imaging device according to the present invention. G and H are manufacturing process diagrams (part 4) showing the embodiment of the manufacturing method of the CMOS type solid-state imaging device according to the present invention. FIG. 10 is a manufacturing process diagram (part 5) illustrating the embodiment of the method for manufacturing the CMOS solid-state imaging device according to the present invention; 1 is a schematic configuration diagram showing an embodiment in which a semiconductor device and a manufacturing method thereof according to the present invention are applied to a DRAM embedded logic semiconductor integrated circuit. FIGS. 9A and 9B are manufacturing process diagrams (part 1) illustrating a method for manufacturing a semiconductor device according to a comparative example; FIGS. FIG. 6C is a manufacturing process diagram (part 2) illustrating the method for manufacturing the semiconductor device according to the comparative example; E, F is a manufacturing process diagram (part 3) illustrating the method for manufacturing the semiconductor device according to the comparative example; FIG. 6G is a manufacturing process diagram (part 4) illustrating the method for manufacturing the semiconductor device according to the comparative example; FIGS. 9A and 9B are manufacturing process diagrams illustrating a method for manufacturing a semiconductor device according to a reference example; FIGS.

Explanation of symbols

  61..Semiconductor substrate 62..First region 63..Second region 66..Element isolation region 64.65..p-type semiconductor well region 67..Gate insulating film 68-71 · Gate electrode, 72, 73 · · n-type semiconductor region, 75 to 78 · · LDD low impurity concentration region (n-region, p-region), 81 · · first insulating film, 82 · · · second Insulating film, 84 .. side wall, 86... Third insulating film, 87, 88 .. side wall, 103 to 106 .. resist mask, 91 to 98 .. LDD high impurity concentration region (p region, p + Area), 99 .. refractory metal silicide layer, 101... Semiconductor device, 111... CMOS type solid-state imaging device, 112... Pixel, 113 .. imaging area, 114, 115. 117 .. Analog circuit part 121..Semiconductor substrate 121A..n Semiconductor substrate 122..Element isolation region 123..Sensor portion forming region 124.about.126 MOS transistor forming region 130..Semiconductor well region 133.148. .. Gate insulating film, 135... First insulating film, 136... Second insulating film, 137... Third insulating film, 137 A, 138 .. Side wall, 144... N + semiconductor region, 145. .. p + semiconductor region, 311, 312, 313, 314... LDD low impurity concentration region, 321, 322, 323, 324... LDD high impurity concentration region, Tr 11 to Tr 14.

Claims (10)

A first field effect transistor in which a silicide layer is formed on a semiconductor substrate; and a second field effect transistor in which no silicide layer is formed;
A depth of the source / drain region of each of the first field effect transistor and the second field effect transistor is set to be equal. The semiconductor device according to claim 1, wherein a silicide block layer for preventing a silicide reaction is formed in the second field effect transistor. A first field effect transistor constituting a logic circuit is formed in the first region, and an imaging region having a pixel including a second field effect transistor in which a silicide layer is not formed and a sensor portion is formed in the second region. ,
The first field effect transistor includes a field effect transistor having a silicide layer formed thereon,
The depths of the source / drain regions of the first field effect transistor and the second field effect transistor are set to be equal,
A semiconductor device characterized by being used as a CMOS type solid-state imaging device. The semiconductor device according to claim 3, wherein a silicide block layer for preventing a silicide reaction is formed in the field effect transistor in which no silicide layer is formed. Without forming a silicide block layer that inhibits the silicide reaction in the first region where the first field effect transistor having the silicide layer is formed;
Forming the silicide block layer in a second region where a second field effect transistor having no silicide layer is formed;
Forming a source / drain region by selectively introducing impurities by ion implantation through a mask selectively formed in the first region and the second region;
Forming a silicide layer on the first field effect transistor. A method for manufacturing a semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the ion implantation conditions for the first region and the second region are different from each other. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the implantation energy for the ion implantation into the second region is set to be larger than the implantation energy for the ion implantation into the first region. . In the first region where the first field effect transistor constituting the logic circuit is formed, without forming a silicide block layer for blocking the side reaction in the region where the field effect transistor having the silicide layer is formed,
Forming the silicide block layer in an imaging region in which a pixel including a second field effect transistor having no silicide layer and a sensor portion is formed;
In the first region and the second region, an impurity is selectively introduced by ion implantation into a region where the silicide layer is not formed and a region where the silicide layer is formed through a mask, respectively. A step of forming a drain;
A method of manufacturing a semiconductor device, comprising: forming a silicide layer on a field transistor on which a silicide layer of the first field transistor is to be formed. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the ion implantation conditions for the first region and the second region are different from each other. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the implantation energy of the ion implantation into the second region is set larger than the implantation energy of the ion implantation into the first region. .

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