JP2005222692A - Inspection device for semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inspection device of a semiconductor memory, which readily compensates for errors produced in data when failures generate in the semiconductor memory 703, and operates as a desired RAM, even if the failures are present in data input/output. <P>SOLUTION: The semiconductor memory 703 is tested by a test circuit 702, each test result of plurality of digits is held by a data-holding means 706 in the test circuit 702, and the digit of the defective data, concerning the failures in the semiconductor memory 703, is designated. Based on the designation, the errors produced in the data are compensated by a redundant circuit 704. Errors produced in the data, when the failures generated in semiconductor memory 703, are compensated readily, and operation as a desired RAM, even if the failures are present in the data input/output, is performed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an inspection apparatus that performs a function test on a semiconductor memory as a logic integrated circuit including a plurality of RAMs, ROMs, and the like.

{First Conventional Example}
FIG. S. It is a circuit diagram showing a scan register 414a of a semiconductor memory inspection device of a first conventional example of a two-phase clock method shown in Patent: 4,926,424. In FIG. 22, 401a and 401b are latch circuits, 402 is a selector circuit, 408 is a selector control terminal, 409 is a serial input terminal, 410 is a parallel input terminal, 411 is a parallel output terminal, and 412 is a serial output terminal. Reference numerals 415 and 416 denote two-phase clock terminals, 419 denotes an exclusive NOR circuit (hereinafter referred to as ex.NOR circuit), 420 denotes a NOR circuit, 421 denotes an OR circuit, and 422 denotes a test clock terminal.

  Next, the operation will be described. When the test clock terminal 422 is fixed to the “H” level, the output of the NOR circuit 420 becomes the “L” level, so that the OR circuit 421 transmits the level of one clock terminal 415 to the enable terminal EN of the latch circuit 401 a as it is. Therefore, in this case, by supplying a two-phase clock signal to both clock terminals 415 and 416, the data supplied to the serial input terminal 409 or the parallel input terminal 410 is transmitted to the serial output terminal 412 and the parallel output terminal 411. Can do.

  On the other hand, in a read test of a circuit under test such as a RAM, expected data is set in the latch circuit 401a and the latch circuit 401b, and a clock signal is supplied to the test clock terminal 422 in this state, whereby the data at the parallel input terminal 410 is stored. Only when the data is different from the expected data, the data of the parallel input terminal is latched in the latch circuit 401a, and the contents of the latch circuit 401a are inverted.

  That is, when data different from the expected data is read from the test circuit such as the RAM and applied to the parallel input terminal 410, the data different from the expected data is latched in the latch circuit 401a. It can be known from the latched data that there is an abnormality in the circuit under test such as RAM.

  FIG. 23 is a block diagram showing a scan path configured by the scan register 414a shown in FIG.

{Second Conventional Example}
FIG. 57 shows a semiconductor memory inspection device of a second conventional example (see Japanese Patent Laid-Open No. 62-195572, US Patent: 4,813,043). In the second conventional example, a pseudorandom number (pseudorandom sequence) generating algorithmic pattern generating circuit (linear feedback shift register circuit: hereinafter referred to as LFSR circuit) is used as such an inspection apparatus. In FIG. 57, 501 is a base data register for storing reference data, 502 is a constant register for supplying constants when performing constant operations, and 503 is an arithmetic logic operation for performing various arithmetic logic operations with a shift-in function. A unit (ALU) 504 is a selector for selecting the input of the ALU 503, 505 is an ALU output register for holding the operation result of the ALU 503, 506 is a bit selection register, 507 is an AND operation circuit, and 508 is a parity detection circuit.

  FIG. 58 is a logic circuit diagram showing an example of a 4-bit LFSR circuit. In FIG. 58, reference numeral 509 denotes an exclusive OR (Ex.OR) circuit, 510, 511, 512, and 513 denote flip-flop circuits, and CLK denotes a click signal input terminal. The exclusive OR circuit 509 corresponds to the parity detection circuit 508 in FIG. 57, and the flip-flop circuits 510, 511, 512, and 513 correspond to the ALU output register 505 in FIG. 58, the exclusive OR circuit 509 is input from two flip-flop circuits 510 and 513. This is because 1001 (binary system) is selected for the bit selection register 506 in FIG. It corresponds to that.

In the LFSR circuit of the second conventional example having such a configuration, parity detection is performed on an arbitrary bit group of the ALU output register 505, and the detection result is shifted into the ALU 503 at the same time as the arithmetic operation in the ALU 503. 505 is updated, and a complicated pseudo random number pattern is generated at high speed. Here, in the LFSR circuit of the second conventional example, 2 ⁿ pseudorandom numbers (pseudorandom series) are generated as an algorithmic pattern for function test.

  The operation in the case where the LFSR circuit of the second conventional example is used as the address generation circuit and the test data of the whole period series is used for address setting of a plurality of RAMs will be described with reference to FIG. FIG. 59 shows an address input system. 59, 521a to 521c are RAMs, 522a to 522c are shift registers for selecting the addresses of the RAMs 521a to 521c at the time of a function test of the RAMs 521a to 521c, and 523 includes an LFSR circuit (address generation circuit) of the second conventional example. The test pattern generation circuit, SIA, is a common wiring for transmitting addressing data to all the shift registers 522a to 522c. As shown in FIG. 59, a plurality of RAMs 521a to 521c are connected to one test pattern generation circuit 523. A0 to A4 are address input terminals of the RAMs 521a to 521c. The RAM 521a is a four-terminal input, the RAM 521b is a five-terminal input, and the RAM 521c is a four-terminal input.

  In the function test of the RAMs 521a to 521c, the test pattern generation circuit 523 first outputs address designation data to the common wiring SIA. The shift registers 522a to 522c connected in common to the common wiring SIA are shifted in by the addressing data to be transmitted, and select the addresses of the RAMs 521a to 521c.

  Here, for the RAMs 521a and 521c having the four address input terminals A0 to A3, the test pattern generation circuit 523 generates a quaternary full cycle sequence, and based on this, the addresses of the RAMs 521a and 521c are set. Do. Similarly, for the RAM 521b having five address input terminals A0 to A4, the test pattern generation circuit 523 generates a fifth-order full cycle sequence, and the address setting of the RAM 521b is performed based on this.

{Third conventional example}
The third conventional semiconductor memory testing apparatus increments or decrements addresses by an address generation circuit. That is, as shown in FIG. 59, a common counter as a separate member is connected to the same test pattern generation circuit (LFSR circuit) 523 as in the second conventional example, and redundant operation is achieved by the cooperative operation of the counter and the LFSR circuit 523. Cancel bit.

{Fourth conventional example}
FIG. 132 shows a fourth conventional semiconductor memory inspection apparatus. The semiconductor memories (RAM1, RAM2, and RAM3) in FIG. 132 each have a data output scan path DO (scan FF with a data compression function), and the output from the scan path DO of the preceding semiconductor memory is subsequent. Input to the semiconductor memory. The test result at the time of the test is performed by the shift operation of each scan path. For each of such semiconductor memories, when it is desired to compress data in the test, an SINH signal (shift prohibition signal) is input to prohibit the shift operation of the scan path DO.

{Fifth conventional example}
FIGS. 157 and 158 are diagrams showing a redundant circuit of a fifth conventional example. The redundant circuit includes a plurality of signal lines L1 to L4 to which a plurality of memory cells C are connected, and a decoder (not shown) connected to the plurality of signal lines L1 to L4. Are provided with at least one spare signal line L5 connected thereto. In addition, D1 to D4 in FIGS. 157 and 158 are drive circuits connected to the decoder.

  In FIG. 157 and FIG. 158, S denotes a switch unit, and S1 to S4 denote individual switching elements in the switch unit S. Transistors are often used as the switching elements S1 to S4. Among these, the first switching element S1 is provided between the drive circuit D1 and the first signal line L1 when the first signal line L1 among the plurality of signal lines L1 to L4 is defective. And the driving circuit D1 to the first signal line L1 of the decoder is connected to the second signal line L2 adjacent to the first signal line L1. The second switching element S2 is provided between the drive circuit D2 and the second signal line L2 when the second signal line L2 among the plurality of signal lines L1 to L4 is defective. The connection is disconnected, and the driving circuit D2 to the second signal line L2 of the decoder is connected to the third signal line L3 adjacent to the second signal line L2. Similarly, the third switching element S3 is provided between the drive circuit D3 and the third signal line L3 when the third signal line L3 among the plurality of signal lines L1 to L4 is defective. And the drive circuit D3 to the third signal line L3 of the decoder is connected to the fourth signal line L4 adjacent to the third signal line L3. Further, the fourth switching element connects the remaining drive circuit D4 of the decoder to the spare signal line L5.

  In such a configuration, a plurality of defective signal lines L1 to L4 are sequentially connected from a spare spare signal line L5 to a plurality of adjacent signal lines, whereby any defective signal lines L1 to L1 are connected. L4 can be removed.

{Problems of the first conventional example}
Since the two-phase clock type semiconductor memory inspection device of the first conventional example is configured as described above, it is necessary to supply a two-phase clock signal to the pair of clock terminals 415 and 416. When a circuit under test such as the above is tested at a high speed, there has been a problem that a clock driver circuit capable of complicated driving for supplying a high-speed two-phase clock signal to the pair of clock terminals 415 and 416 is required.

  SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a semiconductor memory inspection apparatus that can eliminate the need for a complicated clock driver circuit for supplying a two-phase clock signal, that is, can be driven by a one-phase clock signal. .

{Problem of the second conventional example}
Usually, for example, there is a march test as a function test used for testing a RAM or the like. In this test, all address designation data in all RAMs are updated from initial storage data (for example, “0”) which is an initial state to new storage data (“1”). In the case of such a march test, it is necessary to specify an address of a RAM to be updated. In the second conventional example, in order to specify the RAM address, the LFSR circuit of the test pattern generation circuit 523 generates 2 ⁿ total periodic sequences of pseudo-random numbers as described above. The number n is undetermined depending on the type of RAM, for example, four in the case of the RAM 521a in FIG. 59 and five in the case of the RAM 521b. Therefore, the number of words 2 ⁿ determined by the combination of the binary number (“0”, “1”) of the address number n is also undetermined. For this reason, if the 2 ^{n -th} complete periodic sequence generated in the LFSR circuit is smaller than the actual number of words in the RAM, a word that cannot be subjected to the function test will be generated. On the other hand, if the 2 ^{n -th} complete cycle sequence generated by the LFSR circuit is larger than the actual number of words in the RAM, even if the full cycle sequence is generated, a part of the data protrudes from the shift register and the wrong address is recognized. There was a risk of being. That is, in the case of the second conventional example, the number ²ⁿ of all periodic sequences generated in the LFSR circuit must completely match the number of words in the RAM, and the degree of freedom of the RAM for function testing is limited. There was a drawback.

  In view of the above problems, an object of the present invention is to provide a semiconductor memory inspection apparatus capable of testing a RAM having an arbitrary number of words when performing a function test of a plurality of RAMs.

  Also, when performing a RAM functional test, it is necessary to burn in while moving all addresses, bits, etc. (dynamic burn-in). However, when there are a large number of connected RAMs for performing functional tests, generally, burn-in testers often cannot generate complex control signals, and initial setting of bit line selection registers and the like necessary before test pattern generation cannot be performed.

  An object of the present invention is to provide a semiconductor memory inspection device capable of initial setting of a bit line selection register or the like necessary before test pattern generation.

{Problem of the third conventional example}
The mismatch in the number of bits, which has been a problem in the second conventional example, can be solved by canceling redundant bits by the cooperative operation of the counter and the LFSR circuit 523 if configured as in the third conventional example. . However, in general, the counter has a larger area size than the LFSR circuit 523, and it is difficult to integrate the counter in a single integrated circuit, and the counter is externally provided with the address bus outside. Therefore, not only an area for the counter is required, but also a wiring mechanism such as an address bus is required, which is a factor of greatly reducing the area efficiency.

  The present invention has been made in view of the above problems, and it is another object of the present invention to provide an inspection apparatus for a semiconductor memory having a small area.

{Problem of Fourth Conventional Example}
In the fourth conventional example, since the same SINH signal is supplied to a plurality of scan paths DO, the SINH signal is always supplied to a plurality of semiconductor memories. As a result, high speed operation cannot be performed due to the impossibility of capacity, which has been the limit for improving test efficiency.

  SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a semiconductor memory inspection apparatus capable of testing a built-in RAM core at high speed.

{Problem of the fifth conventional example}
In the fifth conventional example, after the signal lines L1 to L4 in which defects are generated are found, the switching elements S1 to S4 are disconnected using a laser device or the like, and the connection of a driver such as writing is disconnected. However, the apparatus for cutting becomes larger, and the cost increases accordingly.

  An object of the present invention is to provide an inspection apparatus for a semiconductor memory that can reduce the size of the apparatus and reduce the cost.

According to a first aspect of the present invention, there is provided a problem solving means comprising: a test circuit having a data holding means for carrying out a test of a semiconductor memory and holding a test result of a plurality of digits of the semiconductor memory; and And a redundant circuit that compensates for an error that occurs in the data when a failure occurs in the semiconductor memory based on a result, and the redundant circuit is connected to each of a plurality of digits of data in the semiconductor memory. Among the plurality of signal lines, a digit designated as a defective bit according to a test result held by the data holding means of the test circuit, among the plurality of signal lines. Binary signal specification that outputs one of the two values for the signal line on one side of the signal line corresponding to the signal line and outputs the other value of the two values for the signal line on the other direction side Department and Based on the binary signal from the binary signal designating unit, disconnect the signal line corresponding to the digit designated to be a defective bit, and switch and connect the signal line at the end to the spare line. And a selector group for sequentially switching and connecting the signal lines to the signal lines adjacent to the other signal lines.

  In the problem solving means according to claim 2 of the present invention, the data holding means scans and outputs the result of the test.

  According to a third aspect of the present invention, there is provided the problem solving means, wherein the redundant circuit has a bit write control signal output terminal for outputting a signal for controlling writing for each data bit to the semiconductor memory. In response to a signal given from the bit write control signal output terminal of the redundant circuit, writing of a digit designated as a defective bit is suppressed.

  According to a fourth aspect of the present invention, there is provided the problem solving means, wherein the data holding means holds one of the two values corresponding to the digit of the defective data and the binary corresponding to the other digit. Is a binary data holding means for designating a digit of defective data related to a failure in the semiconductor memory by holding the other value, and the binary signal designating unit is a plurality of digits of data in the semiconductor memory. And one input terminal of the plurality of AND circuits is connected to a corresponding digit of the binary data holding means, respectively, and the other inputs of the plurality of AND circuits The terminals are sequentially connected to the output terminal of the AND circuit adjacent to one of the large digit side and the small digit side of the AND circuit.

  In the problem solving means according to claim 5 of the present invention, the redundant circuit inactivates the bit write control signal output terminal of the digit corresponding to the defective bit.

  In the semiconductor memory inspection apparatus according to the present invention, the test of the semiconductor memory is performed by the test circuit, and the result of each test of a plurality of digits is held in the holding unit, and the digit of the defective data related to the failure in the semiconductor memory is designated. As a result, an error occurring in the data is compensated by the redundant circuit, so that an error occurring in the data when the failure occurs in the semiconductor memory can be easily compensated, and a failure occurs in the data input / output. Even if it exists, it can operate as a desired RAM.

{Embodiment 1}
<Configuration>
FIG. 1 is a logic circuit diagram showing a semiconductor memory (RAM) inspection device (test auxiliary circuit) according to the first embodiment of the present invention. In FIG. 1, reference numeral 231 denotes a scan register, which, like the first conventional example shown in FIG. 23, forms a scan path by connecting a plurality of scan registers 231 in series. While the data input from the integrated circuit device is output to an external circuit, at the time of data comparison, the data input from the semiconductor integrated circuit device is compared with the expected data, and when they do not match, the data from the semiconductor integrated circuit device is compared. The fact that the data has failed is output to an external circuit. In FIG. 1, 232 is a comparison circuit, 233 is a selector circuit (selector means), 234 is a flip-flop circuit with a reset function, and 235 is an OR circuit.

  The comparison circuit 232 includes one exclusive OR circuit (hereinafter referred to as “Ex.OR circuit”) 241, one NOT circuit 242, and one NAND circuit 243. Ex. The OR circuit 241 has a pair of input terminals. A data input signal (D) from the semiconductor integrated circuit device (not shown) is input to one input terminal, and the data input is input to the other input terminal. An expected data signal (EXP) from the outside for comparing and checking whether the signal (D) is normal is input. An external clock signal (T) is input to the input terminal of the NOT circuit 242. The NAND circuit 243 has three input terminals. One input terminal receives an external comparison enable signal (CMPEN), and the other input terminal receives the Ex. The other output terminal is connected to the output terminal of the NOT circuit 242, and is connected to the output terminal of the OR circuit 241. As a result, the comparison circuit 232 inputs the expected data signal (EXP) from the outside and the data input from the outside only when the comparison enable signal (CMPEN) from the outside is High and the clock signal (T) is Low. The signal (D) is compared and set to output Low when they are different.

  The selector circuit 233 includes a pair of signal input terminals “0” and “1” to which the data input signal (D) from the semiconductor integrated circuit device and a serial input signal (SI) from the outside are input, and an external One of the signal input terminals based on the shift mode control signal (SM) from the outside during normal operation and test mode. “0” (data input signal (D)) is selected, and the other signal input terminal “1” (serial input signal (SI)) side is selected based on the shift mode control signal (SM) in the shift mode. Is set as follows.

  The flip-flop circuit 234 has a data input terminal D1, a data output terminal O1, a timing signal input terminal T1, and a reset input terminal R1, and when the timing signal is input to the timing signal input terminal T1, the data Data is fetched from the input terminal D1, the data (SO.Q) is transmitted to the data output terminal O1, and the fetched data is reset when a low level reset signal is inputted to the reset input terminal R1. Is set. Here, the flip-flop circuit 234 is of a type that captures data at the rising edge of the timing signal input to the timing signal input terminal T1 (positive edge trigger type). In this embodiment, the data whose data becomes “0” by the reset operation is used, but the data whose data becomes “1” may be used. Here, the data output terminal O1 is connected to the signal input terminal of the flip-flop circuit of the next-stage scan register, and is transmitted as a serial input signal (SO.Q = SI).

  The OR circuit 235 outputs a timing signal for defining a predetermined timing of the shift operation to the flip-flop circuit 234, and has a pair of input terminals and one output terminal. The clock signal (T) is input to the terminal, an external shift inhibition signal (SINH) is input to the other input terminal, and the one output terminal is connected to the timing signal input terminal T1 of the flip-flop circuit 234. It is connected. Thus, the OR circuit 235 allows the flip-flop circuit 234 to capture data in accordance with a periodic clock signal (T) from the outside when the shift prohibit signal (SINH) is not input from the outside, while the shift circuit A timing stop circuit that holds the data of the flip-flop circuit 234 by stopping the timing signal that defines the predetermined timing regardless of the input of the clock signal (T) when the inhibition signal (SINH) is input. It functions as (data holding means).

<Operation>
The operation of the scan register 231 having the above configuration will be described. FIG. 2 is a timing chart showing an operation for taking in data at the data input terminal D when the scan register 231 is used as an output flip-flop of a semiconductor integrated circuit device (RAM) during normal operation. As shown in FIG. 2, when the shift inhibition signal (SINH) is Low, the clock signal (T) is directly transmitted to the timing signal input terminal T1 of the flip-flop circuit 234 via the OR circuit 235. When the comparison enable signal (CMPEN) is Low as shown in FIG. 2, the output of the NAND circuit 243 of the comparison circuit 232 is always High and no reset signal (Low signal) is generated. If the shift mode control signal (SM) is Low at the rising edge of the clock signal (T), the selector circuit 233 selects the signal input terminal “0” and the data input signal (RAM) from the semiconductor integrated circuit device (RAM). D) is taken into the flip-flop circuit 234.

  FIG. 3 shows the shift operation of the flip-flop circuit 234 at the time of initial setting (setting “1”) before starting the test of the semiconductor integrated circuit device (RAM) and reading of the test result after the RAM test is completed. It is a timing chart which shows. As shown in FIG. 3, when the shift inhibition signal (SINH) is Low, the clock signal (T) is transmitted through the OR circuit 235 to the timing signal input terminal T1 of the flip-flop circuit 234 as it is. Further, when the comparison enable signal (CMPEN) is Low, the reset signal (Low signal) is not generated from the comparison circuit 232. If the shift mode control signal (SM) is High when the clock signal (T) rises, the selector circuit 233 selects the signal input terminal “1”, and the serial input signal (SI) is taken into the flip-flop circuit 234. And output to the data output terminal O1 (serial output terminal). The data output terminal O1 is connected to the signal input terminal (“1”) of the next-stage scan register (see FIG. 23), and data transmission is performed as a serial input signal (SO.Q = SI) to perform a shift operation. .

  FIG. 4 is a timing chart showing an operation of prohibiting the shift operation of the flip-flop circuit 234 when the comparison operation should not be performed, for example, when the output data of the RAM is indefinite. As shown in FIG. 4, when the shift inhibition signal (SINH) is High, the OR circuit 235 always outputs High, and therefore the clock signal (T) is not transmitted to the timing signal input terminal T1 of the flip-flop circuit 234. Therefore, the flip-flop circuit 234 cannot detect the rising edge of the clock signal (T), and therefore the shift operation is not performed. Also, as shown in FIG. 4, when the comparison enable signal (CMPEN) is Low, the reset signal (Low signal) is not generated from the comparison circuit 232. The shift mode control signal (SM) at the rising edge of the clock signal (T) may be either High / Low.

  FIG. 5 is a timing chart showing the comparison operation of the comparison circuit 232. As shown in FIG. 5, when the shift inhibition signal (SINH) is High, the OR circuit 235 always outputs High, and therefore the clock signal (T) is not transmitted to the timing signal input terminal T1 of the flip-flop circuit 234. Therefore, the flip-flop circuit 234 cannot detect the rising edge of the clock signal (T), and therefore the shift operation is not performed. When the clock signal (T) is Low and the comparison enable signal (CMPEN) is High, if the data at the data input terminal D and the expected data terminal (EXP) are different, the comparison circuit 232 outputs a reset signal (Low signal). Occurs, and the flip-flop circuit 234 is reset to "0". Since the flip-flop circuit 234 is set to “1” by the initial shift operation, the presence of a failure is stored by changing this to “0”. Data indicating the presence or absence of a failure held in the scan register 231 is read out by a shift operation after the RAM test is completed.

  According to the present embodiment, the data in the flip-flop circuit 234 is rewritten according to the comparison result between the expected value data and the input data when the test mode is set only by using a one-phase clock signal. Since it is configured, a test clock signal can be omitted as compared with the first conventional example, and a complicated two-phase clock signal is unnecessary, and a complicated clock driver circuit for supplying this clock signal is not required. .

{Embodiment 2}
<Configuration>
FIG. 6 is a logic circuit diagram showing a semiconductor memory inspection apparatus according to the second embodiment of the present invention. Reference numeral 251 in FIG. 6 denotes a scan register, which is a type that takes in data at the rising edge of the clock signal (T) as in the first embodiment (positive edge trigger type), and is input from a semiconductor integrated circuit device (not shown) during normal operation. Output data to an external circuit, while comparing the data, the data input from the semiconductor integrated circuit device is compared with the expected data, and if they do not match, the data from the semiconductor integrated circuit device has failed. Is output to an external circuit. In FIG. 6, reference numeral 232 denotes a comparison circuit, and 234 denotes a flip-flop circuit with a reset function. Since these configurations are the same as those in the first embodiment, description thereof is omitted. Reference numerals 252 and 253 in FIG. 6 are selector circuits having the same structure as the selector circuit 233 (see FIG. 1) in the first embodiment, but one selector circuit (hereinafter referred to as the first selector circuit). Of the pair of signal input terminals “0” and “1” of 252, the signal input terminal “1” is connected to the output terminal of the second selector circuit 253. Of the pair of signal input terminals “0” and “1” of the other selector circuit (hereinafter referred to as the second selector circuit) 253, the pair of signal input terminals “0” has an external serial input signal. (SI) is input, and the other signal input terminal “1” is connected to the data output terminal O 1 of the flip-flop circuit 234. Further, an external shift inhibition signal (SINH) is input to the control input terminal of the second selector circuit 253. When the shift inhibition signal (SINH) is Low, the serial input signal (SI) is prohibited from shifting. When the signal (SINH) is High, the output data SO. Q is output to the first selector circuit 252.

  Here, the data output terminal O1 of the flip-flop circuit 234 and the other signal input terminal “1” of the second selector circuit 253 are connected by an internal wiring (loop wiring), whereby the data of the flip-flop circuit 234 is obtained. A loop circuit 254 is formed from the output terminal O 1 to the data input terminal D 1 of the flip-flop circuit 234 through the second selector circuit 253 and the first selector circuit 252. When the loop circuit 254 receives the shift inhibition signal (SINH), the loop circuit 254 replaces the serial input signal (SI) and the data input signal (D) with the output data SO. It functions as a data holding unit that feeds back Q to the flip-flop circuit and holds data of the flip-flop circuit 234.

  Here, the first selector circuit 252, the second selector circuit 253, a terminal to which the serial input signal (SI) is input (first input terminal), and the data input signal (D) are An input terminal (second input terminal) and a terminal (third input terminal) to which the shift mode control signal (SM) is input include the serial input signal (SI) and the data input signal (D ) Is selected and output.

  The first selector circuit 252, the second selector circuit 253, the other signal input terminal “1” of the second selector circuit 253 and the data output terminal O1 of the flip-flop circuit 234 are connected. Data holding means for holding data of the flip-flop circuit 234 is configured by the loop wiring and a terminal (third input terminal) to which the shift inhibition signal (SINH) is input.

<Operation>
The operation of the scan register 251 configured as described above will be described. FIG. 7 is a timing chart showing an operation of taking in data at the data input terminal D when the scan register 251 is used as an output flip-flop of a semiconductor integrated circuit device (RAM) during normal operation. As shown in FIG. 7, when the comparison enable signal (CMPEN) is Low, no reset signal is generated from the comparison circuit 232. If the shift mode control signal (SM) is Low at the rising edge of the clock signal (T), the selector circuit 252 selects the signal input terminal “0” and the data input signal (D) from the semiconductor integrated circuit device (RAM) is received. The data is taken into the flip-flop circuit 234. Since the RAM data output is connected to the data input terminal D, the scan register can be used as a RAM output flip-flop during normal operation.

  FIG. 8 is a timing chart showing the shift operation. When the comparison enable signal (CMPEN) is Low, no reset signal is generated from the comparison circuit 232. If the shift mode control signal (SM) is High (“1”) and the shift inhibit signal (SINH) is Low (“0”) at the rising edge of the clock signal (T), the serial input signal (SI) is the second selector. The signal is taken into the flip-flop circuit 234 via the circuit 253 and the first selector circuit 252 and output to the serial output terminal O1. Since the serial output terminal O1 is connected to the signal input terminal on the serial input signal (SI) side of the next-stage scan register, a shift operation is performed. The shift operation is performed at the initial setting (setting “1”) before starting the RAM test or at the time of reading the test result after the RAM test is completed.

  FIG. 9 is a timing chart showing the shift prohibiting operation. When the comparison enable signal (CMPEN) is Low, no reset signal is generated from the comparison circuit 232. If the shift mode control signal (SM) is High (“1”) and the shift inhibit signal (SINH) is High (“1”) at the rising edge of the clock signal (T), the output data SO. Q is taken into the flip-flop circuit 234 itself via both selector circuits 253 and 252. Accordingly, data is retained and no shift operation is performed. The shift prohibiting operation is used when the comparison operation should not be performed such as when the output data of the RAM is indefinite.

  FIG. 10 is a timing chart showing the comparison operation. If the shift inhibition signal (SINH) is High (“1”) and the shift inhibition signal (SINH) is High (“1”) at the rising edge of the clock signal (T), the output data SO. Q is taken into the flip-flop circuit 234 itself via the selector circuits 253 and 252. Therefore, the data is retained. When the clock signal (T) is Low and the comparison enable signal (CMPEN) is High, if the data at the data input terminal D and the expected data terminal (EXP) are different, a reset signal is generated, and the flip-flop circuit 234 is reset to “0”. Is done. Since the flip-flop circuit 234 is set to “1” by the initial shift operation, the presence of a failure is stored by the BS that changes to “0”. Data indicating the presence or absence of a failure held in the scan register is read out by a shift operation after the RAM test is completed.

  Also in the present embodiment, as in the first embodiment, only the one-phase clock signal is used, and the internal state of the flip-flop circuit 234 is set according to the comparison result between the expected value data and the input data when the test mode is set. In comparison with the first conventional example, the test clock signal can be omitted, and a complicated two-phase clock signal is not required, and a complicated clock for supplying this clock signal is provided. No driver circuit is required.

{Third embodiment}
<Configuration>
FIG. 11 is a logic circuit diagram showing a semiconductor memory inspection apparatus according to the third embodiment of the present invention. In FIG. 11, reference numeral 261 denotes a scan register, which is a type that captures data at the rising edge of the clock signal (T) as in the first and second embodiments (positive edge trigger type). Data input from an integrated circuit device (RAM) is output to an external circuit, while data comparison is performed by comparing data input from the semiconductor integrated circuit device with expected data, and when they do not match, the semiconductor integrated circuit The fact that the data from the device is faulty is output to an external circuit. In FIG. 11, reference numeral 234 denotes a flip-flop circuit. Further, reference numeral 254 in FIG. 11 denotes a loop circuit similar to that described in the second embodiment.

  Reference numeral 232a in FIG. 11 is a comparison circuit that compares an external expected data signal (EXP) with an external data input signal (D) based on an external comparison enable signal (CMPEN). The comparison circuit 232a includes one Ex. The circuit includes an OR circuit 241a and one NAND circuit 243a. Ex. The OR circuit 241a has a pair of input terminals. A data input signal (D) from the semiconductor integrated circuit device (not shown) is input to one input terminal, and the data input is input to the other input terminal. An expected data signal (EXP) from the outside for comparing and checking whether the signal (D) is normal is input. The NAND circuit 243a has two input terminals. One input terminal receives an external comparison enable signal (CMPEN), and the other input terminal receives the Ex. It is connected to the output terminal of the OR circuit 241a. Thus, the comparison circuit 232a compares the expected data signal (EXP) from the outside with the data input signal (D) from the outside when the comparison enable signal (CMPEN) from the outside is High, and these are different. Sometimes set to output Low.

  Reference numeral 264 in FIG. 11 denotes a feedback inhibition element (AND circuit) that inhibits feedback of the output of the flip-flop circuit 234 when a reset signal is output from the NAND circuit 243a of the comparison circuit 232a. The input terminal is connected to the output terminal of the NAND circuit 243a of the comparison circuit 232a, and the other input terminal is connected to the data output terminal O1 of the flip-flop circuit 234.

  Further, reference numeral 262 in FIG. 11 denotes a first selector circuit having a structure similar to that of the first selector circuit 252 (see FIG. 6) in the second embodiment, and reference numeral 263 denotes a second selector in the second embodiment. A second selector circuit having a structure similar to that of the circuit 253 (see FIG. 6), but of the pair of signal input terminals “0” and “1” of the second selector circuit 263, the signal input terminal “1” "Is connected to the output terminal of the feedback inhibition element 264.

  The first selector circuit 262, the second selector circuit 263, a terminal to which the serial input signal (SI) is input (first input terminal), and the data input signal (D) are input. Terminal (second input terminal) and the terminal (third input terminal) to which the shift mode control signal (SM) is input, the serial input signal (SI) and the data input signal (D) And selector means for selecting and outputting a reset signal from the comparison circuit 232a.

  Further, the first selector circuit 262, the second selector circuit 263, the other signal input terminal “1” of the second selector circuit 263 and the data output terminal O1 of the flip-flop circuit 234 are connected. For holding data of the flip-flop circuit 234 from a loop wiring and a terminal (third input terminal) to which the shift inhibition signal (SINH) is input while no reset signal is input from the comparison circuit 232a. Data holding means is configured. Since other configurations in the present embodiment are the same as those in the second embodiment, description thereof is omitted.

<Operation>
The operation of the scan register 261 having the above configuration will be described. FIG. 12 is a timing chart showing an operation of taking in data at the data input terminal D when the scan register 261 is used as an output flip-flop of a semiconductor integrated circuit device (RAM) during normal operation. As shown in FIG. 12, if the shift mode control signal (SM) is Low at the rising edge of the clock signal (T), the selector circuit 262 selects the signal input terminal “0” side. D) is taken into the flip-flop circuit 234. When operated in this way, the scan register can be used as a RAM output flip-flop during normal operation.

  FIG. 13 is a timing chart showing the shift operation. As shown in FIG. 13, when the shift mode control signal (SM) is High (“1”) and the shift inhibition signal (SINH) is Low (“0”) at the rising edge of the clock signal (T), the serial input signal (SI). Is taken into the flip-flop circuit 234 via both selector circuits 263 and 262 and output to the serial output terminal O1. Since the serial output terminal O1 is connected to the signal input terminal on the serial input signal (SI) side of the next-stage scan register, a shift operation is performed. The shift operation is performed at the initial setting (setting “1”) before starting the RAM test or at the time of reading the test result after the RAM test is completed.

  FIG. 14 is a timing chart showing the shift prohibiting operation. As shown in FIG. 14, when the comparison enable signal (CMPEN) is Low, the output of the NAND circuit 243a is High. Therefore, the feedback inhibition element 264 outputs the data held in the flip-flop circuit 234 as it is. If the shift mode control signal (SM) is High (“1”) and the shift inhibit signal (SINH) is High (“1”) at the rising edge of the clock signal (T), the output data SO. Q is taken into the flip-flop circuit 234 itself via the feedback inhibition element 264 and the selector circuits 263 and 262. Accordingly, data is retained and no shift operation is performed. The shift prohibiting operation is used when the comparison operation should not be performed, for example, when the output data of the RAM is indefinite.

  FIG. 15 is a timing chart showing the comparison operation. As shown in FIG. 15, if the comparison enable signal (CMPEN) is High, the data input signal (D) from the comparison circuit 232a is compared with the expected data signal (EXP), and if they are different, the output of the comparison circuit 232a is Becomes Low level. Therefore, the output of the feedback inhibition element 264 is at a low level. When the shift mode control signal (SM) becomes High (“1”) and the shift inhibition signal (SINH) becomes High (“1”) at the rising edge of the clock signal (T), the flip-flop circuit 234 is set to “0”. Reset.

  On the other hand, if the data at the data input terminal D and the expected data terminal (EXP) are the same at the rising edge of the clock signal (T), the output of the NAND circuit 243a is High, and the output data SO. Q is taken into the flip-flop circuit 234 itself via the feedback inhibition element 264 and the selector circuits 263 and 262. Therefore, the data is retained. Since the flip-flop circuit 234 is set to “1” by the initial shift operation, the presence of a failure is stored by changing this to “0”. Data indicating the presence or absence of a failure held in the scan register is read out by a shift operation after the RAM test is completed.

  Also according to the present embodiment, as in the first and second embodiments, only a one-phase clock signal is used, and according to the comparison result between the expected value data and the input data when the test mode is set. Since the data in the flip-flop circuit 234 is rewritten, the test clock signal can be omitted as compared with the first conventional example, and a complicated two-phase clock signal is not required, and this clock signal is supplied. This eliminates the need for a complicated clock driver circuit.

{Embodiment 4}
<Configuration>
FIG. 24 is a block diagram showing an outline of the fourth embodiment of the present invention. The inspection apparatus according to the present embodiment performs a function test on a plurality of semiconductor memories (circuits to be tested) such as RAM and ROM. In FIG. 24, reference numeral 30 denotes an inspection apparatus having a test pattern (algorithmic pattern) generating circuit according to the present embodiment, 31a to 31c are RAMs as circuits to be tested, and 32a to 32c are RAMs 31a to 31c during a function test of the RAMs 31a to 31c. 31c is a shift register for selecting an address, SIA is a common wiring for transmitting addressing data to all the shift registers 32a to 32c, 33a to 33c are write enable (write control) data input registers, and SIW is a data input wiring. , 34a to 34c are comparison circuits for comparing the output values of the data of the circuits under test 31a to 31c with the expected values, and CMPEN is for controlling (prohibiting) output correctness judgment (comparison operation) in the comparison circuits 34a to 34c. The comparison enable signal input terminal (comparison prohibition means). The SIW signal flowing through the data input wiring (SIW) is an inverted version of the comparison enable signal (CMPEN) flowing through the comparison enable signal input terminal (CMPEN). The semiconductor memory inspection apparatus of the present embodiment has the same purpose as that of the second conventional example and the third conventional example in that the address is incremented or decremented by the address generation circuit. Since it is necessary to shift (increment or decrement) the address in order, the LFSR function and the counter function are switched in the same circuit in order to increment or decrement the address in the address generation circuit. In FIG. 24, WEC is a write enable (write control) terminal of the RAM as the circuit under test 31. As shown in FIG. 24, each of the comparison circuits 34a to 34c includes a comparison prohibition unit 34Z. When the CMPEN terminal is “1”, the output values of the circuits under test 31a to 31c are compared with the expected values. When “0”, the comparison prohibition unit 34Z is configured not to perform the comparison. Reference numeral 34F denotes a flip-flop for correcting a time difference of one clock between the data input to the data input shift register 33 and the data output from the comparison circuit 34.

FIG. 25 is a diagram showing a semiconductor memory inspection apparatus according to the fourth embodiment of the present invention. The semiconductor memory inspection apparatus according to the present embodiment is a 5-bit address generation circuit that generates a pseudo-random sequence within 5 bits and enables count-up / down, and includes 5-bit addressing as a pseudo-random number. A function test is performed on a plurality of semiconductor memories (circuits to be tested) such as RAM and ROM while generating data. In FIG. 25, reference numeral 31 denotes a circuit under test (semiconductor memory) such as a RAM in which the number of words (number of address input terminals) is set to an arbitrary value (for example, 2 ⁴ ), and 32 denotes an address input terminal of the circuit under test 31. A 4-bit address input shift register for inputting addresses to A0 to A3, 33 is a data input register as a write enable (write control) command section, and 34 is a 2-bit comparison between the data output value of the RAM and the expected value. Comparison circuit (data output shift register) 35 is a 5-bit address generation shift register (address generation unit: ADDR) for storing the initial value of the RAM address, α-0 (least significant bit: LSB) to α- 4 (most significant bit: MSB) is a flip-flop (1-bit register) constituting the address generation shift register (ADDR) , 36 is a 5-bit control register (CARRY), and β-0 (least significant bit: LSB) to β-4 (most significant bit: MSB) are flip-flops (1-bit register) constituting the control register (CARRY) , 37 is a 5-bit flip-flop selection register (effective address number storage unit: MASKA) in which a generating polynomial for all periodic sequences is given as an initial value at the time of address setting and the effective address number is stored at the time of counting, γ-0 (maximum Lower bits: LSB) to γ-4 (most significant bit: MSB) are flip-flops constituting the flip-flop selection register (MASKA), and 38 is each flip-flop α-0 to the address generation shift register (ADDR). α-4 and each flip-flop selection register (MASKA) corresponding to each of them A first AND (logical product) circuit group that takes a logical product (AND) with the flops γ-0 to γ-4, 39 is the flip-flops β-0 to β-4 of the control register (CARRY) and these , A second AND (logical product) circuit group that takes a logical product (AND) with each of the flip-flops γ-0 to γ-4 of the flip-flop selection register (MASKA), 41 is an expected value generator A circuit 42 is an OR (logical sum) circuit group that takes a logical sum (OR) with respect to 39 outputs, 43 is a counter, and 44 is an exclusive OR (Ex.OR) circuit. The address generation shift register (ADDR) 35, the control register (CARRY) 36, the flip-flop selection register (MASKA) 37, the first AND circuit group 38, the second AND circuit group 39, The expected value generation circuit 41 and the OR circuit group 42 generate a test pattern having the number of bits corresponding to the maximum address value among the number of addresses of a plurality of types of semiconductor memories that perform a function test when the test pattern is generated. An arithmetic logic unit that sets the number of effective addresses of the semiconductor memory is configured.

  The address generation shift register (ADDR) 35 and the control register (CARRY) 36 are connected to terminals for inputting an external signal (Sinh-LX) for shift prohibition control of the registers 35 and 36. The flip-flop selection register (MASKA) 37 functions as an effective address number information storage unit that stores effective address number information at the time of counting.

  As shown in FIG. 26, the first AND circuit group 38 includes five AND circuits 51 to 55 corresponding to the number of bits of the address generation shift register (ADDR) 35 and the flip-flop selection register (MASKA) 37. Consists of The AND circuits 51 to 55 include flip-flops α-0 to α-4 of a corresponding address generation shift register (ADDR) 35 and flip-flops γ-0 to γ of a flip-flop selection register (MASKA) 37. -4 is input. For example, the AND circuit 51 calculates “α-0 AND γ-0”, and for example, the AND circuit 54 calculates “α-4 AND γ-4”.

  The second AND circuit group 39 is composed of five AND circuits 56 to 60 corresponding to the number of bits of the control register (CARRY) 36 and the flip-flop selection register (MASKA) 37. The AND circuits 56 to 60 include respective flip-flops β-0 to β-4 of the corresponding control register (CARRY) 36 and flip-flops γ-0 to γ- of the flip-flop selection register (MASKA) 37. 4 is input. For example, the AND circuit 56 calculates “β-0 AND γ-0”, and the AND circuit 60 calculates “β-4 AND γ-4”, for example.

  The expected value generation circuit 41 includes four exclusive OR (Ex.OR) circuits 61 to 64. Of these, Ex. The OR circuit 61 receives signals from the AND circuits 54 and 55. Ex. The OR circuit 62 receives signals from the AND circuits 52 and 53. Ex. OR circuit 63 is connected to Ex. Signals from the OR circuit 62 and the AND circuit 51 are input. Ex. OR circuit 64 is connected to Ex. Signals from the OR circuits 61 and 63 are input.

  The OR circuit group 42 includes four OR circuits 65-68. Among these, the OR circuit 65 receives signals from the AND circuits 59 and 60. The OR circuit 66 receives signals from the AND circuits 57 and 58. The OR circuit 67 receives signals from the OR circuit 66 and the AND circuit 56. The OR circuit 68 receives signals from the OR circuits 65 and 67.

  The counter 43 includes one AND circuit 71, one OR circuit 72, one half adder (half adder circuit) 73, one switch 74, and one flip-flop (hereinafter abbreviated as FF) 75. Is provided.

The AND circuit 71 has two input terminals. A reset signal (RSET) is input to one input terminal, and a signal from the FF 75 is input to the other input terminal. Thus, the counter 43 is reset when a signal is input from the FF 75 and a reset signal (RSET) is input. The OR circuit 72 counts the number of times corresponding to the number of effective addresses of the semiconductor memory based on information on the number of effective addresses from the arithmetic logic unit, and detects whether the address is immediately after incrementing or decrementing the address. At this time, it functions as an adding element for adding 1 and has two input terminals. One input terminal receives a signal (inarry) from the AND circuit 71 and the other input terminal. The signal (set) from the OR circuit 68 of the OR circuit group 42 is input. As shown in FIG. 27, the half adder 73 is a combinational logic element having two outputs of SUM (hereinafter abbreviated as S) and Carry (hereinafter abbreviated as C) and two inputs of A and B. S represents a sum without carry (sum output), C represents a carry (carry output), and the input terminals A and B and the output terminals S and C are
S = A Ex.OR B
C = A AND B
There is a relationship. The input terminal A has the Ex. A signal (coin) from the OR circuit 64 is input, and a signal (cain) from the OR circuit 72 is input to the input terminal B. The switch 74 selects whether to generate a pseudo-random sequence or to function as a counter based on a selection signal (Counter / LFSR) from the outside, has two input terminals, and has one input. The terminal of the expected value generating circuit 41 is connected to the Ex. A signal from the OR circuit 64 is input, and the output S (Data Out) of the half adder 73 is input to the other input terminal. The FF 75 functions as a storage element that stores the address contents immediately before the increment or decrement operation of the address by the OR circuit 72 based on the carry output C of the half adder 73 and transmits it to the OR circuit 72.

  Ex. The OR circuit 44 is for inverting the generated pattern based on the UP / DOWN signal from the outside, and has two input terminals. The signal from the switch 74 is input to one input terminal. The UP / DOWN signal is input to the other input terminal. And the Ex. The output of the OR circuit 44 is transmitted to the serial input terminal of the address input shift register 32. Here, in FIG. 25, the address input shift register 32 is omitted as a single unit, but actually, in order to functionally test a plurality of circuits under test 31a to 31c as shown in FIG. A plurality of address input shift registers 32a to 32c are connected in parallel. SIA in FIG. 25 is a common wiring for transmitting address designation data to the plurality of address input shift registers 32.

<How to use>
A method of using the semiconductor memory inspection apparatus having the above configuration will be described. First, at the time of a function test of the circuit under test 31, test data is input to the serial input terminal of the address input shift register 32 through the common wiring SIA and input to the circuit under test 31 (RAM) as an address. Here, when the circuit under test 31 (semiconductor memory) supports up to m bits (for example, 5 bits in the case of the present embodiment), the circuit under test 31 to be tested has n bits (for example, FIG. 25 to FIG. 25). In the case of 4 bits in FIG. 30, mn (in the case of this embodiment) of each register of the address generation shift register (ADDR) 35, the control register (CARRY) 36, and the flip-flop selection register (MASKA) 37 5-4 = 1) Bits are redundant. That is, in the present embodiment shown in FIGS. 25 to 30, a circuit corresponding to a RAM having an address terminal of 5 bits at the maximum, and the RAM to be tested has 4 bits, so there is only 1 redundant bit. Will do. Such redundant bits are set so as to be on the least significant bit (LSB) side of the register.

FIG. 28 shows an example in which the inspection apparatus of the present embodiment generates a quaternary full cycle sequence (test pattern). First, “00000” is set in the flip-flops α-0 to α-4 of the address generation shift register (ADDR) 35, and “11111” is set in the flip-flops β-0 to β-4 of the control register (CARRY) 36. “00110” is input to the flip-flops γ-0 to γ-4 of the flip-flop selection register (MASKA) 37 and “0000” is input to the flip-flop of the address input shift register 32 in advance. Here, the data set in the flip-flop selection register (MASKA) 37 is a generator polynomial of LFSR that generates a full-period sequence. The generator polynomial used in this embodiment is, for example,
1 + X ³ + X ⁴
= 1 + 0 × X ¹ + 0 × X ² + 1 × X ³ + 1 × X ⁴ + 0 × X ⁵
And Therefore, “00110” is set in the flip-flop selection register (MASKA) 37 as described above. Another example of the fourth-order generator polynomial is 1 + X ² + X ⁴ , and in this case, different test patterns can be generated by setting “01010” in the flip-flop selection register (MASKA) 37. .

Address generation shift register (ADDR) data is set to 35 "00000" is a 2 ⁴ tested circuit having an address word 31 the initial value of the address to be supplied to the (RAM) "0000". However, in the case of the present embodiment shown in FIG. 28, the least significant bit α-0 (the least significant bit: LSB) of the address generation shift register (ADDR) 35 is a redundant bit.

  Also, “11111” is set in the control register (CARRY) 36 as described above. During the test execution, the output (CMPEN) of the comparison circuit 34 is always “1” and the input (SIW) to the write enable (write control) data input register 33 is always “0”. Writing to (RAM) and comparison of the expected value and the output data of the circuit under test 31 are performed.

  Further, “0000” is input in advance to the address input shift register 32 as described above. The selection signal terminal Counter / LFSR is set to “0” (LFSR designation) so that the inspection apparatus of the present embodiment functions as an LFSR. Further, the selection signal UP / DOWN is set to “0” (UP designation).

  FIG. 29 is an equivalent circuit when initial values of the respective registers are set as shown in FIG. The symbols in FIG. 29 correspond to FIG. 25, respectively. That is, the inspection apparatus according to the present embodiment is a 4-bit LFSR including an address generation shift register (ADDR) 35 having flip-flops α-1 to α-4. When the Sinh-LX terminal is set to “0”, Generate a quaternary full-period sequence. After all patterns have been generated, the UP / DOWN terminal is inverted to designate DOWN so that the addresses can be generated in the reverse order to the previously generated address pattern.

  Next, a case where the semiconductor memory inspection device of this embodiment is operated as a counter will be described. FIG. 30 shows an example in which the circuit generates a quaternary counter. “00000” is input in advance to the address generation shift register (ADDR) 35. Further, “00010” is previously input to the control register (CARRY) 36. Further, “00010” indicating the number of bits (= 4) of the address input shift register 32 is previously input to the flip-flop selection register (MASKA) 37. Generally, when the flip-flop selection register (MASKA) 37 is m bits (5 bits in this embodiment) and the address input shift register 32 is n bits (4 bits in FIG. 30), the flip-flop selection register (MASKA) Only the first digit of the valid data string of 37 is set to “1”, and the remaining registers are set to “0”. Here, only flip-flop γ-1 is set to “1”.

Address generation shift register (ADDR) data entered in 35 "00000" is the initial value of the test circuit 31 (RAM) having addresses 2 ⁴ words. However, the least significant bit α-0 is a redundant bit. The data “00010” input to the control register (CARRY) 36 is the same as the data input to the flip-flop selection register (MASKA) 37. The address input shift register 32 is set with an initial address “0000” which is the same as the address generation shift register (ADDR) 35 (but the same as the data in which the least significant bit α-0 is omitted). In such a setting, the circuit shown in FIG. 30 is equivalent to the circuit shown in FIG. That is, in such a condition setting, the inspection apparatus becomes a 1-bit counter as an address changing means and increments every four cycles.

  The operation of the inspection apparatus of the present embodiment will be described based on FIG. First, the reset (RSET) signal is set to “0”, and the inside of the FF 75 is set to “0”. At this time, Sinh-LX is set to “1” so that the data in the address generation shift register (ADDR) 35 is not shifted.

  Next, the reset (RSET) signal is set to “1”, and Sinh-LX is set to “0” at the same time. At this time, the address generation shift register (ADDR) 35 and the address input shift register 32 are “0000”, and the control register (CARRY) 36 is “0001”.

  In FIG. 30, SIW (write enable) is “0”, CMPEN (data output) is “1”, data is written to address 0 of the circuit under test 31 (RAM), or circuit under test 31 (RAM ) Compare the data output with the expected value. Then, “α-1” AND “β-1” is executed by the half adder 73, and S = 1 and C = 0. Therefore, at the next clock, the address generation shift register (ADDR) 35 and the address input shift register 32 become “1000”, and the control register (CARRY) 36 becomes “1000”. At this time, SIW becomes “1” and CMPEN becomes “0”, and therefore, data writing in the circuit under test 31 (RAM) and comparison between the data output value and the expected value are prohibited. The address input shift register 32 is “0000”.

  In the fourth clock cycle, the address generation shift register (ADDR) 35 is “0001” and the address input shift register 32 is “0010”. SIW is “0” and CMPEN is “1”, and data is written to address 1 of the circuit under test 31 or the data output is compared with the expected value.

  In the fifth clock cycle, the address generation shift register (ADDR) 35 is “0000” and the address input shift register 32 is “0001”. SIW is "1" and CMPEN is "0", and data writing to the circuit under test 31 (RAM) and comparison between the data output value and the expected value are prohibited.

  Next, “α−1” AND “β−1” is executed by the half adder 73, and S = 0 and C = 1. Therefore, at the next clock, the address generation shift register (ADDR) 35 and the address input shift register 32 become “0000”, and the control register (CARRY) 36 becomes “1000”. At this time, SIW is “1” and CMPEN is “0”, and data writing to the circuit under test 31 and comparison between the data output and the expected value are prohibited.

  In the eighth clock cycle, the address generation shift register (ADDR) 35 and the address input shift register 32 are “0010”, and CARRY is “0001”. SIW is “0” and CMPEN is “1”, and data is written to the second value of the RAM, or the data output of the RAM is compared with the expected value.

  As described above, the circuit sets the address to increment every four shift operations. CMPEN outputs a signal in synchronization with the shift of CARRY, generates “0” at the time of address setting, “1” at the time of test, and SIW receives these inverted values.

  As described above, the circuit according to the present invention can increment the address every n shift operations when an n-bit shift register is set. Further, the address can be decremented by setting the UP / DOWN terminal to “1” and inverting the SIA.

  In order to solve the first problem described above, it is necessary to shift (increment or decrement) the address in a certain order. In order to increment or decrement the address in the address generation circuit, this embodiment is implemented. In the embodiment, the LFSR function and the counter function are switched by the same circuit. By the way, in order to increment or decrement the address by the address generation circuit, as another proposal example, another member is added to the LFSR circuit 523 having the same configuration as the second conventional example shown in FIGS. It is also conceivable to connect a general counter as described above, and increment or decrement the address by the cooperative operation of the counter and the LFSR circuit 523. However, in general, the counter has a larger area than the LFSR circuit 523, and it is difficult to integrate the counter in a single integrated circuit, and the counter must be externally provided outside the address bus. Therefore, not only an extra area for the counter is required, but also a wiring mechanism such as an address bus is required, which causes a significant reduction in area efficiency. In consideration of this, in the present embodiment, a small-area inspection apparatus is realized using a 1-bit register including a half adder 73, an FF 75, and the like.

{Embodiment 5}
<Configuration>
FIG. 32 shows a semiconductor memory inspection apparatus according to the fifth embodiment of the present invention. Inspection apparatus of the semiconductor memory of the embodiment, five bits, i.e. 2 but at ⁵ points a number of words following the address generating circuit is similar to that of the fourth embodiment, the inspection apparatus of this embodiment Magunechudo inside The present embodiment is different from Embodiment 4 in that a comparator (Magnitude Comparator) is provided. 32 in FIG. 32 is a 5-bit address generation shift register (ADDR) for storing an initial value of a RAM address, and 37 is a 5-bit flip-flop selection register (MASKA) in which a generator polynomial of all period series is given as an initial value. , 38 are a first AND (logical product) circuit group, and 41 is an expected value generating circuit, each having the same configuration as that described in the fourth embodiment. Also, in FIG. 32, 81 is an OR (logical sum) circuit group (MASK), 82 is a second AND (logical product) circuit group, and 83 is a 5-bit maximum in which the maximum value of the RAM address is given as an initial value. Address value storage registers (MAXA) 84 are magnitude comparators. The address generation shift register (ADDR) 35, the flip-flop selection register (MASKA) 37, the first AND circuit group 38, the expected value generation circuit 41, the OR circuit group (MASK) 81, and the The second AND circuit group 82 constitutes an arithmetic logic unit that generates a test pattern having the number of bits corresponding to the maximum address value among the number of addresses of the plurality of types of semiconductor memories that perform the function test when the test pattern is generated.

  The OR circuit group (MASK) 81 reads the flip-flop selection register (MASKA) 37 sequentially from the least significant bit γ-0 (LSB) to the most significant bit γ-4 (MSB). When -n is “1”, the most significant bit γ−4 (MSB) is converted to “1” from the most significant bit (γ−n + 1). The OR circuit group (MASK) 81 has four OR circuits 91, 92, 93, 94, and each of the OR circuits 91, 92, 93, 94 has two input terminals. One terminal of the OR circuit 91 is connected to the flip-flop γ-0 of the flip-flop selection register (MASKA) 37, and the other terminal is connected to the flip-flop γ-1. One terminal of the OR circuit 92 is connected to the output terminal of the OR circuit 91, and the other terminal is connected to the flip-flop γ-2. One terminal of the OR circuit 93 is connected to the output terminal of the OR circuit 92, and the other terminal is connected to the flip-flop γ-3. One terminal of the OR circuit 94 is connected to the output terminal of the OR circuit 93, and the other terminal is connected to the flip-flop γ-4. Here, the OR circuits 91 to 94 of the OR circuit group 81 are designated as MASKADDR (1) to MASKADDR (4), and the connection point between the least significant bit γ-0 of the flip-flop selection register (MASKA) 37 and the OR circuit 91. Is set to MASKADDR (0).

  The second AND circuit group 82 takes an AND of each bit for the address generation shift register (ADDR) 35 and the MASKADDR (0) to MASKADDR (4) of the OR circuit group 81 and outputs the result. The second AND circuit group 82 includes five AND circuits 95 to 99 corresponding to the number of bits of the address generation shift register (ADDR) 35 and the flip-flop selection register (MASKA) 37. The AND circuits 95 to 99 include respective flip-flops α-0 to α-4 of the corresponding address generation shift register (ADDR) 35 and flip-flops γ-0 of the flip-flop selection register (MASKA) 37. The signals from γ-4 are input. For example, the AND circuit 95 calculates “α-0 AND γ-0”, and the AND circuit 99 calculates “α-4 AND γ-4”, for example.

  The maximum address value storage register (MAXA) 83 is a register for storing the maximum number of words of the circuit under test 31, and is the same as the address generation shift register (ADDR) 35 and the flip-flop selection register (MASKA) 37. And five flip-flops δ-0 to δ-4.

  The magnitude comparator 84 is a digital data magnitude comparison circuit, and outputs “1” to SIW and “0” to CMPEN when the generated entire period series outputs a value equal to or greater than the RAM address value.

  Also, the data input register 33 and the comparison circuit 34 in FIG. 32 are the same as those described in the fourth embodiment. In the magnitude comparator 84, the data input register 33, and the comparison circuit 34, the redundant bit data of the arithmetic logic unit not corresponding to the address of the circuit under test 31 (ROM) is written into the semiconductor memory. A write control command unit for prohibiting the above is configured.

<How to use>
A method of using the semiconductor memory inspection apparatus having the above configuration will be described. First, as in the fourth embodiment, as an initial stage, the initial value of the RAM address is stored in the address generation shift register (ADDR) 35, and the generator polynomial (= “00110”) of the full-period sequence is stored in the flip-flop selection register (MASKA) 37. ) Is stored in the maximum address value storage register (MAXA) 83, the maximum value of the RAM address (= “1011”). In this embodiment, redundant bits are set on the least significant bit (LSB) side, and α-0 and δ-0 are redundant bits as in the fourth embodiment.

Here, as shown in FIG. 33, a time point of a certain clock cycle, for example, a time point when the address generation shift register (ADDR) 35 is “1001” is considered. FIG. 34 is an equivalent circuit of FIG. A pseudo-random address pattern generated according to the LFSR generator polynomial of “1 + X ³ + X ⁴ ” is output to SIA in FIG. Here, the value of the address input shift register 32 and the value α-4 to α-1 of the address generation shift register (ADDR) 35 are equal. For this reason, it is necessary to prohibit data writing to the RAM and comparison between the RAM data output value and the expected value. Therefore, SIW and CMPEN are generated by comparing the value of the address generation shift register (ADDR) 35 with the value of the maximum address value storage register (MAXA) 83 by the magnitude comparator 84. Specifically, when the RAM address value becomes larger than the value (= “1011”) set in advance in the maximum address value storage register (MAXA) 83, “1” is set to SIW and “0” is set to CMPEN. Occurs and prohibits data writing to the RAM and comparison between the RAM data output value and the expected value.

  In this way, regardless of the number of addresses of the circuit under test 31 to be functionally tested, the redundant bit elimination process can be performed reliably by comparing the magnitude of the address value with respect to the reference value.

{Sixth embodiment}
<Configuration>
In the fifth embodiment, if “00000” is to be generated as a test pattern, all the data that has passed through the first AND circuit group 38 and the second AND circuit group 82 become “0”. No matter how many times the shift register (ADDR) 35 is shifted, the inputs (SIA) to the address input shift register 32 remain “0” and are not converted to “1” forever. Therefore, in the fifth embodiment, “00000” cannot be generated as a test pattern, and there is a problem that the test pattern is limited in that sense. The semiconductor memory inspection apparatus according to the sixth embodiment of the present invention can generate “00000” that could not be generated in the fifth embodiment.

  FIG. 35 shows a semiconductor memory inspection apparatus according to the sixth embodiment of the present invention. Reference numeral 101 in FIG. 35 denotes a third AND circuit group having the same configuration as that of the first AND circuit group 38 and the second AND circuit group 82 described in the fifth embodiment. Specifically, the third AND (logical product) circuit group 101 includes four AND circuits 101a to 101d, and one input terminal of each of the AND circuits 101a to 101d is connected to the address generation shift register ( ADDR) 35 is connected to each of the flip-flops α-1 to α-4 except the least significant bit, and the other input terminals are MASKADDR (0) to MASKADDR (4) of the OR circuit group 81 (see the fifth embodiment). It is connected to the. In FIG. 35, the third AND circuit group 101 is {1, 0, 0, 1} AND {1, 1, 1, 0}. In FIG. 35, reference numeral 102 denotes a 4-bit NOR circuit 102 which takes the NOR of all outputs of the third AND circuit group 101.

The second AND circuit group 82 is an M-bit address generating circuit.
“ADDR (1) AND MASKA (0)”
“ADDR (2) AND MASKA (1)”
~
"ADDR (M) AND MASKA (M-1)"
Is output.

  Also, 103 in FIG. An OR circuit 103 to which an output signal from the NOR circuit 102 and an output signal from the expected value generation circuit 41 are input. The NOR circuit 102 and the Ex. The OR circuit 103 generates bit data having a value different from the value of the bit data when all the bit data of the address of the semiconductor memory generated immediately before is “0001”, and sets the bit data to the address of the subsequent semiconductor memory. A circuit for providing “0000” is configured.

<How to use>
FIG. 36 is a circuit equivalent to FIG. The semiconductor memory inspection apparatus SIA having the above-described configuration will be described with respect to a method of use when generating a pseudo-random address pattern. First, the expected value generation circuit 41 generates a pseudo-random address pattern based on a signal from the address generation shift register (ADDR) 35. However, if the RAM address value becomes larger than the value stored in the maximum address value storage register (MAXA) 83, the magnitude comparator 84 determines that and outputs “1” to SIW and “0” to CMPEN. Then, a write enable signal and a comparison enable signal input signal are transmitted to the circuit under test (RAM), and data writing to the RAM and correctness judgment (inspection) are prohibited. Here, when α-2 to α-4 are all “0001”, Ex. The OR circuit 103 outputs “0” to the wiring SIA leading to the address input shift register, and generates the RAM address 0. Also in the present embodiment, the same effect as in the fifth embodiment can be obtained.

{Embodiment 7}
The magnitude comparator 84 shown in the fifth and sixth embodiments has a large circuit scale and a large delay time. Therefore, both the area efficiency and the processing efficiency have been degraded. By the way, depending on the number of words, there is a case where it is not always necessary to compare the relatively lower bits by the magnitude comparator 84. For example, when the least significant bit α-0 (LSB) is a redundant bit and the maximum word (binary number) is “1001 (10 words in decimal)” (that is, “α-4” = “1”, “α -3 ”=“ 0 ”,“ α-2 ”=“ 0 ”, and“ α-1 ”=“ 1 ”), the least significant bit“ α-1 ”of these is“ 0 ”or“ Since 1 "is acceptable, it is the same whether or not the size is compared. Therefore, in this case, the result is the same even if only the upper 3 bits of “α-4”, “α-3”, and “α-2” are compared in size. Further, when the maximum word (binary number) is “1011 (12 words in decimal number)” (that is, “α-4” = “1”, “α-3” = “0”, “α-2” = “1”, “α-1” = “1”), the lower two bits “α-2” and “α-1” of these can be allowed to be “0” or “1”. Even if only the upper 2 bits of “α-4” and “α-3” are compared in size, the result is the same. Utilizing this fact, in the seventh embodiment of the present invention, the magnitude comparator 84 is configured to omit the comparison of unnecessary lower bits and perform the comparison only with specific upper bits. Then, the circuit scale of the magnitude comparator 84 can be reduced as compared with the fifth embodiment, the area efficiency can be improved, and the processing efficiency can be improved by reducing the delay time. For example, as shown in FIG. 37, in the case of a maximum of 10 words (decimal number), only the upper 3 bits of “α-4”, “α-3”, and “α-2” can be compared in size as described above. As described above, the area of the magnitude comparator 84 is not limited to the circuit area required for 3-bit data comparison, but also the wiring between the maximum address value storage register (MAXA) 83 and the magnitude comparator 84, and the second AND circuit group. The number of wirings between the terminal 82 and the magnitude comparator 84 is three, and the area on the wiring can be reduced.

{Embodiment 8}
In a test pattern in which the cycle of RAM data input (DI) changes during addressing, it is necessary to prepare a circuit that generates data by changing the data input pattern in synchronization with the address pattern. For example, in the case of the checkerboard pattern shown in FIG. 39, if the ROM address is incremented sequentially from “0000” to “1111”, the pattern corresponding to each bit is “0” “1” “0” “1” “1”. “0” “1” “0” “0” “1” “0” “1” “1” “0” “1” “0” in this order, but simple “0” “1” "Is not a repetition of"", but it is a complicated order of inversion for each stage. The eighth embodiment of the present invention has a data input pattern generation circuit for generating such a complicated order of test patterns.

  FIG. 38 shows a semiconductor memory inspection device according to the eighth embodiment of the present invention. The semiconductor memory inspection apparatus according to the present embodiment will be described with reference to a method for generating a checkerboard pattern, a column bar pattern, and a row bar pattern, which are often used for testing a memory circuit. In FIG. 38, 35 is an address generation shift register (ADDR), 37 is a flip-flop selection register (MASKA), 38 is a first AND circuit group, 41 is an expected value generation circuit, and these are the fourth embodiment. This is the same as that described in. Reference numeral 111 denotes a 5-bit shift register (hereinafter abbreviated as MASKD) as a two-dimensional pattern storage unit, 113 denotes an expected value generation circuit similar to the expected value generation circuit 41, and 114 denotes an internal configuration of the first AND. The second AND circuit group 115, which is similar to the circuit group 38 and executes “{ADDR} AND {MASKD}”, sends a write enable signal and Ex. This is an OR circuit 115. The expected value generation circuit 113 generates expected values for the address generation shift register (ADDR) 35 and the MASKD 111. The output of the expected value generation circuit 113 is Ex. It is transmitted to the OR circuit 115 to control SIW and CMPEN.

  Here, as shown in FIG. 40, the RAM address is divided into an upper address as a virtual vertical axis address (hereinafter abbreviated as X address) and a lower address as a virtual horizontal axis address (hereinafter abbreviated as Y address). Can think. 40 and 41 show an example in which MASKD 111 is set so as to generate a checkerboard pattern. That is, the MASKD 111 is formed by connecting a 2-bit virtual vertical axis (X) address storage bit group, a 2-bit virtual horizontal axis (Y) address storage bit group, and 1 redundant bit. As shown in FIG. 40, the least significant bit of the X address (hereinafter abbreviated as X (lsb)) is set to “1”, the least significant bit of the Y address (hereinafter abbreviated as Y (lsb)) is set to “1”, Set the bit to “0”. Here, the Ex. DATA input to one terminal of the OR circuit 115 is set to “0”. The expected value generation circuit 113 outputs “0” when the values of the address generation shift register (ADDR) 35 and the MASKD 111 are equal. At this time, Ex. The SIW output from the OR circuit 115 is “1” and the CMPEN is “0”, and comparison and writing between the RAM output and the expected value are prohibited. Conversely, when X (lsb) and Y (lsb) are different, the RAM output is compared with the expected value or written. Also, SIW and CMPEN can be inverted by setting DATA to “1”. FIG. 41 is an equivalent circuit at this time.

  Next, a procedure for generating the checkerboard pattern described above will be briefly described.

      1. Set MASKD to “01010”. Here, the ADDR address generation shift register (ADDR) 35 and the address input shift register 32 are initialized to the addresses where the test is started. Further, DATA is set to “0”, and all DIs of the circuit under test 31 (RAM) are set to “0”.

      2. LFSR is executed to generate all addresses.

      3. Set DATA to “1”. Also, all DIs in the RAM are set to “0”.

      4). LFSR is executed to generate all addresses. The pattern shown in FIG. 39 is generated by such a procedure.

  42 and 43 are examples in which MASKD is set so as to generate a column bar pattern. The least significant bit (hereinafter abbreviated as Y (lsb)) of the Y address is set to “1”, and the other bits are set to “0”. Set DATA to “0”. Since the expected value generation circuit 113 outputs the value of Y (lsb), when Y (lsb) is “0”, SIW is “1”, CMPEN is “0”, and Y (lsb) is “0”. When it is “1”, SIW is “0” and CMPEN is “1”. Also, SIW and CMPEN can be inverted by setting DATA to “1”. FIG. 44 is an equivalent circuit at this time.

  The procedure for generating the column bar pattern in this case is as follows.

    1. Initialize MASKD as described above. Here, MASKD is set to “000010”. Further, the address generation shift register (ADDR) 35 and the address input shift register 32 are initialized to the addresses at which the test is started. Furthermore, Ex. DATA input to one terminal of the OR circuit 115 is set to “0”. Then, all DIs of the circuit under test 31 (RAM) are set to “0”.

    2. LFSR is executed to generate all addresses.

    3. Set DATA to “1”. Then, all DIs of the circuit under test 31 (RAM) are set to “0”.

    4). LFSR is executed to generate all addresses. The pattern shown in FIG. 42 is generated by such a procedure.

  45 and 46 are examples in which MASKD is set so as to generate a rover pattern. The least significant bit (hereinafter abbreviated as X (lsb)) of the X address is set to “1”, and the other bits are set to “0”. Set DATA to “0”. 113 outputs the value of X (lsb), so when X (lsb) is “0”, SIW is “1”, CMPEN is “0”, and X (lsb) is “1”. , SIW generates “0” and CMPEN generates “1”. Further, SIW / CMPEN can be inverted by setting DATA to “1”. FIG. 47 is an equivalent circuit at this time.

  The procedure for generating the rover pattern in this case is as follows.

      1. Initialize MASKD as described above. Here, MASKD is set to “01000”. The ADDR and RAM address shift registers are initialized to the address at which the test is started. Set DATA to “0”. All DIs in the RAM are set to “1”.

      2. LFSR is executed to generate all addresses.

      3. Set DATA to “1”. All DIs in the RAM are set to “0”.

      4). LFSR is executed to generate all addresses.

{Embodiment 9}
<Configuration>
FIG. 48 shows a semiconductor memory inspection device according to the ninth embodiment of the present invention. When performing a function test of a circuit under test (RAM), it is necessary to burn in while moving all addresses and bits (dynamic burn-in). The semiconductor memory inspection apparatus of the present embodiment generates a dynamic burn-in test pattern with only one pin. In FIG. 48, 121 is a dynamic burn-in pattern generation circuit 121, 122 is an LFSR circuit, 123 is a 1-bit counter, 124, 125, and 126 are signal lines, 127 is a shift register, and 128 is a flip-flop (hereinafter referred to as a 1-bit counter). , FF), 129 is a NOT circuit, 130 is Ex. OR circuit, SI-D is a data output, SI-W0 and SI-W1 are inverted outputs, SI-C is an output of a chip enable signal or a read enable signal, and SI-A is an address output. FIG. 49 is a diagram showing a connection state when the dynamic burn-in pattern generation circuit 121 sets the RAM addresses of the plurality of circuits under test 31a to 31c. 49, 32a to 32d are address input shift registers, 33a to 33d are write enable (write control) data input registers, and 34a to 34d compare data output values of the circuits under test 31a to 31c with expected values. The comparison circuits 131a and 131b are registers for sending a chip enable signal to the chip enable terminal CE, and 132a and 132b are registers for sending a read enable signal to the read enable terminals RE0 and RE1. Further, DI0 to DI2 are data input terminals.

As shown in FIG. 48, the LFSR circuit 122 includes a shift register 127 having a plurality of FFs and an Ex. A combination with the OR circuit 130 is possible. In the LFSR circuit 122 of FIG. 48, the generator polynomial is 1 + X + X ²² . The generator polynomial is set so that the number of bits becomes larger than the sum of the number of address terminals and the number of control terminals of the dynamic burn-in pattern generation circuit 121 and the plurality of circuits under test 31a to 31c (RAM) to be tested. However, in the multi-port RAM such as the circuit under test 31a in FIG. 49, even if the shift input of the address shift register and the read enable (RE) signal are shared, the effect of the invention does not change. When there are two WEC terminals (WEC0, WEC1), the WEC0 signal is inverted and input to the WEC1 terminal to prevent simultaneous writing of the same address. For example, in FIG. 49, the RAM 31a and the RAM 31b have 6 terminals and the RAM 31a has 7 terminals, so a generator polynomial for generating a full-period sequence of 7th order or higher is set.

  In FIG. 48, the data output SI-D generated by the dynamic burn-in pattern generation circuit 121 is connected to the address input shift register 32 to the circuit under test 31. BURNIN is a 1-bit counter of this circuit and a reset terminal of the LFSR circuit. CLK is a clock terminal and is supplied to the 1-bit counter 123 and the LFSR circuit 122.

<How to use>
A method of using the semiconductor memory inspection apparatus having the above configuration will be described below.

    1. The RSET terminal is set to “0”, and the LFSR and 1-bit counter are RSET.

    2. When the reset terminal BURNIN is set to “1”, the LFSR circuit 122 generates a 22nd-order full cycle sequence, and the 1-bit counter 123 sets “1”, “0”, “1”, “0”, “1”. . . Is generated.

3. The nth-order LFSR circuit 122 generates an entire period sequence of odd bits (2 ⁿ −1). On the other hand, the 1-bit counter 123 generates 2-bit data. Therefore, when the LFSR is in the second period after generating the entire period series, the 1-bit counter 123 generates data inverted from the previous stage (2. above). That is, DI0, DI1, DI00 to DI11 are input with inverted data in odd cycles and even cycles for the combinations of address addresses A0 to A4, A00 to A13 and all CEs, RE0, RE1, WEC0, and WEC1. .

  Such an operation (1. to 3.) is repeated for a predetermined time.

{Embodiment 10}
<Configuration>
FIG. 50 is a diagram showing a semiconductor memory inspection apparatus according to the tenth embodiment of the present invention. The semiconductor memory inspection apparatus according to the present embodiment incorporates the elements of the fourth to ninth embodiments into one circuit. In FIG. 50, elements having the same functions as those in the fourth to ninth embodiments are denoted by the same reference numerals. In FIG. 50, 141, 142, and 143 are FFs, 144 and 145 are OR circuits, 146 is an AND circuit, 147 is an AND circuit in which one side input terminal is a negative input, 148 is a switching element, and 149 is an inverter. . Further, SI is a shift input signal, SO is a shift output signal, LFSRX is a selector selection signal, and Sinh-LX is a shift inhibition signal of the address generation shift register (ADDR) 35. Further, Sinh-MX is an AND of a signal obtained by inverting BURNIN, and includes a control register (CARRY) 36, a flip-flop selection register (MASKA) 37, a flip-flop selection register (MASKA) 37, a MASKD 111, and a control register. (MAXA) 83, flip-flop UP / DOWN, Counter, and DATA shift inhibit signal. When Sinh-LX and Sinh-MX are “1”, the shift operation of each shift register and flip-flop is prohibited.

  FIG. 52 describes the dynamic burn-in pattern generation circuit 121 of FIG. 50 in detail. Here, MASKA, MASKD, and MAXA are used in common with shift registers (LFSR / Counters) 38, 39, 41, 42, and 43 that constitute an LFSR circuit that generates a burn-in test pattern. The dynamic burn-in pattern generation circuit 121 shown in FIG. 52 has the same configuration as the generator polynomial LFSR circuit 122 shown in FIG. 141 resets the LFSR circuits 38, 39, 41, 42, and 43. That is, FF 141 corresponds to the Counter / LFSR terminal in the fourth embodiment shown in FIG. Reference numerals 124, 125, and 126 correspond to the signal lines having the same symbols in FIG. The FF 143 corresponds to the DATA terminal in FIG.

  Here, FIG. 53 shows details of the connection between the dynamic burn-in pattern generation circuit 121 and the circuit under test 31. 53, SIA, SID, SIC, and SIW are outputs of the dynamic burn-in pattern generation circuit 121, SIA is to the address input shift register 32, SIW is to the data input shift register 140, and SIC is CEC (REC ), The SIW is transmitted to the WEC. SIX is an SI input to the dynamic burn-in pattern generation circuit 121x, SICX is a signal for outputting SIC, SIWX is a signal for outputting SIW, SIDX is a signal for outputting SID, and CMPENX is 34F. This is a signal for outputting CMPEN. Further, CMPEN and SIWX from the dynamic burn-in pattern generation circuit 121 x are input to one AND circuit, and SIW is input to the circuit under test 31. Further, CMPEN and CMPENX from the dynamic burn-in pattern generation circuit 121x are input to another AND circuit, and CMPEN is input to 34F.

<How to use>
A method of using the semiconductor memory inspection apparatus having the above configuration will be described. FIG. 51 summarizes the input terminal settings in a table. In the semiconductor memory inspection apparatus of the present embodiment, the control registers MASKA, MASKD, and MAXA described in the fourth to eighth embodiments are used as shift registers. At each initial setting, these shift registers constitute one scan path. When the test pattern is generated, the shift inhibit signal Sinh-MX operates as a control register.

{1} Operation at the Time of Generating Dynamic Burn-In Test Pattern First, a case will be described in which the semiconductor memory inspection apparatus of the present embodiment is used as a circuit for generating an address pattern during a normal test.

(Initial setting)
The BURNIN terminal is set to “0”, and the LFSR circuits 38, 39, 41, 42, 43 and the dynamic burn-in pattern generation circuit 121 as a 1-bit counter are RSET.

(During dynamic burn-in pattern generation)
When the BURNIN terminal is set to “1”, the LFSR circuits 38, 39, 41, 42, and 43 generate 22nd order periodic sequences, and the dynamic burn-in pattern generation circuit 121 sets “1”, “0”, and “1”. , “0”, “1”. . . Is generated. Then, the nth-order LFSR circuits 38, 39, 41, 42, and 43 generate an entire period sequence of odd bits (2 ⁿ −1). In contrast, the 1-bit counter 121 generates 2-bit data. Therefore, when the LFSR is in the second period after generating the entire period series, the 1-bit counter 121 generates data inverted from the previous stage.

  Such an operation (1. to 3.) is repeated for a predetermined time. At this time, the other input terminals do not affect the inspection apparatus.

{2} Operation during address pattern generation (initial setting)
First, initial values are set in each shift register. For the initial value of each shift register, Sinh-LX and Sinh-MX are set to “0” to enable the shift operation. The rest is the same as described in the fourth to ninth embodiments. The FF 142 corresponds to the control signal terminal UP / DOWN in the fourth embodiment shown in FIG. 25, and the address pattern can be inverted by setting “1”.

(When generating test pattern)
A test pattern is generated according to the initial settings of the shift registers 35, 36, 37, 111, 83 and the FFs 141 to 143. The test execution time is 2 ⁿ cycles for the RAMs 31a to 31c having n address lines. During this time, Sinh-LX is set to “0” to enable the address generation shift register (ADDR) 35 to perform a shift operation. Sinh-MX is set to “1”, and the flip-flop selection register (MASKA) 37, MASKD111, control register (MAXA) 83, flip-flop UP / DOWN, Counter, and DATA are prohibited from shifting. The operation of each part is as described in the fourth to ninth embodiments.

  As described above, in the semiconductor memory inspection apparatus according to the present embodiment, the number of test vectors can be significantly reduced for a complicated test pattern.

{Embodiment 11}
<Configuration>
FIG. 54 shows a semiconductor memory inspection apparatus according to the eleventh embodiment of the present invention. The semiconductor memory inspection apparatus according to the present embodiment can detect a failure at a specific address of a RAM. The semiconductor memory inspection apparatus has a circuit configuration similar to that of the fifth embodiment, the sixth embodiment, and the seventh embodiment, except that the fifth embodiment, the sixth embodiment, and the fifth embodiment. 7 includes a single magnitude comparator 84, whereas the present embodiment includes a pair of magnitude comparators 84a and 84b (magnet comparators). Here, one magnitude comparator 84a has the same function as the magnitude comparator 84 described in the fifth, sixth, and seventh embodiments, that is, the maximum address value stored in the control register (MAXA) 83. The arithmetic logic unit has a function of comparing the size with a newly generated address. The other magnitude comparator 84b (detection circuit) has a function of detecting whether the maximum address value stored in the control register (MAXA) 83 is equal to the address newly generated by the arithmetic logic unit. The newly generated RAM address is compared with the MAXA value by the magnitude comparator 84b, and CMPEN = "1" is generated only when the RAM address matches the MAXA value and compared with the expected value of the RAM data. Do. Therefore, by setting a specific address of the circuit under test 31 in MAXA, a failure can be detected for the specific address of the circuit under test 31.

  As shown in FIG. 54, the semiconductor memory inspection apparatus of the present embodiment is obtained by adding a magnitude comparator 84b for detecting a failure at a specific address to the circuit of the fifth embodiment shown in FIG. The control register (MAXA) 83 sets the final address of the circuit under test 31 or the address where failure detection is to be performed. As in the seventh embodiment, in order to reduce the circuit scale and delay, it is preferable to compare the RAM addresses with MAXA only by using the upper bits. In FIG. 54, EQ is a switching signal for both outputs of the pair of magnitude comparators 84a and 84b. When EQ = 0, the magnitude comparator 84a is selected, and when EQ = 1, the magnitude comparator 84b is selected.

<How to use>
In the semiconductor memory inspection apparatus having the above-described configuration, when detecting a failure at a specific address, the magnitude comparator 84b compares the newly generated RAM address with the value of MAXA, and the RAM address is compared with the value of MAXA. Only when they match, CMPEN generates “1” and a comparison with the expected value of the RAM data is performed. Therefore, by setting a specific address of the circuit under test 31 in MAXA, a failure can be detected for the specific address of the circuit under test 31.

  On the other hand, in the normal function test, the function test may be performed by the same method as described in the fifth embodiment.

{Embodiment 12}
<Background>
FIG. 60 shows a circuit example of a semiconductor memory inspection apparatus. In FIG. 60, 301 is a test pattern generation circuit (for example, LFSR: random number generation circuit), 302 is a test circuit as a peripheral circuit, and 303 is a RAM core (memory core). Here, the test circuit 302 also has a function as a data input / output circuit (peripheral circuit) that exchanges various data with the RAM core 303 during normal operation. The test pattern generation circuit 301 includes shift registers 312 and 313 having a predetermined number of bits, and generates a test pattern for testing the RAM core 303. Note that one shift register 312 corresponds to, for example, the effective address number storage unit (MASKA) 37 or the two-dimensional pattern storage unit (MASKD) 111 of the fourth to eleventh embodiments, and the other shift register 313. Corresponds to, for example, the address generation unit (ADDR) 35 and the control register (CARRY) 36 of the fourth to eleventh embodiments. BIST is an input pin for a mode switching signal (BIST signal) for switching between the normal operation mode and the test mode for the peripheral circuit (test circuit) 302. SI is a logic data (first input data) input pin of the test pattern generation circuit 301 to shift in data. SINH0 and SINH1 (shift prohibition signals) are input pins for inputting a control signal for prohibiting the shift operation of each of the shift registers 312 and 313 by outputting “1”, respectively, when an address or the like is to be determined. is there. That is, the shift registers 312 and 313 shift when SINH1 and SINH0 are “0”, and shift is prohibited when “1”. Here, the test pattern generation circuit 301 in FIG. 60 corresponds to the circuit of the tenth embodiment described above and corresponds to the circuit 121X in FIG. The test circuit 302 in FIG. 60 corresponds to the circuits in the first to third embodiments and the first to sixth modifications described later, and The BIST signal corresponds to the SM signal in the first to third embodiments and the first to sixth modifications described later.

  The operation of the circuit of FIG. 60 will be described. First, during normal operation, the BIST signal is set to “0”. At this time, since the test circuit 302 does not operate, the RAM core 303 operates normally. On the other hand, when the test circuit operates, the BIST signal is set to “1”. At this time, SINH0 in FIG. 60 corresponds to SINH-LX in FIG. 50, and SINH1 in FIG. 60 also corresponds to SINH-MX.

  FIG. 61 shows the operation. During normal operation (normal state), the BIST signal is maintained at “0”. At this time, the RAM core 303 performs a normal operation regardless of the SI signal (logic data: first input data), the SINH0 signal, and the SINH1 signal.

  On the other hand, in FIG. 60 and FIG. 61, at the time of initial setting (INIT. State), the BIST signal is maintained at “1” and the SI signal is input. At this time, SINH0 and SINH1 are kept at “0”. That is, in the circuit of FIG. 50, SINH-LX and SINH-MX are set to “0”, and the SI signal (logic data) is shifted in (DATA SHIFT IN state). When the test is executed (RUN state), the SINH0 is maintained at “0” and the SINH1 is maintained at “1” while the BIST signal is maintained at “1”. That is, in the circuit of FIG. 50, SINH-LX is set to “0”, and SINH-MX is set to “1”. In this case, the SI signal is ignored in any state (Don't Care state). Then, it operates as described in the tenth embodiment.

  By the way, in the test circuit having such a function, the test signal pins require three pins, SI, SINH1, and SINH0. Here, there is a request to reduce the number of pins, and in particular, there is a case where one pin is to be operated in a test circuit. In this case, the semiconductor memory inspection apparatus according to the twelfth embodiment of the present invention is effective.

<Configuration>
FIG. 62 is a block diagram showing a semiconductor memory and an inspection apparatus thereof according to Embodiment 12 of the present invention. The semiconductor memory inspection apparatus according to the present embodiment uses a plurality of circuits described in each of the above embodiments and the above-described proposal examples (MULTIPLE LOGIC SCAN CHAIN). For the above, a circuit similar to or similar to each of the above embodiments is used. Reference numeral 315 in FIG. 62 denotes a memory (hereinafter simply referred to as a RAM) assuming that the test circuit 302 and the RAM core 303 connected to each other in FIG. Each RAM 315 includes a logic data input (SI) terminal (first input terminal) for inputting logic data (SI signal) during a logic data test, and a SIM signal (RAM test data: second input) during RAM test data. RAM test data input (SIM) terminal (second input terminal) for inputting input data) and a read (SOM) terminal for outputting an SOM signal as a read signal. The SOM terminal of one RAM (hereinafter referred to as preceding RAM) 315 is connected to the SIM terminal (second input terminal) of another RAM (hereinafter referred to as subsequent RAM) 315 adjacent thereto. Further, the SI terminal (first input terminal) of the subsequent RAM 315 is connected to the SOM terminal of the preceding RAM 315 or the above via a scan path 316 (SCAN FFs) as a shift register having a plurality of flip-flops (FF). Connected to the test pattern generation circuit 301 (SI1, SI2).

  Various test signals (TEST) at the time of the RAM test, that is, an EXP signal, a comparison enable signal (CMPEN), an SIA signal, an SID signal, an SIC signal, an SIW signal, an SINH signal, an EXXY signal, and CHDIR (change direction), which will be described later. ) Signal, WINH signal, INSFF signal, and MEMST signal are provided to each RAM 315 through a pipeline 319 having a plurality of FFs 317. One FF 317 is provided for each of a predetermined number of RAMs 315. As shown in FIG. 62, a test data input terminal (TEST) for inputting various test data is connected to the pipeline 319, and a shift inhibition signal (SINH) is input to the test data input terminal (TEST). A shift prohibiting signal input terminal is included. The shift prohibiting signal input terminal (see TEST in FIG. 62) and the pipeline 319 constitute data compression means for compressing data in the serial connection body. By supplying the SINH signal to each RAM 315 at a predetermined timing, data compression of the SI signal is performed, and a plurality of the FFs 317 are connected in series to form an FF series connection body. The pipeline 319 as the FF series connection body is formed in parallel to a circuit (RAM series connection body) in which the RAM 315 is connected in series, and an output signal from each FF 317 of the pipeline 319 is the corresponding RAM 315. Is input. A signal input terminal for inputting various test signals (TEST) such as SINH to the pipeline 319 is formed on the most output (SOM) side of the RAM 315. With this configuration, particularly when the SINH signal is supplied through the pipeline 319 and the FF 317, the data can be automatically delayed by one clock at the FF 317, and the plurality of RAMs 315 grouped for each FF 317 can be stored. Of these, data compression can be easily performed by prohibiting a shift operation of a scan path 332 (particularly, a data output scan path (DO-SCAN)) described later in order from the RAM 315 of the output side group. Here, for example, when the SINH signal is directly input to each RAM 315 without using the FF 317, it is necessary to drive the SINH signals of a large number of RAMs. Therefore, the processing speed may be reduced. By automatically delaying data by one clock at FF 317, data compression can be performed at a very high speed.

  In addition to these test signals, each RAM 315 is provided with an SM (shift mode) signal, that is, a BIST signal. From the semiconductor memory inspection apparatus, SO1 and SOM (SO2) are output to the outside. Note that reference numeral 318 in FIG. 62 denotes a scan path (shift register) used when it is desired to directly output the supplied SI3 signal as SO3 without passing through the RAM 315.

  FIG. 63 is a diagram showing a semiconductor memory inspection apparatus according to the present embodiment. Elements having the same functions as those of the proposed example shown in FIG. 60 are denoted by the same reference numerals. Further, reference numerals 321 and 322 are flip-flops (FF), 323 is a selector, 324 is an AND circuit, 325 is a NOT circuit, 326 is an OR circuit in which an input on one side is inverted, and 327 is a NOR circuit. The FFs 321 and 322, the selector 323, the AND circuit 324, the NOT circuit 325, the OR circuit 326, and the NOR circuit 327 constitute control signal generation means for generating the SINH0 signal and the SINH1 signal. One input terminal of the AND circuit 324 is connected to the BIST terminal. Here, the BIST terminal is an instruction terminal for inputting an instruction signal (BIST signal) for instructing generation of SINH0 and SINH1 (shift inhibition signal) in the control signal generating means. The input terminal of the FF 322 is connected to the output terminal (SHINH-FF) of the AND circuit 324. The input terminal of the NOT circuit 325 is connected to the output terminal of the FF 322. The other input terminal of the AND circuit 324 is connected to the output terminal of the NOT circuit 325. Logic data (SI signal) is input to the “0” side input terminals of the shift register 312 and the selector 323. The output terminal of the selector 323 is connected to the FF 321, and the output of the FF 321 is fed back to the “1” side input terminal of the selector 323. The positive input terminal of the OR circuit 326 is connected to the output terminal (RUNBIST) of the FF 321, and the inverting input terminal is connected to the output terminal (SHINH-FF) of the FF 322. Control signals SINH0 and SINH1 for prohibiting the shift operation of the shift registers 312 and 313 are output from the OR circuit 326 and the NOR circuit 327, respectively. With this configuration, the FF 321 and the selector 323 always operate to detect an odd-numbered value of the SI signal, and determine an operation mode in which the test pattern generation circuit 301 should operate (mode determination unit). When the odd value of the SI signal is “0”, it represents the initial setting operation mode, and when it is “1”, it represents the test execution operation mode. The FF 322, the AND circuit 324, the NOT circuit 325, the OR circuit 326, and the NOR circuit 327 are based on the determination by the mode determination unit (321, 323) and the shift registers 312 and 313 of the test pattern generation circuit 301. The prohibition signal generation unit for generating the shift prohibition signals SINH0 and SINH1 corresponding to. The mode determination unit and the prohibition signal generation unit constitute prohibition signal generation means for generating the shift prohibition signals SINH0 and SINH1 based on the data input signal and transmitting them to the test pattern generation circuit 301.

  64 and 65 show a semiconductor memory and an inspection apparatus (single port RAM) thereof according to the twelfth embodiment of the present invention. 64 and 65 are broken along the line AA. 65. The single port RAM refers to a RAM core (Core) as a semiconductor memory and a peripheral circuit that controls input / output of various signals to / from the RAM core. Both read (READ) and write (WRITE) are used. The scan path 332 as a plurality of shift registers is provided around the synchronous RAM core (memory core) 331 (corresponding to the above-mentioned RAM core 303). (A-SCAN, DI-SCAN, DO-SCAN) and a single write pulse generator (Wright Pulse Generator) 333 and the like. TEST BUS in FIG. 64 is a terminal used in the RAM test, and is an EXP (expected data) signal, a CMPEN (comparison enable) signal, an SID (test data) signal, an SIA (address) signal, an SIC signal, and an SM (shift mode). ) Signal, SIW0 signal, MEMST (memory test) signal, SINHA0X signal, SINHA0Y signal, EXXY (XY conversion) signal, CHDIR (change direction) signal, SINHDI signal, SINHDO signal, INSFF signal, and WINH signal.

  FIG. 66 shows a data input scan path 332 (DI-SCAN). “A” in FIG. 66 is a scan FF corresponding to an individual address of the data input scan path 332 (DI-SCAN) of each single-port RAM, and a plurality of scan FFs (“A”) are connected in series ( Serial). The data input scan path 332 (DI-SCAN) has a shift operation suppression function, and the shift operation can be suppressed by setting the SM signal to “1” and the SINHDI to “1”. It is possible to fix all of the write data to “0” or “1” by the shift operation suppression function, and it is also possible to switch the pattern of “0101...” Or “1010. . In the RAM test, the same logical value can be used for each bit of data I / O. That is, there is almost no need to worry about the number of bits of data I / O in the test algorithm. Therefore, as the input / output data pattern, all data may be set to either “0” or “1”. However, if the shift operation is used, the operation of switching “0000” to “1111” or “1111” to “0000” cannot be performed in one clock (that is, the number of shifts is only one) (in this example, 4 clocks required). In the present test circuit, each scan FF (“A”) is configured as shown in FIG. 67 in order to greatly improve the data input speed by switching data with one clock data. That is, each of the scan FFs (“A”) includes a register 332a that stores and outputs data, a first selector 332b that switches between an output of the register 332a and an SI signal, and an output from the first selector 332b. And a second selector 332c for switching between a data (D) signal from an external logic circuit.

  Further, the data output scan path 332 (DO-SCAN) is configured as shown in FIG. The data output scan path 332 (DO-SCAN) is provided with the comparison circuits (34, 34a to 34c) and the comparison prohibition unit (34Z) as described in the fourth embodiment (FIG. 25, FIG. 25). 26, FIG. 28 and FIG. 31). “B” in FIG. 68 is a scan FF of the data output scan path 332 (DO-SCAN). The data output scan path 332 (DO-SCAN) has a shift operation suppression function, and each scan FF ("B") includes a register 332a for storing and outputting data, as shown in FIG. A first selector 332b that switches between an output signal of the register 332a and an SI signal, a second selector 332c that switches between an output from the first selector 332b and a data (D) signal from an external logic circuit, Ex. For taking exclusive OR of data (D) signal and EXP signal. OR circuit 332d, Ex. A NAND circuit 332e that takes a negative logical product of the output signal of the OR circuit 332d and the comparison enable signal (CMPEN), and an AND circuit 332f that takes a logical product of the output signal of the NAND circuit 332e and the output signal of the register 332a. It is configured. The data output scan path 332 (DO-SCAN) can suppress the shift operation by setting the SM signal to “1” and the SINHDI to “1”. Further, by setting CMPEN to “1” in the shift operation suppression state, the EXP value and D are compared at the rising edge of the clock. If EXP and D are different, the scan FF (“B”) is reset to “0”. Therefore, before testing the RAM, it is necessary to set “1” to the scan FF (“B”) by the shift operation. If the value of the scan FF (“B”) of the data output unit is shifted out after the RAM test, it is possible to determine which bit has a failure. Since the expected data (EXP) signal is commonly applied to all the bits of the data output, when the pattern “0101” or “1010” is used for the write data, the even-numbered bit or the odd-numbered bit is used. Bits are always ignored. Therefore, it is necessary to perform two tests using both a test pattern that targets only even-numbered bits and a test pattern that targets only odd-numbered bits.

  In the scan FF ("B"), a NOT circuit is connected to the scan FF of only one of the even bit and the odd bit so that the expected data (EXP) signal can be easily changed alternately between the odd bit and the even bit. ing. With this configuration, when serial data is input (see FIG. 66), test data such as “0101” or “1010” can be easily input. The data output scan path 332 (DO-SCAN) shown in FIG. 68 is connected to the circuits of the first to third embodiments and the first to sixth modifications described later. It corresponds.

  In the address input scan path 332 (A-SCAN) shown in FIG. 64, for example, seven FFs (“A”) of XA0 to XA6 are connected in series as shown in FIG. Connected to a similar A-SCAN in a single port RAM. 70 is configured to input only the X address when there is no Y address. The address input scan path 332 (A-SCAN) is configured to be able to shift the address in both directions, and each of the change direction signals (switching signal: CHDIR) indicated by “A” in FIG. By switching the selector 341 connected to the FF (“A”: XA0 to XA6), the shift direction of the FF (“A”) can be changed. For example, when CHDIR = 0, the SI signal is input from the higher order (BSM) side. Conversely, when CHDIR = 1, the SI signal is input from the lower order (LSB) side. As shown in FIG. 67, each FF (“A”) switches between the register 332a for storing and outputting data, and the output of the register 332a and the SI signal, like the data input scan path 332 (DI-SCAN). The first selector 332b includes a second selector 332c that switches between an output from the first selector 332b and a data (D) signal from an external logic circuit.

  The test circuit 302 shown in FIG. 63 corresponds to a peripheral circuit excluding the RAM core 331 in FIGS. 64 and 65. 64 and 65, A <0>... A <MSB> is an address input terminal of a multiplexer (multiple equal distribution) system, DI <0>... DI <MSB> is a data input terminal of a multiplexer system, and DO <0>. ... DO <MSB> is a multiplexer-type data output terminal, BWC <0> ... BWC <MSB> is a multiplexer-type control that enables control for each bit instead of control for each byte (= 8 bits) This is a low enable bit write inhibit signal input terminal. In the above terminals, <0> indicates the least significant bit and <MSB> indicates the most significant bit. Each scan path 332 has, for example, a 32-bit flip-flop (FF) (in this case, <MSB> = <32>). A low enable signal is input to CSC (chip select terminal) and WEC (write enable terminal). C in FIGS. 64 and 65 is a scan FF. Further, MEMST is a terminal for inputting a signal for switching between the normal operation mode and the memory test mode, and corresponds to each scan FF (C) and each scan path 332 (A-SCAN, DI-SCAN). In addition to being connected to the selector 334 and for prohibiting input from BWC <0>... BWC <MSB> during a memory test (MEMTST = 1), for example, 32 bit writes are prohibited via a single NOT circuit 335. The signal input AND circuit 336 is connected.

  Each of the scan paths 332 (A-SCAN, DI-SCAN, DO-SCAN) is sent from A <0>... A <MSB> when no mode switching signal (SM) is input as shown in FIGS. Address, DI <0>... Input data from DI <MSB>, BWC <0>... 1 bit data from BWC <MSB> is fetched in a multiplexer manner and passed to RAM core 331 or output data from RAM core 331 Are transferred to the data output terminals DO <0>... DO <MSB>.

  On the other hand, when a mode switching signal (shift mode: SM) is input, each selector 334 is configured to select the “0” side. In this case, each selector 334, each scan FF (C), and each scan path 332 (A-SCAN, DI-SCAN, DO-SCAN) are all connected in series, and a given SI signal is applied to each selector. 334, each scan FF (C), and each scan path 332, the output to the SOM.

  Reference numeral 337 in FIGS. 64 and 65 denotes a selector that switches between a RAM test SIM signal and a logic test SI signal. The EXP signal is input as a desired expected data signal of “0” or “1” during the RAM test, but otherwise functions as a switch signal for switching the selector 337, and during normal operation (NORMAL) When the SI signal is input (SHIFT-SI) and when the data is captured (CAPTURE), “0” is input to the selector 337, and when the SIM signal is input (SHIFT-SIM), “1” is input to the selector 337. Enter. As the write pulse generator 333, for example, a general one having a pair of delays (Delay 1 and Delay 2), three not circuits and a pair of NAND circuits as shown in FIG. 71 is used. FIG. 72 is a timing chart showing the operation of the write pulse generator 333. 72, T, A, B, C, bar EN, WINH, and WEC correspond to the same symbols in FIG. In FIG. 72, tchw is the length of the half cycle of the clock signal (T), Delay 1 is the time difference between the input (T) and output (A) of one delay (Delay 1), and Delay 2 is the other delay (Delay 2). Is the time difference between the input (A) and the output (B), td (WPG) is the time difference between the clock signal (T) and the output of the WEC signal, and tw (WPG) is the output time of the WEC signal.

<Operation>
FIG. 76 shows the circuit operation of the present embodiment. Each signal (CHDIR, etc.) in FIG. 76 corresponds to FIG. 63, however, SINHA1X, SINHA1Y, SINHA2X, SINHA2Y, and SIW1 indicate signals related to test circuits of other adjacent RAMs. In FIG. 76, “NORMAL” is a normal operation, “SHIFT-SI” is a shift operation when an SI signal is input, “SHIFT-SIM” is a shift operation when a SIM signal is input, and “CAPTURE” is an external logic. An operation when capturing data generated by a circuit or the like (SM signal = “0”), and “RAMTEST” indicate an operation at the time of RAM test.

  First, during normal operation (normal state), the BIST signal is set to “0” as shown in FIG. At this time, the RAM core 303 operates normally (Don't Care state) no matter what data is input as the SI signal. That is, almost all data on the test bus is set to 0 as shown in FIG. 76, and data or addresses are input in a multiplexer manner from A <>, DI <>, or BWC <> as shown in FIG. 77, or data is input from DO. Output. However, the signal indicated by “−” (that is, “Don't Care”) in FIG. 76 may not be zero. 77 and 78, <Read cycle>, <Write cycle>, and <Noop cycle> respectively indicate a read operation state, a write operation state, and a non-operation state. Each state of the read (Read) operation and the write (Write) operation of the RAM core 331 at this time is as shown in FIG. 77 and 78, tuss (C), tuss (W), tuss (A), tuss (D), tsu (D), tsu (BW), and tsu (A) are external BWC signals. To the input of the bwc signal to the RAM core 331, ths (C), ths (W), ths (A), ths (D), th (D), th (BW), and th (A ) Is the valid time of each signal, td (WPG) is the time difference from the start of the write operation to the wec (WEC) signal input into the RAM core 331, tw (WPG) and tw (W) are the wec (WEC) signal input time , Tv (T), tv2 (T) and tv (A) are the time from the start of reading or writing until the end of data output, ta (T), ta2 (T) and ta (A) are the data after starting reading or writing. Time until the end of output, a (0) and a (1) are addresses, di (1) is input data, bwc (1) is input time of BWC signal, and data (a (0)) is output data. Show. Further, as shown in FIG. 76, no output is made from the SOM.

  On the other hand, when a scan test or a RAM test is performed, the operation is performed according to the procedures shown in FIGS. 74 and 75, respectively. In the scan test shown in FIG. 74, first, a shift operation (SHIFT-SIM) is performed while inputting a SIM signal (RAM test data), then a RAM test (TEST) is performed, and then a shift operation (SHIFT) is performed again. -Perform SIM). Each of these operations is repeated as necessary. In the logic scan test flow shown in FIG. 75, first, the shift operation (SHIFT-SI) is performed while the SI signal is input, then the data capture (CAPTURE) is performed, and then the shift operation (SHIFT) is performed again. -SI). Each of these operations is repeated as necessary.

  Here, when the SI signal (logic data) or the SIM signal (RAM test data) is input, the SM signal is set to “1”, the INSFF signal and the WINH signal are set to “1” as shown in FIG. A SIM signal (Test Date) is input. At the time of data capture (CAPTURE), the SM signal is set to “0”. At this time, no data is output from the SOM. In the RAM test (TEST), the MEMTEST signal, the SINHDO signal, and the SM signal are set to “1” and the WINH signal is set to “0”, and desired data (0 or 1) is input from other terminals. That's fine.

  The transition of the data of each part in this operation will be described. First, as shown in FIG. 63, when the test circuit is operating (BIST state), the BIST signal is always set to “1” (= “High”), and the SI signal is shifted in (DATA SHIFT IN state). At this time, the test circuit 302 enters a test mode. The SINH-FF signal generates “0101010...” Based on the signal from the AND circuit 324. Then, the OR circuit 326 takes in the data (RUNBIST signal) stored in the FF 321 only when the SINH-FF signal is “0”, and supplies it to the shift register 312. The NOR circuit 327 outputs SINH0 as “1” only when the RUNBIST signal is “0” and the SINH-FF signal is “0”.

Here, at the time of initial setting (INIT. State), “0” is inserted for each bit in the bit string of data that should be originally initialized in the test pattern generation circuit 301. For example, “1011” as the data (SI signal) in the circuit shown in FIG.
When it is desired to execute an operation similar to that for shifting in a bit string such as “01 00 01 01” as an SI signal in this embodiment,
Shift in. At this time, the SINH-FF signal is “01 01 01 01”.
Therefore, the RUNBIST signal takes in the odd bits of the SI signal, and therefore holds “0”. In this case, the output (SINH1) of the OR circuit 326 outputs the SINH-FF signal as it is, as shown in FIG.
"10 10 10 10"
It becomes. The output (SINH0) of the NOR circuit 327 is also “10 10 10 10”.
Therefore, the shift register shifts only the timing of the divisor bit of the bit string of the SI signal, and therefore, the divisor bit of the bit string of the SI signal is taken into the shift register. That is,
“1011”
Is entered. When the test is executed (RUN state), the SI signal is “11 11 11 11”.
Shift in. At this time, SINH-FF is “01 01 01 01”.
Therefore, since odd bits are taken into RUNBIST, the state of “1” is held. Then, the output (SINH1) of the OR circuit 326 is always “1” as shown in FIG. 79, and the output (SINH0) of the NOR circuit 327 is always “0”. Then, one shift register 312 functions as, for example, the effective address number storage unit (MASKA) 37 or the two-dimensional pattern storage unit (MASKD) 111 in the fourth to eleventh embodiments, and the other shift register 313 is used. Functions as, for example, the address generation unit (ADDR) 35 and the control register (CARRY) 36 in the fourth to eleventh embodiments described above, thereby providing a predetermined signal (described in the fourth to fourth embodiments) to the test circuit 302. (SIA, CMPEN, SIW, etc. in the eleventh embodiment) are transmitted and the test is executed.

  As described above, when the test circuit operates (BIST state), the initial setting (INIT. State) and the test execution (RUN state) are alternately repeated. FIG. 80 shows an input example of the SI signal, and FIG. 81 shows transition examples of the SINH-FF signal, the RUNBIST signal, the SINH0 signal, and the SINH1 signal with respect to the SI signal. By operating in this way, a predetermined test operation as described in the fourth to eleventh embodiments is possible by providing data from only one pin (SI pin) at the time of test execution.

{Thirteenth embodiment}
<Configuration>
FIG. 82 shows a semiconductor memory and an inspection apparatus thereof according to the thirteenth embodiment of the present invention. Elements having the same functions as those in the twelfth embodiment are denoted by the same reference numerals. In the twelfth embodiment, since there is a possibility that malfunction occurs when the timing of the SINH-FF and the timing of the SI signal are shifted, the SINH-FF signal is generated only by the SI signal. The test pattern generation circuit 301, test circuit 302, RAM core 303, FFs 321 and 322, selector 323, NOT circuit 325, OR circuit 326, and NOR circuit 327 in FIG. 82 are connected in the same manner as described in the twelfth embodiment. Therefore, the description is omitted here. In the present embodiment, a three-terminal input AND circuit 344 is provided instead of the two-terminal input AND circuit (324) in the twelfth embodiment shown in FIG. Although one input terminal of the AND circuit 344 is connected to the BIST terminal and the other input terminal is connected to the output terminal of the NOT circuit 325, it is the same as in the twelfth embodiment. As shown in FIG. 82, the terminal is connected to mark detection means 345 for detecting a mark (“11”) included in the SI signal. Even when a deviation occurs between the timing of the SINH-FF and the timing of the SI signal, the timing deviation is corrected by detecting the mark (“11”) in the SI signal to prevent malfunction. A bit shift register 346 and a NAND circuit 347 having three terminal inputs, one of which is an inverting input terminal. The SI signal is input to the shift register 346 from the most significant bit (MSB) side. The most significant bit (MSB) of the shift register 346 is connected so that the SI signal stored here is transmitted as it is to the input terminal of the shift register 312 of the test pattern generation circuit 301 and the “0” side input terminal of the selector 323. Is done. The inverting input terminal of the NAND circuit 347 is connected to the most significant bit (MSB) of the shift register 346, and the other input terminals are connected to other bits of the shift register 346, respectively. The output terminal of the NAND circuit 347 is connected to the other input terminal of the AND circuit 344. The AND circuit 344 functions as a timing correction means for matching the instruction timing of the BIST signal (instruction signal) with the time point after the end of the mark of the SI signal based on the detection result of the mark detection means 345.

<Operation>
The normal operation (normal state) is as shown in FIG. 83 and is the same as in the twelfth embodiment.

When the test pattern generation circuit 301 is initially set (BIST-INIT. State), as shown in FIG. 83, the BIST signal is set to “1” (= “High”), and the SI signal is shifted in (DATA SHIFT IN state). I do. At this time, the test circuit 302 enters a test mode. Data in which “11” is inserted as a mark at the head of SI signal data similar to that of the twelfth embodiment shown in FIG. 80 is input as SI signal data. That is, as shown in FIG. 84 and FIG. 85, first, “11 01 01 00” is input to the shift register 346 as an SI signal.
Shift in. At this time, the output from the NAND circuit 347 is “11 01 11 11”.
Thereafter, “1” is continuously output. Then, the other input terminal of the AND circuit 344 always receives “0” from the NAND circuit 347 in the third bit. Accordingly, the AND circuit 344 always outputs “0” at the third bit. Thereafter, regardless of the output from the NOT circuit 325 before that, the AND circuit 344 always makes the third bit of the SI signal “01 01 01 01” based on the feedback of the inverted data by the FF 322 and the NOT circuit 325 thereafter. "
SINH-FF is output. Thereafter, as in the twelfth embodiment, the odd bits of the SI signal are taken into the RUNBIST signal, and therefore hold “0”. In this case, the output (SINH1) of the OR circuit 326 outputs the SINH-FF signal as it is, as shown in FIG.
"10 10 10 10"
It becomes. The output (SINH0) of the NOR circuit 327 is also “10 10 10 10”.
Therefore, the shift register shifts only the timing of the divisor bit of the bit string of the SI signal, and therefore, the divisor bit of the bit string of the SI signal is taken into the shift register. That is, only the even-numbered data is extracted from the SI signal after the end of the “11” data. At the time of test execution (RUN state), the SI signal indicates “11 11 11 11”.
Shift in. At this time, SINH-FF is “01 01 01 01”.
Therefore, since odd bits are taken into RUNBIST, the state of “1” is held. Then, the output (SINH1) of the OR circuit 326 is always “1” as shown in FIG. 79, and the output (SINH0) of the NOR circuit 327 is always “0”.

  As described above, according to the present embodiment, as shown in FIG. 85, when the “011” signal is given as the SI signal regardless of the SINH-FF signal, the circuit is automatically reset. Therefore, even if the test operation is an odd number cycle of the SI signal, no malfunction occurs. Other effects are the same as those of the twelfth embodiment.

{Embodiment 14}
<Configuration>
87 and 88 are block diagrams showing a semiconductor memory and an inspection apparatus (DFT-RAM) thereof according to the fourteenth embodiment of the present invention. 87 and 88 are broken along the line BB. Elements having the same functions as those in the twelfth embodiment are denoted by the same reference numerals. The DFT-RAM is a peripheral circuit that controls input / output of various signals to and from the RAM core (Core), and includes a scan path 332 as a plurality of shift registers around the asynchronous RAM core 331 and a single unit. The write pulse generator 333 is added. 63 corresponds to a peripheral circuit excluding the RAM core 331 in FIGS. 87 and 88. As shown in FIGS. 87 and 88, the scan path 332 (A-SCAN-0, A-SCAN-1) in the address portion can suppress the shift operation by the shift prohibition signal (SINHAX0, SINHAX1). The scan path 332 (DI-SCAN-0) of the data input unit can suppress the shift operation by the shift prohibit signal (SINHDI). The scan path 332 (DO-SCAN-1) of the data output unit can suppress the shift operation by the shift inhibition signal (SINHDO). The scan path 332 (A-SCAN-0, A-SCAN-1) in the address part has a bidirectional shift function, and a test using bidirectional pseudorandom addressing can be performed at high speed. In this case, the plurality of RAMs are connected by the connection method shown in FIG. The scan path 332 (DI-SCAN-0) of the data output unit is provided with a data compression function. The data compression function is achieved by inputting the SINH signal to each RAM 315 and prohibiting the shift operation for the desired RAM 315. However, as shown in FIG. By providing the flip-flop 317, data can be compressed by 1 bit before and after the flip-flop 317. Thus, as in the fourth conventional example shown in FIG. 132, the SINH signal is simultaneously applied to all the RAMs (RAM1, RAM2, RAM3) to prevent the shift-out operation for each test address. By using these pseudo-random addressing method and data compression method, it is possible to suppress the increase in test patterns and realize a high-speed test.

  The circuits of FIGS. 87 and 88 function like the equivalent circuits shown in FIGS. 89 and 90 by setting MEMTST0 = 1 in the test mode. 89 and 90 are broken along the line CC. That is, when MEMSTST0 (= 1) is input, the address for the scan path 332 (A-SCAN-0, A-SCAN-1) in the address part is from SIA, and the scan path 332 (DI-SCAN in the data input part). The write data for (−0) can be shifted in from the SID. The address input to the SIA is generated by the address generation method described in each of the above embodiments. At this time, the write enable signal (Low Enable) is supplied from SIW0, and the read enable signal (Low Enable) is supplied from the SIC. Further, an expected read data (EXP) signal to the scan path 332 (DI-SCAN-0) of the data output unit is supplied from an expected data input (EXP) terminal, and a comparison enable signal (CMPEN) is also supplied from a CMPEN terminal. Since these signals can be commonly connected to a plurality of RAMs as a test bus (TEST BUS), a plurality of RAMs can be tested simultaneously if the number of words is the same. It is designed so that the same address can be shifted in from the SIA for each port, and the multi-port RAM can be tested like a single-port RAM.

  If SINHA0, SINHA1, and SINHDI are set to 1, the shift operation can be stopped.

{Embodiment 15}
FIGS. 91 and 92 are block diagrams showing a semiconductor memory and an inspection apparatus thereof (1 Write 1 Read 2-port RAM) according to Embodiment 15 of the present invention. 91 and 92 are broken along the line DD. Elements having the same functions as those in the twelfth embodiment are denoted by the same reference numerals. As in the twelfth embodiment, the semiconductor memory inspection apparatus according to the present embodiment gives addresses and data individually to each scan path 332 as a shift register during normal operation, and the scan paths 332 in series during a RAM test. Connected and configured to sequentially shift data. However, in the semiconductor memory inspection apparatus of the present embodiment, the addressing system is divided into two systems: a write-only address (A0 <MSB: 0>) and a read-only address (A1 <MSB: 0>). In the same cycle, while writing to one address (A0 <n>), it is possible to simultaneously specify one address (A1 <n>) and perform data output (DO1 <n>). This is different from the twelfth embodiment.

  91 and 92, T0 is a write clock, and T1 is a read clock. As described above, the two types of clock input terminals are set in the normal operation (NORMAL) in the above-described two systems (write / read) addresses (A0 <MSB: 0>, A1 <MSB: 0>). ) In which separate circuits having different frequencies must be connected and accessed simultaneously. Thereby, for example, writing can be performed at 10 MH and reading can be performed at 20 MH. However, when the RAM test is performed, each scan path 332 (A-SCAN-0, A-SCAN-1, DI-SCAN-0, DO-SCAN-1) operates as a circuit connected in series. It is necessary to supply the same frequency clock to the scan path 332. Therefore, as shown in FIGS. 91 and 92, the shift operation of each scan path 332 is absorbed between the adjacent scan paths 332 by absorbing the shift between the timing of the write clock T0 and the timing of the read clock T1. Latch circuit (“L” in FIGS. 91 and 92) is interposed. The latch circuit (“L”) is configured to output a signal when T0 and T1 are negatively input and T0 and T1 = “Low”. Also according to the present embodiment, the same effects as those of the above embodiments can be obtained.

{Embodiment 16}
121 and 122 are diagrams showing a semiconductor memory and an inspection apparatus thereof according to the sixteenth embodiment of the present invention. The semiconductor memory inspection apparatus of the present embodiment is the same as that of the twelfth embodiment shown in FIG. It is similar. 121 and 122 are broken along the line GG. As the address input scan path 332 of the present embodiment, B-SCAN is used instead of the address input scan path 332 (A-SCAN) in the twelfth embodiment (FIG. 63). FIG. 123 shows the internal configuration of the B-SCAN. The B-SCAN is configured to input only the X address when there is no Y address, and is similar to the circuit of the twelfth embodiment (FIG. 70). That is, seven FFs (“A”) of XA0 to XA6 are connected in series and connected to the same B-SCAN of another adjacent single port RAM. However, in this embodiment, unlike the circuit shown in FIG. 70, when the CHDIR signal is set to “1”, the test address terminal TA (TA0, TA1, TA2,...) Side is selected. As shown in FIG. 121, the test address terminal TA is provided as a RAM pin. Therefore, the address can be set and tested in an arbitrary order. That is, B-SCAN can set addresses by serial shift operation when the CHDIR signal is “0”. When the CHDIR signal is “1”, addresses can be set in parallel by the test address terminal TA. An address signal for the test address terminal TA may be supplied from an external pin of the LSI, or may be supplied from a test address generation circuit (corresponding to 301 in FIG. 60) mounted in the LSI. As the test address generation circuit, an algorithmic pattern generator as provided in a memory LSI test apparatus may be used.

{Embodiment 17}
<Configuration>
Embodiment 17 of the present invention is a DFT-RAM type semiconductor memory inspection device, and FIG. 133 is a circuit diagram showing an outline of its control signal generation circuit 610. In general, since test pins are not used during normal operation, they are often switched between pins and selectors that are not used during test execution. However, there are some pins that cannot be inserted due to a problem that timing is shifted. Also, if the pin cannot operate at the same frequency as the internal frequency, it cannot be used as a test pin. The semiconductor memory inspection apparatus according to the present embodiment is applied to correct such a timing shift when an external signal is later than the shift timing of the shift register. A plurality of shift registers for transmitting a control signal to a test circuit connected to a memory core substantially delays the data shift by circulating the internal data, and corrects the timing described above. is there. That is, in this embodiment, a cyclic shift register 600 (hereinafter referred to as a cyclic shift register) 600 in which a loop is formed is applied as a shift register in the control signal generation circuit 610. The cyclic shift register 600 is connected in the control signal generation circuit 610 as shown in FIG. In FIG. 133, SI in each cyclic shift register 600 is a pin for inputting a shift inhibition signal (SI), SO is an output pin for outputting output data (SO) to the subsequent cyclic shift register 600, and DO is output data. This is a data output pin for outputting (DO). RUNBIST is a terminal for inputting a RUNBIST signal similar to that shown in FIG. 63, SINH-C is a terminal for inputting a SINH signal (shift prohibition signal), SR SINHDO, SR SINHDI, SR SINHA1, SR SINHA0 is a terminal for transmitting a prohibition signal to the test circuit.

  An internal configuration of one cyclic shift register 600 is shown in FIG. The cyclic shift register 600 includes a shift-in selector 601 that selects an SI signal from the pin SI and an SO signal to the pin SO as a data signal to be shifted in, and a first register unit 603 for data output (DO). And a second register unit 604 that outputs an SO signal to the subsequent cyclic shift register 600. The first register unit 603 and the second register unit 604 include flip-flops 606a and 606b and selectors 607a and 607b, respectively.

  The “0” side input terminal of the shift-in selector 601 is connected to the pin SI, and the “1” side input terminal is connected to the output terminal (that is, the SO terminal) of the second flip-flop 606b of the second register unit 604. Is done. The “0” side input terminal of the first selector 607a of the first register unit 603 is connected to the output terminal of the shift-in selector 601 and the “1” side input terminal is connected to the output terminal of the first flip-flop 606a. Connected. The input terminal of the first flip-flop 606a of the first register unit 603 is connected to the output terminal of the first selector 607a, and the output terminal of the first flip-flop 606a is connected to the DO terminal. The “0” side input terminal of the second selector 607b of the second register unit 604 is connected to the output terminal of the first flip-flop 606a of the first register unit 603, and the “1” side input terminal is Connected to the output terminal of the second flip-flop 606b. The input terminal of the second flip-flop 606b of the second register unit 604 is connected to the output terminal of the second selector 607b, and the output terminal of the second flip-flop 606b is connected to the SO terminal.

  In this manner, each of the register units 603 and 604 is provided with one flip-flop 606a and 606b and selectors 607a and 607b that select an input signal to the flip-flop 606a and 606b. It is possible to feed back the output from 606b and input it again to the flip-flops 606a and 606b. Further, by connecting the output terminal of the flip-flop of the second register unit 604 to one input terminal of the shift-in selector 601, the SO signal is re-input to the first register unit 603 by switching the RUNBIST signal. Is possible.

  The control signal generation circuit 610 is connected to the test circuit 611 as shown in FIGS. 135 and 136. 135 and 136 are broken along the line KK. SR SINHA1 and SR SINHA0 in FIGS. 135 and 136 are cyclic shift registers for generating a shift inhibition signal (SINHA1, SINHA0) for controlling the address input scan path (A-SCAN-1, A-SCAN-0). SR SINHDO is a cyclic shift register that generates a shift inhibition signal (SINHDO) for controlling the data output scan path (DO-SCAN-1), and SR SINHDI is a data input scan path (DI-SCAN-0). SR SIW is a cyclic shift register for generating a SIW signal for controlling a write signal (WEC) input register, and SR SIC is a read signal (REC). Control input registers SR SID is a cyclic shift register for data input, SR CMPEN is a cyclic shift register for transmitting a comparison enable signal (CMPEN) to the data output scan path, and SR EXP is a data output scan path Is a cyclic shift register for transmitting an expected value signal (EXP). 135 and 136, 613 is a test pattern generation circuit, 614 is an address pattern generation circuit, 615 is a RAM core, A00 to A03 are write address pins of the RAM core 615, A10 to A13 are read address pins, DI0 to DI3 are data input pins, and DO0 to DO3 are data output pins. The test pattern generation circuit 613 includes the address pattern generation circuit 614 and a plurality of 2-bit cyclic shift registers 600 (SR SINHA1, SR SINHA0, SR SINHDO, SR SINHDI, SR SIW, SR SIC, SR SID. , SR CMPEN, SR EXP).

<Operation>
The operation of the semiconductor memory inspection apparatus having the above configuration will be described. First, the initial value of the shift register is set. In this case, SINH-C = 0 and RUNBIST = 0 are set so that the shift register can be shifted. Then, initial value data is input from the input terminal SI. Next, the value of the shift register is held. Here, SINH-C = 1 is set, the shift operation of the shift register is prohibited, and data is held. Then, a test signal is generated. At this time, SINH-C = 0 and RUNBIST = 1 are set. For example, if “10” is set in the shift register, “1010...” Is generated as the DO signal.

  When REC = “0”, the RAM core 615 is read. Further, when WEC is “0”, data is written to the RAM core 615. The data output scan path (DO-SCAN-1) compares the data output of the RAM core 615 with the expected value (EXP) when CMPEN = “1”, and if these values are different, the data output scan path The value of (DO-SCAN-1) becomes “0”.

  Next, “111...” Is set in the data output scan path (DO-SCAN). In order to execute the test of the RAM core 615, it is necessary to set all of the data output scan paths (DO-SCAN) to “1”. In addition, SR SINHDI and SR SINHDO are set to “00”, “000...” Is output as a shift inhibition signal (SINHDI, SINHDO), a data input scan path (DI-SCAN) and a data output scan path (DO -SCAN) allows shift operation at normal operating frequency. Further, the SID is set to “1”, and the data input scan path (DI-SCAN) is initialized to “1”.

1. ALL-0 WRITE / READ Operation Here, the ALL-0 WRITE / READ operation will be described as an example of an operation during test execution. The ALL-0 WRITE / READ test is a method of reading all “0” data after inputting “0” as all data.

  First, all the data input scan paths (DI-SCAN) are set to “0” (ALL-0). In this case, SR SINHDO is set to “11”, the data output scan path (DO-SCAN) prohibits the shift operation, and holds the state of “1” (ALL-1) for all data. At this time, since writing to the RAM core 615 is not performed, SR SIW is set to “11”. Since reading to the RAM core 615 is not performed, SR SIC is set to “11”. Further, since the comparison between the data output of the RAM core 615 and the expected value (EXP) is not performed, SR CMPEN is set to “00”.

  Next, an initial value of the address is set in the address input scan path (A-SCAN-0, A-SCAN-1). In this case, “00” is set to SR SINHA0 and SR SINHA1, respectively. The SIA signal is transmitted from the address pattern generation circuit 614 to set the initial value of the RAM core 615 address. At this time, SR SINHDI and SR SINHDO are respectively set to “1”, and the shift operation of the data input scan path (DI-SCAN) and the data output scan path (DO-SCAN) is prohibited. At this time, since writing to the RAM core 615 is not performed, SR SIW is set to “11”. Since reading to the RAM core 615 is not performed, SR SIC is set to “11”. Since the data output of the RAM core 615 is not compared with the expected value (EXP), SR CMPEN is set to “00”.

  Subsequently, ALL-0 writing is executed. In this case, “00” is set to SR SINHA0 and SR SINHA1, respectively. Address pattern generation circuit 614 outputs a SIA signal to perform addressing. At this time, SR SINHDI and SR SINHDO are respectively set to “11”, and the shift operation of the data input scan path (DI-SCAN) and the data output scan path (DO-SCAN) is prohibited. SR SIW is set to “00” in order to write to the RAM core 615. Since the RAM core 615 is not read, SR SIC is set to “11”. Since the data output of the RAM core 615 and the expected value (EXP) are not compared, SR CMPEN is set to “00”.

  Next, an initial value of the address is set in the address input scan path (A-SCAN-0, A-SCAN-1). In this case, “00” is set to SR SINHA0 and SR SINHA1, respectively. The initial value of the address is set by the SIA signal from the address pattern generation circuit 614. At this time, SR SINHDI and SR SINHDO are respectively set to “11”, and the shift operation of the data input scan path (DI-SCAN) and the data output scan path (DO-SCAN) is prohibited. At this time, since writing to the RAM core 615 is not performed, SR SIW is set to “11”. Since the RAM core 615 is not read, the SR SIC is set to “11”. Since the comparison between the data output of the RAM core 615 and the expected value (EXP) is not performed, SR CMPEN is set to “00”.

  Then, reading of ALL-0 is executed. In this case, “00” is set to SR SINHA0 and SR SINHA1, respectively. Addressing is performed in a normal operation by the SIA signal from the address pattern generation circuit 614. At this time, SR SINHDI and SR SINHDO are respectively set to “11”, and the shift operation of the data input scan path (DI-SCAN) and the data output scan path (DO-SCAN) is prohibited. Further, the write signal SR SIW of the RAM core 615 is set to “11”, and writing to the RAM core 615 is prohibited. Further, the read signal SR SIC is set to “11”, and the RAM core 615 is read. SR CMPEN is set to “11” and SR EXP is set to “00”, and the data output of the RAM core 615 is compared with the expected value (EXP). At this time, if there is a failure in the RAM core 615, “0” is stored in the corresponding bit of the data output scan path (DO-SCAN).

2. March test Next, the March test will be described as an example. In this test, as described in the second conventional example, the initial storage data (for example, “0”) in the initial state is changed from the initial storage data (for example, “0”) to the new storage data (“1”). It is to be updated.

  First, similarly to the ALL-0 WRITE / READ operation, the data input scan path (DI-SCAN) is set to ALL-0. Next, an initial value of the address is set in the address input scan path (A-SCAN-0, A-SCAN-1). Then, ALL-0 writing is executed.

  Next, an initial value of the address is set in the address input scan path (A-SCAN-0, A-SCAN-1). Then, “1” is set in the data input scan path (DI-SCAN). “11” is set in SR SINHA0, SR SINHA1, and SR SINHDO, respectively. SR SINHDI is set to "00", SID is set to "1", and AL-1 is set to the data input scan path (DI-SCAN). Then, an initial address value is set in the address input scan path (A-SCAN-0, A-SCAN-1).

  Thereafter, “0” reading and “1” writing are performed. In this case, “01” is set in SR SINHA0 and SR SINHA1, respectively. Addressing is performed at half the frequency (1/2) of the normal operation by the SIA signal from the address pattern generation circuit 614. At this time, SR SINHDI and SR SINHDO are respectively set to “11”, and the shift operation of the data input scan path (DI-SCAN) and the data output scan path (DO-SCAN) is prohibited. Further, the SR SIW of the RAM core 615 is set to “10” and the SR SIC is set to “01”, and “0” reading and “1” writing are alternately performed. SR CMPEN is set to “01” and SR EXP is set to “00”, respectively, and the data output of the RAM core 615 is compared with the expected value (EXP). At this time, if there is a failure in the RAM core 615, “0” is stored in the corresponding bit of the data output scan path (DO-SCAN).

  Then, when the test result is output, “01” is set in the 2-bit cyclic shift register 600 (SR SINHA1, SR SINHA0, SR SINHDO, SR SINHDI). At this time, the shift operation signals SINHA0, SINHA1, SINHDI, and SINHDO generate "010101 ...". Therefore, the scan path in the test circuit of the RAM core 615 shifts out at an operating frequency that is half the normal operation (1/2), so that it can be assigned to an output pin corresponding to a low frequency as a test data output pin. .

  In this way, since both the first selector and the second selector are switched to the other input terminal and the output data is input again to the flip-flops of the register units, even if each register unit shifts, The data circulates in each register section and is again taken into the original flip-flop, so that the same action as that of substantially stopping the shift operation can be obtained, and the above-described timing shift is corrected. Can do. Accordingly, the number of test pins can be reduced, and a pin that cannot operate at the same frequency as the internal frequency can be used as the output pin of the test result.

{Embodiment 18}
<Configuration>
FIG. 137 shows a semiconductor memory inspection device (DFT-RAM) according to the eighteenth embodiment of the present invention. As shown in FIG. 137, the DFT-RAM according to the present embodiment is an application in which the 2-bit cyclic shift register 600 is applied to other control signal generation circuits of the DFT-RAM test circuit. A test pattern generation circuit 625 in which a circuit 621, an address generation circuit 622, a burn-in pattern generation circuit 623, and a data input circuit 624 are combined, and circuit timing correction means (321, 322, similar to that shown in FIG. 323, 325, 326, 327, 344, 345). The control signal generation circuit 621, the address generation circuit 622, the burn-in pattern generation circuit 623, and the data input circuit 624 are connected in series. As shown in FIG. 50 or FIG. 52, the burn-in pattern generation circuit can be easily combined with the address generation circuit or the control signal generation circuit, but here it is configured independently from other circuits.

  The test pattern generation circuit 625 is shown in more detail in FIGS. 138 and 139. Note that FIG. 138 and FIG. 139 are broken at line LL. In FIGS. 138 and 139, for simplicity, MEMST0 and MEMSTST1 are combined into one signal to be MEMST, INSFFA0 and INSFFA1, INSFFFI0, and INSFOFO1 are combined into one signal to be MEMSTT, and SELLSIM and EXP are combined into one signal. The signals are collectively expressed as EXP. In this embodiment, the bit write function test is not assumed. Note that the control signal generation circuit 621, the address generation circuit 622, the burn-in pattern generation circuit 623, and the data input circuit 624 in FIGS. 138 and 139 correspond to the test pattern generation circuit 301 in the thirteenth embodiment of FIG. ing.

  The function of each control signal in FIGS. 138 and 139 will be described. The SM signal is a shift mode switching signal for each shift register. SINHA1X is a shift inhibit signal for the read X address part shift register. SINHA1Y is a shift inhibit signal for the read Y address part shift register. SINHA0X is a shift inhibit signal for the write X address part shift register. SINHA0Y is a shift inhibit signal for the write Y address part shift register. SINHDO is a shift inhibition signal for the data input unit shift register. SINHDI is a shift inhibition signal for the data output unit shift register. These SINHA1X, SINHA1Y, SINHA0X, SINHA0Y, SINHDO, and SINHDI output “1” to inhibit the shift operation of each scan path in the test circuit 631 shown in FIGS. 140 and 141. 140 and 141 are diagrams showing a RAM core and a test circuit of the semiconductor memory inspection apparatus according to the present embodiment, which are broken along line MM.

  In addition, MEMTST makes each scan (A-SCAN-0, A-SCAN-1, DI-SCAN-0, DI-SCAN-1) in the test circuit 631 in parallel when MEMSTST = “1”. = “0”, the scans (A-SCAN-0, A-SCAN-1, DI-SCAN-0, DI-SCAN-1) of the test pattern generation circuit 613 are connected in series.

  SIW0 is a write signal, and when SIW = "0", writing to the RAM is performed. SIC is a read signal. When SIC = “0”, reading to the RAM is performed.

  The SID is input data of the data input unit shift register and the data output unit shift register. CMPEN is a comparison enable signal, EXP is an expected value, and the data output unit shift register compares the data output of the RAM core 632 with the expected value (EXP) when CMPEN = “1”. In this case, the value of the shift register becomes “0”.

  CHDIR indicates the direction of the shift operation of the address shift register. When CHDIR = “0”, the shift register shifts in the forward direction, and when CHDIR = “1”, the shift register shifts in the reverse direction.

  The WINH signal is a control signal for the write pulse generator of the RAM. When the WINH signal is “1”, writing to the RAM is prohibited.

  In the test pattern generation circuit 625 shown in FIGS. 138 and 139, control signals such as SINHAX1c, EXXYc, SINHAX0c, SINHDOc, SINHDIc, MEMSTc, SIW0c, SICc, SIDc, CMPENc, EXPc, CHDIRc, and SINH-LXc are generated. The control signal generation circuit 621 is formed by connecting all the 2-bit cyclic shift registers 600 in series as shown in the control signal generation circuit 610 in FIG. 133 and the FIG. 134 in the seventeenth embodiment. SINH-LXc is a shift register inhibition signal of the address generation circuit 622.

<Operation>
1) During normal operation First, during normal operation of the RAM, BURNIN = 0, RAMBIST = 0, SMX = 0, WINHX = 0, and INSFFX = 0. At this time, test buses other than SID, SIC, SIW0, and SIA are set to “0”, and the RAM test circuit is disabled (disabled). In addition, the SID, SIC, SIW0, and SIA signals do not affect the RAM when the MEMSTST signal is “0”, regardless of which value they are. 139 and 140, the shift registers A-SCAN-0, A-SCAN-1, DI-SCAN-0, and DO-SCAN-1 for the RAM test circuit are connected in series, and the SID, SIC , SIW0, SIA signals are not input to the shift registers.

2) At the time of a scan test At the time of a scan test of the LOGIC section, BURNIN = 0, RAMBIST = 0, SMX = 1/0, WINHX = 0/1, and INSFFX = 1. Here, it is assumed that the scan path between the RAM and the logic unit is connected as shown in FIG. At this time, when the MEMTEST is set to “0”, the RAM test circuit sets each shift register in the RAM to one scan path, and the SM signal is used to generate the same signal as the SM signal used for the LOGIC test. A generation circuit is configured. As a result, the scan path in the DFT-RAM can be handled in the same way as the scan path of the logic unit. The other test signals are set to “0” so as not to affect the scan test.

  Note that when the RAM test is performed in the scan test, the WINHX signal is set to “0” to permit writing to the RAM. When the RAM test is not performed, writing to the RAM is prohibited by setting the WINH signal to “1”.

3) When performing the burn-in test When executing the burn-in test, set BURNIN = "1". Here, the dynamic burn-in pattern is generated only by the BURNIN signal. The SIA signal, the SID signal, the SIC signal, and the SIW0 signal are generated by the burn-in pattern generation circuit 623 and supplied to the test circuit 631. In the present embodiment, the selector is configured to select the SIA signal, the SID signal, the SIC signal, and the SIW0 signal when the BURNIN signal is “1”. SINHA1X, SINHA1Y, SINHA0X, SINH0Y, SINHDO, and SINHDI are set to “0”, and the shift operation of each scan path is performed. In the present embodiment, since the BURNIN signal is “1” at the time of burn-in execution, the outputs SINHAX1c, SINHAY1c, SINHAX0c, SINHDOc, SINHDIc of the control signal generation circuit 621 and the inverted signal of the BURNIN signal are each taken. Thus, “0” is set and the shift operation of each scan path is performed.

  Then, MEMST is set to “1”, and each scan path is set in a parallel state. In the present embodiment, OR is performed between the MEMSTCc signal and the BURNIN signal, thereby generating “1” and setting each scan path in a parallel state. The SM signal is set to “1” to enter the shift mode. Here, the SM signal is set to “1” by ORing the SM signal and the BURNIN signal. The comparison enable signal (CMPEN) and EXP signal do not affect the operation of the RAM test circuit 631 during BURNIN. In BURNIN, each signal and an inverted signal of the BURNIN signal are ANDed so as to be fixed to “0”. The CHDIER signal and the EXXY signal need to be fixed to “0” or “1” at BURNIN. In the present embodiment, at the time of BURNIN, each signal and an inverted signal of the BURNIN signal are ANDed so that the CHDIER signal and the EXXY signal are fixed to “0”. When the WINH signal is BURNIN, writing to the RAM is controlled by SIW, so it is necessary to fix it to “1”. Here, fixing to “1” is realized by ANDing the WINH signal and the inverted signal of the BURNIN signal.

4) During RAM test When the RAM test mode is set, BURNIN = 0, RAMBIST = 1, SMX = 1, WINHX = 0, and INSFFX = 1. SINHAX1, SINHAX0, SINHDI, and SINHD0 generate “1”, inhibit the shift operation of each shift register of the test circuit 631 in the RAM, and hold the value of the shift register. The SIW0 signal generates “1” and prohibits writing to the RAM core 632. The WINH signal generates “1” and prohibits writing to the RAM core 632. The comparison enable signal (CMPEN) generates “0” and prohibits the comparison between the output from the RAM core 632 and the expected value (EXP).

  When the control signal generation circuit 621 and the address generation circuit 622 actually generate a test pattern (RUNBIST = “1”), the address generation circuit 622 generates a SIA signal.

  The SM, INSFF, and WINH signals are supplied to the DFT-RAM as they are, respectively.

  SIW0 is the OR of SIWc generated by the control signal and SIW0a generated from the address generation circuit 622.

  The comparison enable signal (CMPEN) is an AND of CMPENc generated as a control signal and CMPENa generated from the address generation circuit 622.

  As other signals, data output from the control signal generation circuit 621 is input to the DFT-RAM.

5) Description of Test Pattern Next, the test pattern generated by the control signal generation circuit 621 will be specifically described.

(ALL “1” / “0” test)
The ALL “1” / “0” test is performed in the following procedure.

  1. Set DO-SCAN to "111 ... 1".

  2. Set DI-SCAN to "111 ... 1".

  3. A-SCAN-0 and A-SCAN-1 are initialized.

  4). Since 1 is written in all the shift registers of DI-SCAN, in which data of DI-SCAN is written into RAM by forward addressing, all “1” is written as a result.

  5). A-SCAN-0 and A-SCAN-1 are initialized.

  6). The RAM data is read and compared with the expected value.

  That is, ALL “1” reading is performed.

  7). 2. ~ 6. A reverse (reverse) pattern is applied to the pattern. That is, ALL “0” writing / ALL “0” reading is performed.

  8.2. ~ 7. The same test is performed with reverse addressing.

  9. Output test results.

(March test)
The march test is conducted according to the following procedure.

  1. Set DO-SCAN to "111 ... 1".

  2. Set DI-SCAN to "111 ... 1".

  3. A-SCAN-0 and A-SCAN-1 are initialized.

  4). Write DI data to RAM with forward addressing.

  5). 1 read / 0 write is performed by forward addressing.

  6). Set DI-SCAN to "000 ... 0".

  7). A-SCAN-0 and A-SCAN-1 are initialized.

  8). 0 read / 1 write is performed by reverse addressing.

  9.2. ~ 8. A reverse (reverse) pattern is applied to the pattern.

  10. Output test results.

(Rover / Column bar / Checkerboard pattern test)
1. Set DO-SCAN to "111 ... 1".

  2. Set DI-SCAN to "111 ... 1".

  3. A-SCAN-0 and A-SCAN-1 are initialized.

  4). While performing addressing in the forward direction by the address generation circuit 622, the data of DI-SCAN is written into the RAM only at a specific address.

(ALL “1” write is performed only for a specific address.)
5). Set DI-SCAN to "000 ... 0".

  6). A-SCAN-0 and A-SCAN-1 are initialized.

  7). 3. performing forward addressing by the address generation circuit 622; The DI-SCAN data is written into the RAM for the address that was not written in (1).

(ALL “0” write is performed.)
8). A-SCAN-0 and A-SCAN-1 are initialized.

  9. While the address generation circuit 622 performs forward addressing, “1” read is performed on the address where “1” is written in 4.

  10. A-SCAN-0 and A-SCAN-1 are initialized.

  11. While performing forward addressing by the address generation circuit 622, “0” read is performed on the address where “0” is written in 7.

  12.2. ~ 11. A reverse (reverse) pattern is applied to the pattern.

  13.2. -12. Reverse addressing is performed.

  14 Output test results.

  In order to execute the test pattern as described above, the control signal generation circuit may be set as follows.

SM = “1” (this sets the DFT part to the scan mode)
MEMTST = “1” (This makes each scan of DFT parallel)
WINH = "0" (This enables the Write Pulse Generator of the RAM to be enabled)
(Set DO-SCAN to "111 ... 1")
Before starting the test, “111... 1” is set in advance in DO-SCAN as data for failure determination in DO-SCAN. The bit of the data that failed during the test execution becomes “0”, and the failure bit is known. Since SID = "1" is set as DO-SCAN input data, "11" is set in the cyclic shift register SID of the control signal generation circuit.

(Set DO-SCAN to "111 ... 1")
Data to be written to the RAM is set from the SID. The BIST controller of the present embodiment sets DI-SCAN in the following pattern.

“111 ...”
“000 ...”
“0101 ...”
"1010 ..."
At this time, CMPEN = “0” and SINH-DO = “1” are set so that the DO-SCAN data does not change. Also, SINH-AX0 and SINH-AX1 = "1" so that A-SCAN-0 and A-SCAN-1 do not change.

(A-SCAN-0, A-SCAN-1 initial setting)
The initial address value of the RAM is set.

  At this time, CMPEN = "0" and SINH-DO = "1" are set so that the DO-SCAN data does not change. Also, SINH-DI = "1" is set so that SI-SCAN data does not change.

(addressing)
The RAM address is given by inputting the SIA signal generated by the address generation circuit 622 from the address scan register.

  With respect to the write signal SIW0c and the comparison enable signal CMPENc generated by the control signal generation circuit 621, SIW = "" during the write operation of the RAM when performing the ALL "0" / "1" test and the row bar / column bar / checkerboard pattern test. Since 0 and CMPEN are preferably set to “0”, the control signals are set to SIW0 = “00” and CMPEN = “00” of the generation circuit, and SIW = “11” and CMPEN = “11” are set when reading the RAM. .

  In normal addressing, SINHA0X, SINHA0Y, SINHA1X, SINHA1Y are set to “0”, respectively, so that a shift operation is possible.

  The March test shifts the address once every two cycles. Therefore, by setting SINHLX = “01”, the address generation circuit 622 generates an address in two cycles. Similarly, since A-SCAN-0 and A-SCAN-1 shift once in two cycles, SINHA0X, SINHA0Y, SINHA1X, and SINHA1Y generate “010101.

  In the row bar / column bar / checkerboard pattern test, the address generation circuit 622 generates a write signal SIW0a and a comparison enable signal CMPENa for each pattern (as described in the specification of the address generation circuit 622). . When the RAM address is not 2n, the SIW0a signal and the comparison enable signal (CMPEN) are generated to prohibit writing and comparison when the shift register in the RAM address portion is not present.

  The comparison enable signal (CMPEN) generated from the test pattern generation circuit 625 takes an AND of the CMPENa signal from the address generation circuit 622 and the CMPENc signal from the control signal generation circuit 621. The SIW0 signal is ORed between the SIWa signal generated by the address generation circuit 622 and the SIWc signal from the control signal generation circuit 621.

  Set as SINH-A0 = "0", SINH-A1 = "0" for addressing like a single board RAM, or address only the write board with SINH-A0 = "0" and SINH-A1 = "1" it can.

  Reverse addressing is possible by setting CHDIR = “1”.

  EXXY is set to “1” and the lower address and the upper address are exchanged to perform addressing.

(Write to RAM)
Write the set value of SI-SCAN to RAM. For example, when “111... 1” is set in SI-SCAN, ALL “1” write is performed in the RAM. Set SIW = "0". At this time, CMPEN = "0" and SINH-DO = "1" are set so that the DO-SCAN data does not change. Also, SINH-DI = "1" is set so that SI-SCAN data does not change.

(Reads out RAM)
The RAM output data is read and compared with the expected value (EXP). When the output data and the expected value are different, the FF of the failed bit of the DO-SCAN is reset to “0”. Similar to the WRITE instruction, the same addressing as the single board RAM and the addressing of only the read port are possible. Further, by setting CHDIR = “1”, reverse addressing is possible.

  At this time, SINH-DO = "1" is set so that DO-SCAN data does not shift.

(“1” write / “0” read is performed)
In this command, the set value of SI-SCAN is written to the RAM, the output data of the RAM is read and compared with the expected value (EXP). For example, when “1111 ... 1” is set in SI-SCAN and EXP = “0”, “1” write / “0” read is obtained. By setting SIC = “01”, SIW = “10”, and CMPEN = “10” in the cyclic shift register of the control signal generation circuit,
SIC = “010101 ...”
SIW = “101010 ...”
CMPEN = "101010 ..."
Set SINH-A0 / SINH-A1 = “010101. By setting CHDIR = “1”, addressing in the reverse direction is possible.

(Test result output)
Setting of SINHA0X, SINHA1X, SINHA1X, SINHA1Y, SINHDI, and SINHDO is performed in the same manner as described in the seventeenth embodiment. For other signals, “00” is set in each cyclic shift register 600 so that the test circuit 631 is not affected.

  As described above, a test signal suitable for the DFT-RAM can be generated with a simple circuit constituted by the 2-bit cyclic shift register 600.

  Further, since the same circuits are connected in series, the function can be easily expanded / reduced with respect to the test pins of the RAM.

  Further, the shift operation speed is freely changed by generating a circuit for generating the shift prohibition signal in the cyclic shift register 600. In particular, the normal operation test is performed during the test execution, and when the test result is output, the frequency is lower than that in the normal operation, and the output can be output from the output pin that does not support the high speed operation.

{Embodiment 19}
<Configuration>
FIG. 142 is a block diagram showing an overview of the entire semiconductor memory inspection device with a self-correcting function according to the nineteenth embodiment of the present invention. The semiconductor memory inspection device with a self-repair function is configured to operate the system with a redundant circuit even when a failure occurs in the RAM. Reference numeral 701 detects power-on and outputs a reset signal. A known power-on reset circuit (Power On Reset Circuit), 702 is a self-test circuit (Self Test Circuit) that performs a RAM test based on a reset signal from the power-on reset circuit 701, and 703 is a RAM with a test circuit (RAM with Test). Circuit), 704 is a redundancy circuit that compensates for errors occurring in the data, 705 is a logic circuit (Logic Circuit) that has been subjected to a predetermined logic configuration, and 706 is binary data that indicates whether or not an error has occurred in the data. Is a register circuit (Register Circuit: holding means: binary data holding means). The semiconductor memory inspection apparatus may be configured on a one-chip LSI, or may be configured by a plurality of chips or individual components. When the RAM 703 with a test circuit has a register function (holding means) (for example, as shown in FIG. 1 or FIGS. 6, 11, 17, 18, 19, 20, and 21) In the case where a plurality of flip-flops provided with loop wiring for data feedback are provided), the register circuit 706 can be omitted.

  The self-test circuit 702 uses a microcomputer 702a as shown in FIG. The self-test operation is controlled by a program stored in a ROM or RAM (not shown) in the microcomputer 702a. It is also possible to take a test result (Test Result) into the microcomputer 702a and transmit it from the input / output port of the microcomputer 702a to the outside of the system (for example, an upper layer system). As a result, the failure can be recognized by the upper layer system, and the maintenance of the upper layer system becomes easy. For example, when a number of failures that cannot be remedied by the redundant circuit 704 occur, the higher-layer system can recognize this and stop the system operation. In FIG. 143, Reset Signal is a reset signal from the power-on reset circuit 701, Test Pattern is a test pattern signal output to the RAM 703 with a test circuit, and Register Control is a register control signal output to the register circuit 706. .

  First, a description will be given of the redundant circuit 704 configured so that only one bit can be relieved. 144 is a diagram showing a detailed connection example of the RAM 703 with a test circuit and the redundant circuit 704 in FIG. As the RAM 703 with a test circuit, for example, the configuration shown in FIGS. 64 and 65 may be used. In FIG. 144, signals SO <0> to SO <5> (hereinafter abbreviated as SO <>) are test result signals. This is the serial output signal SO. In addition, in the RAM 703 with a test circuit in FIG. 144, A <0> to A <3> (hereinafter abbreviated as A <>) are address signals, and DI <0> to DI <5> (hereinafter DI <>). Is a data input terminal, WE is a write enable terminal, DO <0> to DO <5> (hereinafter abbreviated as DO <>) is a data output terminal, and BWC <0> to BWC <5> (hereinafter, abbreviated). , And abbreviated as BWC <>) are bit write control terminals. In this example, a RAM having four address signals and six data bits is shown. BWC <> is a signal for controlling writing for each data bit. For example, BWC <3> = “1”, BWC <0> = “0”, BWC <1> = “0”, BWC <2> = “0”, BWC <4> = “0”, BWC <5 When> = “0” is set and the WE signal is activated, the data of DI <3> is not written.

  The redundant circuit 704 has a circuit configuration as shown in FIGS. 145 and 146. In the redundant circuit 704, DI <0> to DI <4> (hereinafter abbreviated as DI <>) are data input signal output terminals, and DO <0> to DO <4> (hereinafter abbreviated as DO <>). ) Is a data output signal input terminal, G <0> to G <5> (hereinafter abbreviated as G <>) are test result input terminals, and BWC <0> to BWC <5> (hereinafter abbreviated as BWC <>). Is a bit write control signal output terminal, XDI <0> to XDI <4> (hereinafter abbreviated as XDI <>) are data input terminals, and XDO <0> to XDO <4> (hereinafter referred to as XDO <>). (Abbreviated) is a data output terminal and XBWC <0> to XBWC <4> (hereinafter abbreviated as XBWC <>) are bit write control terminals.

  Further, 711 to 715 in the redundant circuit 704 are arranged in signal lines Ldi0 to Ldi4 that connect between DI <> and XDI <>, and when defective bit data is given to any of the signal lines. The selector disconnects the signal line (“1” side) and sequentially connects to the adjacent signal line (“0” side) with the signal line as a boundary. 721 to 725 are arranged in signal lines Lbw0 to Lbw4 that connect between BWC <> and XBWC <>. When a defective bit is given to any of the signal lines Lbw0 to Lbw4, the signal lines (" 1 "side), and a selector that sequentially switches and connects to adjacent signal lines (" 0 "side) with the signal line as a boundary. Reference numerals 731 to 735 are arranged in the signal lines Ldo0 to Ldo5 that connect between DO <> and XDO <>. When a defective bit is given to any of the signal lines Ldo0 to Ldo5, the signal lines (" 1 "side), and a selector that sequentially switches and connects to adjacent signal lines (" 0 "side) with the signal line as a boundary.

  Reference numeral 740 controls switching of the selectors 711 to 715 and 721 to 725, and is a signal designated as a defective bit among the plurality of signal lines Ldi0 to Ldi4, Lbw0 to Lbw4, Ldo0 to Ldo5. This is a binary signal designating unit that outputs “1” to the selector of the signal line on one direction side (LSB side) with the line as the boundary, and outputs “0” to the signal line on the other direction side (MSB side).

  Specifically, the binary signal designating unit 740 includes five AND circuits (logical product circuits) 741 to 745. One input terminal of the first AND circuit 741 on the most LSB side is connected to the G <0> terminal of the register circuit 706, and the other input terminal is connected to the G <1> terminal of the register circuit 706. One input terminal of the second AND circuit 742 adjacent to the first AND circuit 741 is connected to the output terminal of the first AND circuit 741, and the other input terminal is G <2 of the register circuit 706. > Connected to the terminal. One input terminal of the third AND circuit 743 adjacent to the second AND circuit 742 is connected to the output terminal of the second AND circuit 742, and the other input terminal is G <3 of the register circuit 706. > Connected to the terminal. One input terminal of the fourth AND circuit 744 adjacent to the third AND circuit 743 is connected to the output terminal of the third AND circuit 743, and the other input terminal is G <4 of the register circuit 706. > Connected to the terminal. One input terminal of the fifth AND circuit 745 adjacent to the fourth AND circuit 744 is connected to the output terminal of the fourth AND circuit 744, and the other input terminal is G <5 of the register circuit 706. > Connected to the terminal.

  The output terminal of the first AND circuit 741 is connected to the switching control terminals of the selectors 711, 721, and 732. The output terminal of the second AND circuit 742 is connected to the switching control terminals of the selectors 712, 722 and 733. The output terminal of the third AND circuit 743 is connected to the switching control terminals of the selectors 713, 723, and 734. The output terminal of the fourth AND circuit 744 is connected to the switching control terminal of the selectors 714, 724, 735. The output terminal of the fifth AND circuit 745 is connected to the switching control terminals of the selectors 715 and 725. The switching control terminal of the selector 731 is connected to the G <0> terminal of the register circuit 706.

  Further, reference numeral 750 in FIG. 145 denotes a control element group for transmitting a write suppression signal (“1”) to the BWC <> based on the G <> signal from the register circuit 706. And an OR circuit 752 for inputting a signal from the inverter circuit 751 to one terminal and inputting a signal from the selectors 721 to 725 to the other terminal. The Note that the control element group 750 can be omitted for a RAM having no BWC <> terminal.

<Operation>
The operation of the semiconductor memory inspection apparatus having the above configuration will be described. First, the power-on reset circuit 701 detects power-on, and gives a reset signal to the self-test circuit 702. As a result, the self-test circuit 702 automatically starts a RAM test. The self-test circuit 702 tests the RAM core in the RAM 703 with a test circuit, and the test result is output from the RAM 703 with a test circuit.

  The register circuit 706 is controlled by the self test circuit 702 so that the test result is captured after the self test circuit 702 finishes the RAM test. The register circuit 706 may be a parallel register circuit 706 or a serial shift register. The redundancy circuit 704 switches the connection between the RAM input / output data and the bit write control signal and the logic circuit 705 according to the test result. Even if there is a failure in the RAM, the connection is switched so that the failure bit is not used, and the normal function of the system can be maintained.

  Address signals and control signals are given from the logic circuit 705 to the RAM 703 with a test circuit.

  XDI <>, XBWC <>, and XDO <> are connected to another logic circuit 705 on the LSI to realize a desired operation as an LSI.

  The description will be made assuming that the G <> terminal is set to “0” for a failure bit and “1” for a bit without a failure according to the RAM test result.

  When there is no failure in the RAM, G <5> to G <0> are all “1”. As a result, F <5> to F <1> are all “1”.

  At this time, the following signal path is configured.

  (1) A signal of XDI <0> is supplied from XDI <4> to DI <4> to DI <0> (signal line), and a fixed “ 0 "or" 1 "is supplied.

  (2) The signals XBWC <4> to XBWC <0> are supplied to BWC <4> to BWC <0> (signal line) and fixed to BWC <5> (spare line). 1 "is supplied (" 1 "is a write-inhibited state, and writing is not performed for bit number 5).

  (3) Signals of DO <4> to DO <0> (signal lines) are supplied from XDO <4> to XDO <0>. That is, bit number 5 becomes unused and data input / output operates as a 5-bit RAM. DO <5> is a spare line.

  For example, when bit number 3 has a failure, G <5>, G <4>, G <2>, G <1>, G <0> are “1”, and G <3> is “0”. become. As a result, F <5>, F <4>, and F <3> are “0”, and F <2> and F <1> are “1”. At this time, the following signal path is configured.

(1) For DI <5>, the XDI <4> signal is
For DI <4>, the XDI <3> signal is
For DI <3>, the XDI <2> signal is
For DI <2>, the XDI <2> signal is
For DI <1>, the XDI <1> signal is
For DI <0>, the XDI <0> signal is
Each is supplied.

(2) For BWC <5>, the XBWC <4> signal is
For BWC <4>, the XBWC <3> signal is
For BWC <3>, “1” is set by the inverter circuit 751 and the OR circuit 752.
For BWC <2>, the XBWC <2> signal is
For BWC <1>, the XBWC <1> signal is
For BWC <0>, the XBWC <0> signal is
Each is supplied ("1" is a write suppression state, and no write is performed for bit number 3 which is defective).

(3) For XDO <4>, the DO <5> signal is
For XDO <3>, the DO <4> signal is
For XDO <2>, the DO <2> signal is
For XDO <1>, the DO <1> signal is
For XDO <0>, the DO <0> signal is
Each is supplied.

  That is, bit number 3 becomes unused, and data input / output operates as a 5-bit RAM.

  As described above, even if there is a 1-bit failure in data input / output, it can operate as a desired (5-bit) RAM.

{Embodiment 20}
FIG. 147 shows a self-test circuit 702 according to the twentieth embodiment of the present invention. The circuit of FIG. 147 has the same function as that of the circuit shown in FIG. 143 in the nineteenth embodiment, but a dedicated test pattern generation circuit (Pattern Generator) 702b is added. This is effective when the operation speed of the microcomputer is slower than the operation speed of the RAM. The dedicated test pattern generation circuit enables high-speed test pattern generation, and can detect failures such as RAM access time defects. As the test pattern generating circuit, for example, the circuits shown in FIGS. 138 and 139 may be used. Other configurations are the same as those shown in FIGS. 142 to 146, and thus description thereof is omitted. With respect to such other configurations, the same effects as in the nineteenth embodiment can be obtained also in the present embodiment.

{Embodiment 21}
<Configuration>
FIGS. 148 and 149 show redundant circuit 704a (704) of the semiconductor memory inspection device according to the twenty-first embodiment of the present invention. With respect to the bit at the upper end (MSB), instead of inputting a fixed value by the selector (selectors 715 and 725 in the nineteenth embodiment), a fixed value is input by the gate circuits (OR circuits) 761 and 762. Further, paying attention to the fact that the value of any adjacent bit may be used as the input data or the bit write control signal for the failed bit, the control signal from the binary signal designating unit 740 is represented by F <1> to F. <5> is changed to G <0> and F <1> to F <4>. As a result, an AND circuit (AND circuit 745 in the nineteenth embodiment) for generating the F <5> signal is not necessary.

<Operation>
The operation of the semiconductor memory inspection apparatus having the above configuration will be described. When there is no failure in the RAM, G <5> to G <0> are all “1”. As a result, F <4> to F <1> are all “1”.

  At this time, the following signal path is configured.

  (1) Signals XDI <4> to XDI <0> are supplied to DI <4> to DI <0>, and a fixed “1” is supplied to DI <5>.

  (2) The signals XBWC <4> to XBWC <0> are supplied from BWC <4> to BWC <0>, and a fixed “1” is supplied to BWC <5> (“ 1 ″ is a write suppression state, and no write is performed for bit number 5).

  (3) The signals DO <4> to DO <1> are supplied to XDO <4> to XDO <0>. That is, bit number 5 becomes unused and data input / output operates as a 5-bit RAM.

  For example, when bit number 3 has a failure, G <5>, G <4>, G <2>, G <1>, G <0> are “1”, and G <3> is “0”. become. As a result, F <4> and F <3> become “0”, and F <2> and F <1> become “1”.

  At this time, the following signal path is configured.

(1) For DI <5>, the XDI <4> signal is
For DI <4>, the XDI <3> signal is
For DI <3>, the XDI <3> signal is
For DI <2>, the XDI <2> signal is
For DI <1>, the XDI <1> signal is
For DI <0>, the XDI <0> signal is
Each is supplied.

(2) For BWC <5>, the XBWC <4> signal is
For BWC <4>, the XBWC <3> signal is
For BWC <3>, “1” is set by the inverter circuit 751 and the OR circuit 752.
For BWC <2>, the XBWC <2> signal is
For BWC <1>, the XBWC <1> signal is
For BWC <0>, the XBWC <0> signal is
Each is supplied ("1" is a write suppression state, and no write is performed for bit number 3).

For XDO <4>, the DO <5> signal is
For XDO <3>, the DO <4> signal is
For XDO <2>, the DO <2> signal is
For XDO <1>, the DO <1> signal is
For XDO <0>, the DO <0> signal is
Each is supplied.

  That is, bit number 3 becomes unused, and data input / output operates as a 5-bit RAM.

  As described above, even if there is a 1-bit failure in data input / output, it can operate as a desired (5-bit) RAM.

  The signals connected to the DI <> terminal of the failure bit are different between the circuits of FIGS. 145 and 146 and the circuits of FIGS. 148 and 149. For example, when there is a failure in bit number 3, the XDI <2> signal is connected to DI <3> in the circuits of FIGS. 145 and 146, whereas DI <3 in the circuits of FIGS. 148 and 149. Is connected to the XDI <3> signal. Since bit number 3 is not used, there is no difference in system operation.

{Twenty-second embodiment}
<Configuration>
FIG. 150 is a diagram of another embodiment showing a detailed connection example of the RAM 703 with a test circuit and the redundant circuit 704b of FIG. 142 in the twenty-second embodiment of the present invention. In FIG. 150, a redundant circuit 704b for remedying a 2-bit defect is used.

  151 and 152 are circuit diagrams of the 2-bit redundant circuit 704b used in FIG. The redundant circuit 704b can operate as a desired RAM even if a 2-bit failure exists in data input / output. That is, in this embodiment, after detecting a defective bit along one direction, a defective bit is further detected along the opposite direction, so that a total of two bits of defective data are taken out. 151 and 152 show a redundant circuit 704b when a 6-bit data input / output RAM is prepared and used as a 4-bit data input / output RAM. 151 and 152, YDI <> is a data input terminal, YBWC <> is a bit write control terminal, and YDO <> is a data output terminal.

  Specifically, in addition to the same configuration as that of the embodiment 21 shown in FIGS. 148 and 149, selectors 771 to 773 for switching signals from YDI <> and a gate circuit (OR circuit) 774, Selectors 781 to 783 and gate circuits (OR circuits) 784 for switching signals from YBWC <> and selectors 791 to 794 for switching signals to YDI <> are provided.

  Among these, 771 to 773 are arranged in the signal lines Lydi0 to Lydi3 that connect between the selectors 711 to 714 (primary selector unit) and YDI <>, and when defective bit data is given to any of the signal lines And a selector (secondary selector section) that cuts off the signal line (“1” side) and sequentially switches and connects to the adjacent signal line (“0” side) with the signal line as a boundary. The gate circuit (OR circuit) 774 is used to input a fixed value to the lower end (LSB) bit (ie, DI <0>), and one terminal is connected to the YDI <0> terminal. The other terminal is connected to an output terminal of an AND circuit (logical product circuit) 803 of a second binary signal designating unit 800 described later.

  Reference numerals 781 to 783 are arranged in signal lines Lybw0 to Lybw3 that connect between the selectors 721 to 724 (primary selector section) and YBWC <>, and a defective bit is given to any one of the signal lines Lybw0 to Lybw3. In this case, the selector (secondary selector unit) disconnects the signal line (“1” side) and sequentially switches and connects to the adjacent signal line (“0” side) with the signal line as a boundary. 791 to 794 are arranged in signal lines Lxdo0 to Lxdo4 that connect between the selectors 731 to 735 (primary selector unit) and YDO <>, and when any one of the signal lines Lxdo0 to Lxdo4 is given a defective bit. A selector (secondary selector unit) that cuts off the signal line (“1” side) and switches and connects to the adjacent signal line (“0” side) sequentially with the signal line as a boundary. The gate circuit (OR circuit) 784 is for inputting a fixed value to the bit at the lower end (LSB) (that is, the OR circuit 752 connected to BWC <0> of the control element group 750). Is connected to the YBWC <0> terminal, and the other terminal is connected to the output terminal of the AND circuit 803 of the second binary signal designating unit 800 described later.

  800 designates switching control of the selectors 771 to 773, 781 to 783, and a signal designated as a defective bit among the plurality of signal lines Lydi0 to Lydi3, Lybw0 to Lybw3, Lxdo0 to Lxdo4. “0” is output to the selectors 771, 772, 781, 782, 791 to 793 and the OR circuits 774 and 784 of the signal lines on one direction side (LSB side) with the line as the boundary, and on the other direction side (MSB side) A second binary signal designating unit (secondary control circuit) that outputs “1” to the signal line selectors 771, 772, 781, 782, 791 to 793 and the OR circuits 774 and 784. The first binary signal designating unit 740 (primary control circuit) detects a defective bit from the opposite direction on the LSB side and the MSB side. This is because the two-bit signal specifying units 740 and 800 detect defective bits from both the LSB side and the MSB side, thereby detecting a total failure of 2 bits.

  Specifically, the binary signal designating unit 800 includes three AND circuits (secondary AND circuits) 801 to 803. In this case, the four AND circuits 741 to 744 of the first binary signal designating unit 740 function as primary AND circuits for the AND circuits 801 to 805. One input terminal of the fifth AND circuit 801 on the most MSB side is connected to the G <5> terminal of the register circuit 706, and the other input terminal is connected to the G <4> terminal of the register circuit 706. One input terminal of the sixth AND circuit 802 adjacent to the fifth AND circuit 801 is connected to the output terminal of the first AND circuit 801, and the other input terminal is G <3 of the register circuit 706. > Connected to the terminal. One input terminal of the seventh AND circuit 803 adjacent to the sixth AND circuit 802 is connected to the output terminal of the sixth AND circuit 802, and the other input terminal is G <2 of the register circuit 706. > Connected to the terminal.

  The output terminal H <4> of the fifth AND circuit 801 is connected to the switching control terminals of the selectors 772, 782, and 793. The output terminal H <3> of the sixth AND circuit 802 is connected to the switching control terminals of the selectors 771, 781, 792. The output terminal of the seventh AND circuit 803 is connected to one terminal of the OR circuits 774 and 784 and the switching control terminal of the selector 791.

  Other configurations are the same as those in the twenty-first embodiment, and thus description thereof is omitted.

<Operation>
The circuit operation of FIGS. 151 and 152 will be described. When there is no failure in the RAM, G <5> to G <0> of the register circuit 706 are all “1”. As a result, the output terminals F <4> to F <1> of the first binary signal specifying unit 740 are all “1”, and the output terminals H <2> to F <2> of the second binary signal specifying unit 800 are further set. H <4> is all “1”. At this time, the following signal path is configured.

  (1) Signals YDI <3> to YDI <0> are supplied to DI <4> to DI <1>, and a fixed “1” is supplied to DI <5> and DI <0>. Is done.

  (2) The signals YBWC <3> to YBWC <0> are supplied to the OR circuit 752 (control element group 750) for BWC <4> to BWC <1>, and BWC <5> and BWC < A fixed “1” is supplied to the OR circuit 752 (control element group 750) for 0> (“1” is in a write-inhibited state, and no write is performed for bit number 5). . Therefore, “1” is supplied to all BWC <>.

  (3) The signals DO <4> to DO <1> are supplied to YDO <3> to YDO <0>. That is, bit numbers 5 and 0 are unused, and data input / output operates as a 4-bit RAM.

  Here, for example, when there is a failure in bit numbers 2 and 4, G <5>, G <3>, G <1>, and G <0> among the output terminals of the register circuit 706 are “1”. G <4> and G <2> are “0”. As a result, among the output terminals of the first binary signal designating unit 740, F <4>, F <3>, F <2> are “0”, and F <1> is “1”. Further, the output terminals H <4>, H <3>, and H <2> of the second binary signal designating unit 800 are “0”.

  At this time, the following signal path is configured.

(1) For DI <5>, the YDI <3> signal is
For DI <4>, the YDI <3> signal is
For DI <3>, the YDI <2> signal is
For DI <2>, the YDI <2> signal is
For DI <1>, the YDI <1> signal is
For DI <0>, the YDI <0> signal is
Each is supplied.

(2) For BWC <5>, the YBWC <3> signal is
For BWC <4>, “1” is set by the inverter circuit 751 and the OR circuit 752.
For BWC <3>, the YBWC <2> signal is
For BWC <2>, “1” is set by the inverter circuit 751 and the OR circuit 752.
For BWC <1>, the YBWC <1> signal is
For BWC <0>, the YBWC <0> signal is
Each is supplied ("1" is a write-inhibited state, and writing is not performed for bit numbers 4 and 2). Also,
For YDO <3>, the DO <5> signal is
For YDO <2>, the DO <3> signal is
For YDO <1>, the DO <1> signal is
For YDO <0>, the DO <0> signal is
Each is output.

  That is, bit numbers 4 and 2 are unused, and data input / output operates as a 4-bit RAM.

Thus, according to the circuit configurations of FIGS. 151 and 152,
(1) The defective bit is searched from the LSB side by the action of the AND circuit that generates the F <> signal.

  (2) The defective bit is searched from the MSB side by the action of the AND circuit that generates the H <> signal.

  (3) The selectors 711 to 714, 721 to 724, 731 to 735, 771 to 773, 781 to 783, 791 to 794 are switched so as not to select a defective bit based on the search results of (1) and (2). .

  As described above, even if a 2-bit failure exists in data input / output, the circuits of FIGS. 151 and 152 can operate as a desired (4-bit) RAM by using two types of search directions. That is, defects up to 2 bits can be remedied.

{Embodiment 23}
<Configuration>
153 and 154 are diagrams showing a redundant circuit of the semiconductor memory inspection device according to the twenty-third embodiment of the present invention. In FIG. 153 and FIG. 154, elements having the same functions as those in the above embodiments are given the same reference numerals.

  The redundancy circuits 704a and 704c of the semiconductor memory inspection device according to the present embodiment perform the 1-bit defect data compensation in the first layer, and then remove such defect information, and further, the 1-bit in the second layer. Defective data compensation is performed. A 2-bit redundant circuit used in place of the circuits of FIGS. 151 and 152 in the twenty-second embodiment, in particular, redundant circuit 704a is similar to that shown in FIGS. 148 and 149, and is redundant. The circuit 704c (portion surrounded by a broken line: hereinafter referred to as a second-stage redundant circuit) adds (hierarchizes) a second-stage redundant circuit to the redundant circuit 704a.

  In the second-stage redundancy circuit 704c, 811 to 813 are arranged in signal lines Lydi0 to Lydi3 that connect between the selectors 711 to 714 (first layer selector unit) and YDI <>, and any one of the signal lines When defective bit data is given to the selector, the signal line ("1" side) is disconnected and the selector (second circuit) is switched and connected to the adjacent signal line ("0" side) sequentially with the signal line as a boundary. Layer selector). 821 to 823 are arranged in signal lines Lybw0 to Lybw3 that connect between the selectors 721 to 724 (first layer selector unit) and YBWC <>, and when a defective bit is given to any one of the signal lines A selector (second-layer selector unit) that cuts off the signal line (“1” side) and sequentially switches and connects to the adjacent signal line (“0” side) with the signal line as a boundary. 831 to 833 are arranged in a signal line that connects between the first binary signal designating unit 740 (primary control circuit) and a second binary signal designating unit 840 described later. When defective bit data is given, the control selector cuts the signal line (“1” side) and sequentially switches and connects to the adjacent signal line (“0” side) with the signal line as a boundary. . The control selectors 831 to 833 and the second binary signal designating unit 840 constitute a secondary control circuit for switching the selectors 811 to 813, 821 to 823, 791 to 794 (second layer selector unit). The selectors 731 to 735 (first layer selector unit) and 791 to 794 (second layer selector unit) for switching signals to YDI <> are the same as those of the twenty-second embodiment shown in FIGS. 151 and 152. It is the same.

  Further, regarding the signal line connecting DI <> and YDI <> and the signal line connecting BWC <> and YBWC <> in the figure, gate circuits (OR circuits) 861, 862 with respect to the bit at the upper end (MSB). A fixed value is entered in. Reference numeral 863 denotes an OR circuit that takes a logical sum of G <0> and G <1> from the register circuit 706.

  Reference numeral 840 controls switching of the selectors 811 to 813, 821 to 823, 791 to 794, and is one-way with a signal line designated as a defective bit among a plurality of signal lines as a boundary. This is a second binary signal designating unit that outputs “1” to the selector of the signal line on the side (LSB side) and outputs “0” to the signal line on the other direction side (MSB side).

  Specifically, the second binary signal specifying unit 840 includes four AND circuits (secondary AND circuits) 841 to 843. One input terminal of the fifth AND circuit 841 closest to the LSB side is connected to the output terminal of the OR circuit 863, and the other input terminal is connected to the output terminal of the selector 831. One input terminal of the sixth AND circuit 842 adjacent to the fifth AND circuit 841 is connected to the output terminal of the fifth AND circuit 841, and the other input terminal is connected to the output terminal of the selector 832. The One input terminal of the seventh AND circuit 843 adjacent to the sixth AND circuit 842 is connected to the output terminal of the sixth AND circuit 842, and the other input terminal is connected to the output terminal of the selector 833. The

  The output terminal XF <1> of the fifth AND circuit 841 is connected to the switching control terminals of the selectors 812, 822, and 792. The output terminal of the sixth AND circuit 842 is connected to the switching control terminals of the selectors 813, 823 and 793. The output terminal of the seventh AND circuit 843 is connected to the OR circuits 861 and 862 and the switching control terminal of the selector 794. The output terminal of the OR circuit 863 is connected to the switching control terminals of the selectors 811, 821, 791.

  In the present embodiment, the G <> signal from the register circuit 706 is used as the defect information at the first stage, and the XG <> signal from the OR circuit 863 and the selectors 831 to 833 is used at the second stage. It has been.

<Operation>
In the above configuration, first, due to the operation of the AND circuits 741 to 744 of the first binary signal designating unit 740 that generates the F <> signal, the G <> signal is defective toward the MSB side sequentially from the LSB side. Bit search is performed, and 5 bits of 6-bit data are selected and supplied to the second-stage redundancy circuit 704c.

  Next, in the second-stage redundancy circuit 704c, the G <> signal is subjected to internal signal processing as an XG <> signal obtained by removing the bit determined to be defective in the first-stage redundancy circuit 704a. Further, by the operation of the AND circuits 841 to 843 of the second binary signal designating unit 840 that generates the XF signal, the XG <> signal is searched for defective bits sequentially from the LSB side to the MSB side, 4 bits of 5 bit data are selected and YDI <>, YBWC <>, XDO <> are selectively connected. In this way, the operation can be easily compensated for 2-bit defective data.

{Embodiment 24}
<Configuration>
Next, an example of a redundant circuit for a multi-port RAM such as a 3-port RAM will be described. FIG. 155 is a circuit diagram showing the connection between the redundancy circuit 704 and the 3-port RAM 703d with test circuit in the twenty-fourth embodiment of the present invention. As the 3-port RAM 703d with a test circuit, for example, the one shown in FIGS. 113 and 114 may be used.

  Here, signals of SO1 <0> to SO1 <5> (hereinafter abbreviated as SO1 <>) and SO2 <0> to SO2 <5> (hereinafter abbreviated as SO2 <>) are respectively represented by port 1 and port 1 2 is a serial output signal SO of each scan FF (for example, FIG. 69) which is a component of FIG. 95, for example.

  Here, the described 3-port RAM is assumed to be a RAM having the following functions.

  (1) When the WE terminal is active, the data of the DI <> terminal is written to the address specified by the A <> terminal only for the bit in which BWC <> is active.

  (2) Read the address specified by the terminals A1 <0> to A1 <3> (hereinafter abbreviated as A1 <>), and output to the DO1 <> terminal.

  (3) Read the address specified by the terminals A2 <0> to A2 <3> (hereinafter abbreviated as A2 <>), and output to the DO2 <> terminal.

  These operations (1) to (3) can be performed simultaneously. In the case of a RAM without a BWC <> terminal, a circuit related to this signal can be omitted. 706a in FIG. 155 performs AND operation on this failure information between the ports (SO1 <>, SO2 <>) when there are a plurality of read ports as in the case of a 3-port RAM, and generates AND information for the entire RAM. Circuit (logical product circuit).

  In FIG. 156, among the redundant circuits 704d, XDO1 <0> to XDO1 <4> (hereinafter abbreviated as XDO1 <>), DO1 <0> to DO1 <5> (hereinafter abbreviated as DO1 <>), XDO2 <0> to XDO2 <4> (hereinafter abbreviated as XDO2 <>) and DO2 <0> to DO2 <5> (hereinafter abbreviated as DO2 <>) is there. Note that the DI <> and BWC <>, XBC <>, and XDI <> terminals of the redundant circuit 704d in FIG. 155 may be the same as those in FIGS. 148 and 149, and thus are omitted in FIG.

  In FIG. 156, 871 to 875 are arranged in a signal line connecting between DO1 <> and XDO1 <>, and when a defective bit is given to any one of the signal lines, the signal line (“1”) And a selector that sequentially switches and connects to adjacent signal lines (“0” side) with the signal line as a boundary. Reference numerals 881 to 885 are arranged in a signal line connecting between DO2 <> and XDO2 <>. When a defective bit is given to any one of the signal lines, the corresponding signal line ("1" side) Is a selector for switching and connecting to adjacent signal lines ("0" side) sequentially with the signal line as a boundary.

  Reference numeral 890 controls switching of the selectors 871 to 875, 881 to 885, and is one-way side (LSB side) with a signal line designated as a defective bit among a plurality of signal lines as a boundary. ) Is a binary signal designating unit that outputs “1” to the selector of the signal line and outputs “0” to the signal line on the other direction side (MSB side).

  Specifically, the binary signal designating unit 890 is composed of four AND circuits (logical product circuits) 891 to 894. One input terminal of the first AND circuit 891 on the most LSB side is connected to the G <0> terminal of the register circuit 706, and the other input terminal is connected to the G <1> terminal of the register circuit 706. One input terminal of the second AND circuit 892 adjacent to the first AND circuit 891 is connected to the output terminal of the first AND circuit 891, and the other input terminal is G <2 of the register circuit 706. > Connected to the terminal. One input terminal of the third AND circuit 893 adjacent to the second AND circuit 892 is connected to the output terminal of the second AND circuit 892, and the other input terminal is G <3 of the register circuit 706. > Connected to the terminal. One input terminal of the fourth AND circuit 894 adjacent to the third AND circuit 893 is connected to the output terminal of the third AND circuit 893, and the other input terminal is G <4 of the register circuit 706. > Connected to the terminal.

  The output terminal of the first AND circuit 891 is connected to the switching control terminals of the selectors 872 and 882. The output terminal of the second AND circuit 892 is connected to the switching control terminal of the selectors 873 and 883. The output terminal of the third AND circuit 893 is connected to the switching control terminal of the selectors 874 and 884. The output terminal of the fourth AND circuit 894 is connected to the switching control terminal of the selectors 875 and 885. The switching control terminals of the selectors 871 and 881 are connected to the G <0> terminal of the register circuit 706.

<Operation>
In the above configuration, as shown in FIG. 156, the selectors 871 to 875 and 881 to 885 related to the output terminals DO1 <> and DO2 <> of the two read ports have the same control signal, that is, the G <0> signal from the register circuit 706. And it is controlled by F <1> to F <4> signals from the binary signal designating unit 890.

  In FIG. 155, it is assumed that the SO1 <> and SO2 <> signals, which are the test results of the respective ports, are set to “0” for the defective bit and “1” for the non-defective bit. In the present embodiment, since there are a plurality of read ports (3 ports), the AND circuit (logical product circuit) 706a performs AND operation on the defect information between the ports (SO1 <>, SO2 <>), and the entire RAM. Create defect information. For example, if it is assumed that SO1 <2> = “0” exists in port 1 and there is no failure in port 2, bit number 2 is defective in the entire RAM, and port 2 also includes redundancy circuit 704d. It is necessary to switch the selector. Bit number 2 because G <2> = “0” and G <0> = G <1> = G <3> = G <4> = G <5> = “1” by the operation of the AND circuit 706a. The selector is switched so as not to use. Conversely, even if there is a defect in port number 2, the same selector switching is performed.

  If a hierarchical structure such as the multi-bit redundant circuits 704a to 704c as shown in FIGS. 151 and 152, 153 and 154 is applied to the circuit of FIG. Defects can be remedied.

{Modification}
(1) FIG. 16 is a logic circuit diagram showing a first modification, FIG. 17 is a logic circuit diagram showing a second modification, FIG. 18 is a logic circuit diagram showing a third modification, and FIG. FIG. These modifications enable the data input signal (D) to pass through as necessary. In FIG. 16, FIG. 17, FIG. 18 and FIG. 19, Q is a data output terminal, 271 is It is a selector circuit. The selector circuit 271 includes a signal input terminal “0” to which a data input signal (D) from a RAM (not shown) is input, a signal input terminal “1” connected to the data output terminal O 1 of the flip-flop circuit 234, When the control signal (INSFF) is high, the flip-flop circuit 234 connected to the signal input terminal “1” has a control input terminal to which the control signal (INSFF) is input. Data from the data output terminal O1 is output to the data output terminal Q. In this case, it goes without saying that the same effects as those of the first to third embodiments can be obtained, while the control signal (INSFF) is low. In this case, the data input signal (D) inputted to the signal input terminal “0” is outputted as it is to the data output terminal Q. Note that the fourth example shown in FIG. In the example, 272 is a NOT circuit, and 273 is an OR circuit, which is provided to stop the shift operation of the flip-flop circuit 234 while the data input signal (D) is being passed through. When the signal (INSFF) is Low, the data input signal (D) is output to the data output terminal Q via the selector circuit 271. During this time, the output of the NOT circuit 272 is High, and therefore the output of the OR circuit 273 is It always becomes High and disables detection of the rising edge of the clock signal (T), so that the flip-flop circuit 234 can be surely prohibited from shifting and power consumption can be reduced.

  (2) FIG. 20 is a logic circuit diagram showing a fifth modification of the present invention, and FIG. 21 is a logic circuit diagram showing a sixth modification of the present invention. 253a and 253a in FIGS. 20 and 21 are selector circuits (selectors) that select and output a serial input signal (SI) and a data input signal (D) based on an external shift mode control signal (SM). Means) 254a and 264a are selector circuits (data holding means) that feed back the output data of the flip-flop circuit 234 and hold the data when a shift inhibition signal (SINH) is inputted from the outside. The fifth modification can provide the same effects as in the second embodiment, and the sixth modification can provide the same effects as in the third embodiment.

  (3) Embodiment 2 shown in FIG. 6, Embodiment 3 shown in FIG. 11, the second modification shown in FIG. 17, the third modification shown in FIG. 18, and the fourth modification shown in FIG. In the example, the data input signal (D) is input to the signal input terminals of the first selector circuits 252 and 262, and the serial input signal (SI) is input to the signal input terminal of the second selector circuit 253. A serial input signal (SI) may be input to the signal input terminals of the first selector circuits 252 and 262, and a data input signal (D) may be input to the signal input terminal of the second selector circuit 253. Even in this case, it is needless to say that the same effects as those of the above embodiments and modifications can be obtained.

  (4) In the fourth embodiment, the counter 43 is configured as shown in FIG. 26. For example, the counter 43 is configured as shown in FIG. 55 (seventh modified example) or FIG. 56 (eighth modified example). May be. 55 and 56, an OR circuit (adding element) that detects whether or not the address has just been incremented or decremented and adds 1 at this time, and a signal from the OR circuit and an address generation shift register An AND circuit to which the flip-flop α-1 of (ADDR) 35 is input, and an FF (memory that stores the address contents immediately before the address increment or decrement operation based on a signal from the AND circuit and inputs the address contents to the OR circuit. Element).

  (5) In the twelfth embodiment, the connection method when there is no Y address as shown in FIG. 70 is applied, but as shown in FIG. 93, four X addresses and one Y address are set. In this case, the configuration is such that the X address data or the Y address data can be selected by switching the selector 351 with the XY switching signal (EXXY) (Ninth Modification). May be. Further, when four X addresses and three Y addresses are set, the connection of the selector 351 may be as shown in FIG. 94 (tenth modification).

  (6) In the twelfth embodiment, the configuration as shown in FIG. 68 is adopted as the data output scan path 332 (DO-SCAN) so that the test data such as “0101” or “1010” can be easily handled. However, when the test data is limited to “0000” or “1111”, the configuration shown in FIG. 95 (the eleventh modification) may be used.

  Furthermore, when the test data is limited to “0000” or “1111”, the configuration shown in FIG. 96 (a twelfth modification) may be used. In this case, the expected data (EXP) signal and the comparison enable signal (CMPEN) are not directly input to each scan FF (“D”), but via the logic circuit unit 352 having a NOT circuit, a NAND circuit, and a NOR circuit. Test data is provided after conversion into conversion expected data (EXP0, EXP1C) signals.

  Furthermore, when the test data is “0101” or “1010” as in the twelfth embodiment, the configuration shown in FIG. 97 (the thirteenth modification) or the configuration shown in FIG. 98 (the fourteenth modification) ). In this case, the expected data (EXP) signal and the comparison enable signal (CMPEN) are converted into converted expected data (EXP0, EXP1C) signals via logic circuit units 353 and 354 having NOT circuits, NAND circuits, NOR circuits, and the like. Give test data. Then, like FIG. 68, test data such as “0101” or “1010” can be easily handled.

  (7) In the twelfth embodiment, the circuits of the first to third embodiments and the first to sixth modifications described above are applied as scan FFs. For example, a structure (fifteenth modification) as shown in FIG. 99 may be applied. The operation timing chart at the time of data acquisition in this case is as shown in FIG. 100, the timing chart showing the shift operation is as shown in FIG. 101, and the timing chart showing the shift prohibition operation is as shown in FIG.

  Alternatively, a structure as shown in FIG. 103 (sixteenth modification) may be used. The operation timing chart at the time of data acquisition in this case is as shown in FIG. 104, the timing chart showing the shift operation is as shown in FIG. 105, and the timing chart showing the shift prohibition operation is as shown in FIG.

  Further, when the control signal (SINH) can be omitted, a structure as shown in FIG. 107 (a seventeenth modified example) may be used. The operation timing chart at the time of data acquisition in this case is as shown in FIG. 108, and the timing chart showing the shift operation is as shown in FIG.

  Furthermore, when the control signal (SINH) can be omitted, a structure as shown in FIG. 110 (an eighteenth modification) may be used. In this case, the operation timing chart at the time of data acquisition is as shown in FIG. 111, and the timing chart showing the shift operation is as shown in FIG.

  (8) Circuits shown in FIGS. 113 and 114 in place of the circuits of FIGS. 64 and 65 in the twelfth embodiment, FIGS. 87 and 88 in the fourteenth embodiment, and FIGS. 91 and 92 in the fifteenth embodiment (FIG. The nineteenth modification) may be applied. 113 and 114 are broken along the line EE. Here, the fifteenth embodiment shown in FIGS. 91 and 92 is a 1-write 1-read 2-port RAM, whereas the 19th modification shown in FIGS. 113 and 114 is a 1-write 2-read 3-port RAM. is there. A0 <MSB: 0> is a multiplexer-type write address, and A1 <MSB: 0> and A2 <MSB: 0> are multiplexer-type read addresses. FIG. 115 is a timing chart showing the state of the write port of the RAM core 331 of the semiconductor memory inspection device of the nineteenth modification, and FIG. 116 is a timing chart showing the state of the read port of the RAM core 331 as well. 117 shows a timing chart showing the state of the write port of the entire 3-port RAM, and FIG. 118 shows a timing chart showing the state of the read port of the entire 3-port RAM. Note that T0, T1, and T2 in FIGS. 113 and 114 are clock signals, and these can set different frequencies.

  (9) Instead of the circuit of the nineteenth modification shown in FIGS. 113 and 114, the circuit shown in FIGS. 119 and 120 (the twentieth modification) may be applied. 119 and 120 are broken at the line FF. The circuit of the twentieth modification is one in which two ports are used for both writing (Write) and reading (Read) (2-port RAM).

  (10) Although the structure shown in FIG. 123 is applied as the B-SCAN in the sixteenth embodiment, it is shown in FIG. 124 (21st modification) and FIG. 125 (22nd modification). Any one of them may be used. 124, when four X addresses and one Y address are set, instead of the circuit shown in FIG. 123, the data of the X address is set to the head or the data of the Y address. Can be selected by switching the selector 351 with an XY switching signal (EXXY), which is similar to the ninth modification (FIG. 93). The circuit shown in FIG. 125 is used in place of the circuits shown in FIGS. 123 and 124 when four X addresses and three Y addresses are set. The configuration is similar to the example (FIG. 94).

  However, unlike the circuits shown in FIGS. 93 and 94, the circuits shown in FIGS. 124 to 125 have the test address terminals TA (TA0, TA1, TA2,...) Side when the CHDIR signal is set to “1”. Selected. As shown in FIG. 121, the test address terminal TA is provided as a RAMK pin. Therefore, the address can be set and tested in an arbitrary order. That is, B-SCAN can set an address by a serial shift operation when the CHDIR signal is “0”. When the CHDIR signal is “1”, addresses can be set in parallel by the test address terminal TA. An address signal for the test address terminal TA may be supplied from an external pin of the LSI, or may be supplied from a test address generation circuit (corresponding to 301 in FIG. 60) mounted in the LSI. As the test address generation circuit, an algorithmic pattern generator as provided in a memory LSI test apparatus may be used.

  (11) The circuit shown in FIGS. 126 and 127 is a modification (a twenty-third modification) of the fifteenth embodiment (2-write RAM of 1 Write 1 Read) shown in FIGS. 91 and 92. 126 and 127 are broken along the line HH. In the twenty-third modification, the test address terminals TA of B-SCAN-0 and B-SCAN-1 are connected in common and are provided as RAM pins. When it is necessary to perform a test that gives different addresses, two independent test address terminals TA for B-SCAN-0 and B-SCAN-1 may be provided as RAM pins.

  (12) The circuits shown in FIGS. 128 and 129 are further modified examples (24th modified example) of the circuit of the 19th modified example shown in FIGS. 113 and 114. 128 and 129 are cut away along the line II. In the twenty-fourth modification, B-SCAN is used instead of the address input scan path 332 (A-SCAN) in the nineteenth modification (FIGS. 113 and 114). 128 and 129, the test address terminals TA of B-SCAN-0, B-SCAN-1 and B-SCAN-2 are connected in common and provided as RAM pins. In the case of performing a test that gives different addresses, an independent test address terminal TA may be provided as a RAM pin.

  (13) The circuits shown in FIGS. 130 and 131 are further modified examples (25th modified example) of the twentieth modified example shown in FIGS. 119 and 120. 130 and 131 are broken along the line JJ. In the twenty-fifth modification, B-SCAN is used instead of the address input scan path 332 (A-SCAN) in the twentieth modification (FIGS. 119 and 120). 130 and 131, the test address terminals TA of B-SCAN-0 and B-SCAN-1 are connected in common and provided as RAM pins. When it is necessary to perform a test that gives different addresses, two independent test address terminals TA for B-SCAN-0 and B-SCAN-1 may be provided as pins for RAM.

  (14) The self-test circuit 702 described in the nineteenth and twentieth embodiments is not limited to FIGS. 143 and 147. For example, the self test circuit 702 may be configured by a normal random logic circuit.

  (15) In each of the above embodiments, the test result from the RAM 703 with a test circuit changes during the normal operation of the system. Therefore, the register circuit 706 is changed as shown in FIGS. 142, 144, 150, and 155. When the test result from the RAM 703 with the test circuit does not change during the normal operation of the system (for example, FIG. 1, or FIG. 6, FIG. 11, FIG. 17, FIG. 18, 19, 20, and 21, the register circuit 706 may be omitted in the case where a plurality of flip-flops provided with a loop wiring for data feedback are provided.

  (16) Although the circuit of the twenty-third embodiment shown in FIGS. 153 and 154 constitutes a two-stage hierarchical redundancy circuit, multi-bit defect relief can be performed by increasing the number of such layers. For example, in order to perform 3-bit relief, a circuit in which a portion surrounded by a broken line is reduced by 1 bit may be added. In FIG. 153 and FIG. 154, the search for defective bits is limited to the LSB (minimum digit bit) side. However, any search order may be used (MSB (maximum digit bit) side or random). Order).

  (17) In each of the above embodiments, the defective bit is detected from the lower bit side of the binary signal specifying unit 740, but the defective bit may be detected from the upper bit side. In this case, the second binary signal designating unit 800 of the twenty-second embodiment detects a defective bit from the lower bit side, and the second binary signal designating unit 840 of the twenty-third embodiment is defective from the upper bit side. Even if a bit is detected, a defective bit may be detected from the lower bit side.

1 is a logic circuit diagram showing a semiconductor memory inspection device according to a first embodiment of the present invention. 6 is a timing chart showing an operation at the time of data fetching of the flip-flop circuit of the semiconductor memory inspection device according to the first embodiment of the present invention; 6 is a timing chart showing a shift operation of the flip-flop circuit of the semiconductor memory inspection device according to the first embodiment of the present invention; 6 is a timing chart showing a shift prohibiting operation of the flip-flop circuit of the semiconductor memory inspection device according to the first embodiment of the present invention; 6 is a timing chart showing a comparison operation of the comparison circuit of the semiconductor memory inspection device according to the first embodiment of the present invention; It is a logic circuit diagram which shows the test | inspection apparatus of the semiconductor memory of Embodiment 2 of this invention. It is a timing chart which shows the operation | movement at the time of the data capture of the flip-flop circuit of the inspection apparatus of the semiconductor memory of Embodiment 2 of this invention. It is a timing chart which shows the shift operation | movement of the flip-flop circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 2 of this invention. It is a timing chart which shows the shift prohibition operation | movement of the flip-flop circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 2 of this invention. It is a timing chart which shows the comparison operation | movement of the comparison circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 2 of this invention. It is a logic circuit diagram which shows the test | inspection apparatus of the semiconductor memory of Embodiment 3 of this invention. It is a timing chart which shows the operation | movement at the time of the data capture of the flip-flop circuit of the inspection apparatus of the semiconductor memory of Embodiment 3 of this invention. It is a timing chart which shows the shift operation | movement of the flip-flop circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 3 of this invention. It is a timing chart which shows the shift prohibition operation | movement of the flip-flop circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 3 of this invention. It is a timing chart which shows the comparison operation | movement of the comparison circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 3 of this invention. It is a logic circuit diagram which shows the 1st modification of this invention. It is a logic circuit diagram which shows the 2nd modification of this invention. It is a logic circuit diagram which shows the 3rd modification of this invention. It is a logic circuit diagram which shows the 4th modification of this invention. It is a logic circuit diagram which shows the 5th modification of this invention. It is a logic circuit diagram which shows the 6th modification of this invention. It is a circuit diagram which shows the scan register of the test | inspection apparatus of the semiconductor memory of the 1st prior art example. It is a block diagram which shows the scan register comprised by the scan register of the 1st prior art example shown in FIG. It is a block diagram which shows the state which connected the several semiconductor memory to the test | inspection apparatus of Embodiment 4 of this invention. It is a circuit block diagram which shows the test | inspection apparatus of the semiconductor memory of Embodiment 4 of this invention. It is a circuit block diagram which shows the logic structure etc. of the arithmetic logic operation part in the test | inspection apparatus of the semiconductor memory of Embodiment 4 of this invention. It is a circuit diagram which shows the internal structure of the half adder of the test | inspection apparatus of the semiconductor memory of Embodiment 4 of this invention. It is a circuit block diagram which shows the generation | occurrence | production operation | movement of a quaternary test pattern in the semiconductor memory test | inspection apparatus of Embodiment 4 of this invention. It is a circuit block diagram which shows the equivalent circuit at the time of quaternary test pattern generation | occurrence | production in the inspection apparatus of the semiconductor memory of Embodiment 4 of this invention. It is a circuit block diagram which shows the count operation | movement in the semiconductor memory test | inspection apparatus of Embodiment 4 of this invention. It is a circuit block diagram which shows the equivalent circuit at the time of the count in the semiconductor memory test | inspection apparatus of Embodiment 4 of this invention. It is a circuit block diagram which shows the test | inspection apparatus of the semiconductor memory of Embodiment 5 of this invention. It is a circuit block diagram which shows the logic structure of the arithmetic logic operation part in the test | inspection apparatus of the semiconductor memory of Embodiment 5 of this invention. It is a circuit block diagram at the time of operation | movement of the test | inspection apparatus of the semiconductor memory of Embodiment 5 of this invention. It is a circuit block diagram which shows the test | inspection apparatus of the semiconductor memory of Embodiment 6 of this invention. It is a circuit block diagram which shows the equivalent circuit at the time of operation | movement of the test | inspection apparatus of the semiconductor memory of Embodiment 6 of this invention. It is a circuit block diagram which shows the test | inspection apparatus of the semiconductor memory of Embodiment 7 of this invention. It is a circuit block diagram which shows the state at the time of operation | movement of the test | inspection apparatus of the semiconductor memory of Embodiment 7 of this invention. It is a figure which shows the checkerboard pattern at the time of the function test of the semiconductor memory of Embodiment 8 of this invention. It is a figure which shows the two-dimensional pattern memory | storage part in which the checkerboard pattern of the semiconductor memory test | inspection apparatus of Embodiment 8 of this invention was memorize | stored. It is a figure which shows the equivalent circuit at the time of the checkerboard pattern production | generation of the test | inspection apparatus of the semiconductor memory of Embodiment 8 of this invention. It is a figure which shows the column bar pattern at the time of the function test of the semiconductor memory of Embodiment 8 of this invention. It is a figure which shows the two-dimensional pattern memory | storage part by which the column bar pattern of the semiconductor memory test | inspection apparatus of Embodiment 8 of this invention was memorize | stored. It is a figure which shows the equivalent circuit at the time of the column bar pattern production | generation of the semiconductor memory test | inspection apparatus of Embodiment 8 of this invention. It is a figure which shows the rover pattern at the time of the function test of the semiconductor memory of Embodiment 8 of this invention. It is a figure which shows the two-dimensional pattern memory | storage part by which the rover pattern of the inspection apparatus of the semiconductor memory of Embodiment 8 of this invention was memorize | stored. It is a figure which shows the equivalent circuit at the time of the rover pattern production | generation of the semiconductor memory test | inspection apparatus of Embodiment 8 of this invention. It is a circuit block diagram which shows the test | inspection apparatus of the semiconductor memory of Embodiment 9 of this invention. It is a block diagram which shows the state which connected the some semiconductor memory to the test | inspection apparatus of Embodiment 9 of this invention. It is a circuit block diagram which shows the test | inspection apparatus of the semiconductor memory of Embodiment 10 of this invention. It is a figure which shows the setting of each input terminal in the test | inspection apparatus of the semiconductor memory of Embodiment 10 of this invention. It is a circuit block diagram which shows the logic structure etc. of the pattern generation circuit for dynamic burn-ins of the test | inspection apparatus of the semiconductor memory of Embodiment 10 of this invention. It is a circuit block diagram which shows the connection state of the semiconductor memory of Embodiment 10 of this invention, and a test | inspection apparatus. It is a circuit block diagram which shows the logic structure of the test | inspection apparatus of the semiconductor memory of Embodiment 11 of this invention. It is a circuit diagram which shows the internal structure of the half adder of the test | inspection apparatus of the semiconductor memory of the 7th modification of this invention. It is a circuit diagram which shows the internal structure of the half adder of the test | inspection apparatus of the semiconductor memory of the 8th modification of this invention. It is a circuit block diagram which shows the test | inspection apparatus of the semiconductor memory of the 2nd prior art example. It is a circuit block diagram which shows a part of test | inspection apparatus of the semiconductor memory of the 2nd prior art example. It is a block diagram which shows the state which connected the several semiconductor memory to the test | inspection apparatus of the semiconductor memory of the 3rd prior art example. It is a block diagram which shows the test | inspection apparatus of the semiconductor memory of a proposal example. It is a figure which shows operation | movement of the test | inspection apparatus of the semiconductor memory of a proposal example. It is a figure which shows the connection state of RAM of the test | inspection apparatus of the semiconductor memory of Embodiment 12 of this invention. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 12 of this invention. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 12 of this invention. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 12 of this invention. It is a block diagram which shows the scan path for data inputs of the test | inspection apparatus of the semiconductor memory of Embodiment 12 of this invention. It is a block diagram which shows the internal circuit of the scan path for address input and the scan path for data input of Embodiment 12 of this invention. It is a block diagram which shows the scan path for data output of the inspection apparatus of the semiconductor memory of Embodiment 12 of this invention. It is a block diagram which shows the internal circuit of the scan path for data output of Embodiment 12 of this invention. It is a figure which shows the state which connected several RAM about the inspection apparatus of the semiconductor memory of Embodiment 12 of this invention. It is a figure which shows a general write pulse generator. It is a timing chart which shows operation | movement of a write pulse generator. It is a figure which shows the state of the BIST signal and SI signal in the inspection apparatus of the semiconductor memory of Embodiment 12 of this invention. It is a flowchart which shows the scan test operation | movement of Embodiment 12 of this invention. It is a flowchart which shows RAM test operation | movement of Embodiment 12 of this invention. It is a figure which shows operation | movement of the test | inspection apparatus of the semiconductor memory of Embodiment 12 of this invention. It is a timing chart which shows the state of each terminal of the single port RAM of Embodiment 12 of this invention. It is a timing chart which shows the state of the RAM core of Embodiment 12 of this invention. It is a figure which shows the state of SINH1 signal in the test | inspection apparatus of the semiconductor memory of Embodiment 12 of this invention. It is a figure which shows the example of input of the SI signal in the test | inspection apparatus of the semiconductor memory of Embodiment 12 of this invention. It is a figure which shows the state of the SINH-FF signal with respect to SI signal, the RUNBIST signal, the SINH0 signal, and the SINH1 signal in the inspection apparatus of the semiconductor memory of Embodiment 12 of this invention. It is a block diagram which shows the test | inspection apparatus of the semiconductor memory of Embodiment 13 of this invention. It is a figure which shows the state of the BIST signal and SI signal in the inspection apparatus of the semiconductor memory of Embodiment 13 of this invention. It is a figure which shows the example of input of the SI signal in the test | inspection apparatus of the semiconductor memory of Embodiment 13 of this invention. It is a figure which shows the state of the SINH-FF signal with respect to SI signal, the RUNBIST signal, the SINH0 signal, and the SINH1 signal in the semiconductor memory test | inspection apparatus of Embodiment 13 of this invention. It is a figure which shows the state of SINH1 signal in the test | inspection apparatus of the semiconductor memory of Embodiment 13 of this invention. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 14 of this invention. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 14 of this invention. It is a figure which shows the test | inspection apparatus of the semiconductor memory of Embodiment 14 of this invention. It is a figure which shows the test | inspection apparatus of the semiconductor memory of Embodiment 14 of this invention. It is a block diagram which shows the RAM core and test circuit of the semiconductor memory test | inspection apparatus of Embodiment 15 of this invention. It is a block diagram which shows the RAM core and test circuit of the semiconductor memory test | inspection apparatus of Embodiment 15 of this invention. It is a block diagram which shows the state with which the several address was connected in the test | inspection apparatus of the semiconductor memory of a 9th modification. It is a block diagram which shows the state with which the several address was connected in the test | inspection apparatus of the semiconductor memory of a 10th modification. It is a block diagram which shows the scan path for data output of the test | inspection apparatus of the semiconductor memory of an 11th modification. It is a block diagram which shows the scan path for data output of the test | inspection apparatus of the semiconductor memory of a 12th modification. It is a block diagram which shows the scan path for data output of the test | inspection apparatus of the semiconductor memory of a 13th modification. It is a block diagram which shows the scan path for data output of the test | inspection apparatus of the semiconductor memory of a 14th modification. It is a figure which shows scan FF of the 15th modification. It is a timing chart which shows the operation | movement at the time of the data capture of the scan FF of a 15th modification. It is a timing chart which shows the shift operation | movement of the scan FF of a 15th modification. It is a timing chart which shows the shift prohibition operation | movement of the scan FF of a 15th modification. It is a figure which shows scan FF of the 16th modification. It is a timing chart which shows the operation | movement at the time of the data capture of the scan FF of a 16th modification. It is a timing chart which shows the shift operation of scan FF of the 16th modification. It is a timing chart which shows the shift prohibition operation | movement of the scan FF of a 16th modification. It is a figure which shows scan FF of the 17th modification. It is a timing chart which shows the operation | movement at the time of the data capture of the scan FF of a 17th modification. It is a timing chart which shows the shift operation | movement of the scan FF of a 17th modification. It is a figure which shows scan FF of the 18th modification. It is a timing chart which shows the operation | movement at the time of the data capture of the scan FF of the 18th modification. It is a timing chart which shows the shift operation of scan FF of the 18th modification. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of a 19th modification. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of a 19th modification. It is a timing chart which shows the state of the port for writing of the inspection apparatus of the semiconductor memory of a 19th modification. It is a timing chart which shows the state of the read-out port of the test | inspection apparatus of the semiconductor memory of a 19th modification. It is a timing chart which shows the state of the port for writing of the inspection apparatus of the semiconductor memory of a 19th modification. It is a timing chart which shows the state of the read-out port of the test | inspection apparatus of the semiconductor memory of a 19th modification. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of a 20th modification. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of a 20th modification. FIG. 38 is a block diagram showing a RAM core and a test circuit of a semiconductor memory inspection device according to a sixteenth embodiment. FIG. 38 is a block diagram showing a RAM core and a test circuit of a semiconductor memory inspection device according to a sixteenth embodiment. FIG. 38 is a block diagram showing a B-SCAN configuration of a semiconductor memory inspection device according to a sixteenth embodiment; It is a block diagram which shows the structure of B-SCAN of the test | inspection apparatus of the semiconductor memory of a 21st modification. It is a block diagram which shows the structure of B-SCAN of the test | inspection apparatus of the semiconductor memory of a 22nd modification. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of a 23rd modification. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of a 23rd modification. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of a 24th modification. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of a 24th modification. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of a 25th modification. It is a block diagram which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of a 25th modification. It is a figure which shows the connection state of RAM of the test | inspection apparatus of the semiconductor memory of the 4th prior art example. It is a figure which shows the control signal generation circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 17 of this invention. It is a figure which shows the cyclic shift register of the test | inspection apparatus of the semiconductor memory of Embodiment 17 of this invention. It is a figure which shows the RAM core of the test | inspection apparatus of the semiconductor memory of Embodiment 17 of this invention, a test circuit, and a control signal generation circuit. It is a figure which shows the RAM core of the test | inspection apparatus of the semiconductor memory of Embodiment 17 of this invention, a test circuit, and a control signal generation circuit. It is a figure which shows the RAM core of the test | inspection apparatus of the semiconductor memory of Embodiment 18 of this invention, a test circuit, and a test pattern generation circuit. It is a figure which shows the test pattern generation circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 18 of this invention. It is a figure which shows the test pattern generation circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 18 of this invention. It is a figure which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 18 of this invention. It is a figure which shows the RAM core and test circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 18 of this invention. It is a block diagram of the test | inspection apparatus of the semiconductor memory with a self-correction function in Embodiment 19 of this invention. It is a figure which shows the structural example of the self-test circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 19 of this invention. It is a figure which shows the detailed connection example of RAM with a test circuit, and a redundant circuit in the test | inspection apparatus of the semiconductor memory of Embodiment 19 of this invention. It is a figure which shows the redundancy circuit which can relieve 1 bit in the inspection apparatus of the semiconductor memory of Embodiment 19 of this invention. It is a figure which shows the redundancy circuit which can relieve 1 bit in the inspection apparatus of the semiconductor memory of Embodiment 19 of this invention. It is a figure which shows the structural example of the self-test circuit of the test | inspection apparatus of the semiconductor memory of Embodiment 20 of this invention. It is a figure which shows the redundancy circuit which can be relieved by 1 bit in the semiconductor memory test | inspection apparatus of Embodiment 21 of this invention. It is a figure which shows the redundancy circuit which can be relieved by 1 bit in the semiconductor memory test | inspection apparatus of Embodiment 21 of this invention. It is a figure which shows the detailed connection example of RAM with a test circuit, and a redundant circuit in the test | inspection apparatus of the semiconductor memory of Embodiment 22 of this invention. FIG. 38 is a circuit diagram of a 2-bit redundant circuit in a semiconductor memory inspection device according to a twenty-second embodiment of the present invention. FIG. 38 is a circuit diagram of a 2-bit redundant circuit in a semiconductor memory inspection device according to a twenty-second embodiment of the present invention. FIG. 38 is a circuit diagram of a 2-bit redundant circuit in a semiconductor memory inspection device according to a twenty-third embodiment of the present invention. FIG. 38 is a circuit diagram of a 2-bit redundant circuit in a semiconductor memory inspection device according to a twenty-third embodiment of the present invention. It is a figure which shows the detailed example of connection of RAM with a test circuit, and a redundant circuit in the test | inspection apparatus of the semiconductor memory of Embodiment 24 of this invention. It is a figure which shows a part of redundant circuit in the test | inspection apparatus of the semiconductor memory of Embodiment 24 of this invention. It is a figure which shows the test | inspection apparatus of the semiconductor memory of the 5th prior art example. It is a figure which shows the test | inspection apparatus of the semiconductor memory of the 5th prior art example.

Explanation of symbols

231 scan register, 232 comparison circuit, 233 selector circuit, 234 flip-flop circuit, 235 OR circuit, 241 Ex. OR circuit, 242 NOT circuit, 243 NAND circuit, 251 scan register, 252 first selector circuit, 253 second selector circuit, 254 loop circuit, 261 scan register, 262 first selector circuit, 263 second selector circuit 264 feedback inhibition element, 232a comparison circuit, 241a Ex. OR circuit, 243a NAND circuit, 252a, 253a selector circuit, 262a, 263a selector circuit, 30 inspection device, 31 semiconductor memory, 31a-31c semiconductor memory, 32 address input shift register, 32a-32c address input shift register, 33 Data input register, 34 comparison circuit, 34a to 34c comparison circuit, 34Z comparison prohibition unit, 35 address generation unit, 37 effective address number storage unit, 38 first AND circuit group, 39 second AND circuit group, 41 expectation Value generation circuit, 42 OR circuit group, 43 counter, 44 OR circuit, 51-60 logical product circuit, 61-64 exclusive OR circuit, 65-68 logical sum circuit, 71 logical sum circuit, 72 logical product circuit, 73 Half adder, 74 switch, 81 OR circuit group, 82 second AND circuit group, 4 comparison circuit, 84a, 84b comparison circuit, 91-94 logical sum circuit, 95-99 logical product circuit, 101 logical product circuit group, 111 two-dimensional pattern storage unit, 113 expected value generation circuit, 115 logical sum circuit, 121 dynamic Burn-in pattern generation circuit, 121x dynamic burn-in pattern generation circuit, 122 LFSR circuit, 127 shift register, 130 OR circuit, 140 data input shift register, 141 to 143 FF, 301 test pattern generation circuit, 302 test circuit, 303 RAM core, 312, 313 shift register, 315 RAM, 316 scan campus, 317 flip-flop, 319 pipeline, 321, 322 flip-flop, 323 selector, 324 AND circuit, 325 NOT circuit, 326 OR times 327 NOR circuit, 331 RAM core, 331 asynchronous RAM core, 332 scan path, 332a register, 332b first selector, 332c second selector, 332d OR circuit, 332e NAND circuit, 332f AND circuit, 333 write pulse generator 334 selector, 335 NOT circuit, 336 bit write inhibit signal input AND circuit, 337 selector, 341 selector, 344 AND circuit, 345 mark detection means, 346 shift register, 347 NAND circuit, 351 selector, 352 logic circuit unit, 353 354, logic circuit section, 600 cyclic shift register, 601 shift-in selector, 603 first register section, 604 second register section, 606a first flip-flop, 606b second flip-flop 607a first selector, 607b second selector, 610 control signal generation circuit, 611 test circuit, 613 test pattern generation circuit, 614 address pattern generation circuit, 615 RAM core, 615 memory core, 621 control signal generation circuit , 622 Address generation circuit, 623 Burn-in pattern generation circuit, 624 Data input circuit, 625 Test pattern generation circuit, 631 Test circuit, 632 RAM core, 701 Power-on reset circuit, 702 Self-test circuit, 702a Microcomputer, 703 RAM, 704 Redundant circuit, 704a Redundant circuit, 704b Redundant circuit, 704c Redundant circuit, 704d Redundant circuit, 705 Logic circuit, 706 Register circuit, 706a AND circuit, 711-715 selector, 721-725 selector Kuta, 731 to 735 selector, 740 signal designation unit, 741 to 745 AND circuit, 750 control element group, 751 inverter circuit, 752 OR circuit, 771 to 773 selector, 774 OR circuit, 781 to 783 selector, 784 OR circuit, 791 794 selector, 800 signal designation unit, 801-803 AND circuit, 811-813 selector, 821-823 selector, 831-833 selector, 840 signal designation unit, 841-843 AND circuit, 861, 862 OR circuit, 863 OR circuit , 871 to 875 selector, 881 to 885 selector, 890 signal designation unit, 891 to 894 AND circuit.

Claims (5)

A test circuit having a data holding means for performing a test of the semiconductor memory and holding a test result of a plurality of digits of the semiconductor memory;
A redundant circuit that compensates for an error that occurs in data when a failure occurs in the semiconductor memory based on a result of the test in the test circuit;
The redundant circuit is:
A plurality of signal lines connected corresponding to each of a plurality of digits of data of the semiconductor memory;
A spare line adjacent to the signal line;
Among the plurality of signal lines, a signal line on one side with respect to a signal line corresponding to a digit designated as a defective bit according to a test result held by the data holding unit of the test circuit A binary signal designating unit that outputs one of the two values and outputs the other of the two values for the signal line on the other direction side;
Based on the binary signal from the binary signal designating unit, disconnect the signal line corresponding to the digit designated to be a defective bit, switch the signal line at the end to the spare line, and connect other signals. And a selector group for sequentially switching and connecting the signal line to a signal line adjacent to the other signal line.   2. The semiconductor memory inspection apparatus according to claim 1, wherein the data holding means scans and outputs the test result. The redundant circuit has a bit write control signal output terminal for outputting a signal for controlling writing for each data bit to the semiconductor memory,
2. The semiconductor memory according to claim 1, wherein writing of a digit designated as a defective bit is suppressed according to a signal given from the bit write control signal output terminal of the redundancy circuit. Inspection device for semiconductor memory. The data holding means holds one value of the binary values corresponding to the digits of the defective data and holds the other value of the binary values corresponding to the other digits. It is a binary data holding means that specifies the digit of defective data related to a failure in the memory,
The binary signal designating unit has a plurality of AND circuits corresponding to a plurality of digits of data in the semiconductor memory,
One input terminal of the plurality of AND circuits is connected to corresponding digits of the binary data holding unit, respectively.
2. The semiconductor memory according to claim 1, wherein another input terminal of the plurality of AND circuits is sequentially connected to an output terminal of the AND circuit adjacent to one of the large digit side and the small digit side of the AND circuit. Inspection device. 4. The semiconductor memory inspection apparatus according to claim 3, wherein the redundancy circuit inactivates a bit write control signal output terminal of a digit corresponding to a defective bit.

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