JP2005222659A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a word driver which can drive a word line at high speed without increasing layout area. <P>SOLUTION: A level shifter 51 selected by a plurality of signals driven by respective memory main power source voltage VDD (=1.5V) and performing level shift operation is provided at a word driver 801, high level voltage of a gate signal supplied to a PMOS transistor 808 and an NMOS transistor 809 constituting an output stage inverter 52 of this word driver 801 is set to power source voltage VINT(=2.0V) for operating the output stage inverter 52, that is, voltage VPP (=3.3V) being higher than high level voltage of the word line. The high level voltage VINT of the word line is made higher voltage than memory main power source voltage VDD being high level voltage of the bit line by approximately 0.5V so that an off-leak current of a memory cell having a PMOS memory cell transistor is minimized. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, and more particularly to improvement of a word driver for driving a word line.

  A DRAM (Dynamic Random Access Memory) memory cell generally includes a memory cell transistor and a memory cell capacitor. The memory cell transistor is composed of a PMOS transistor, for example, and its gate is connected to the word line. The memory cell capacitor is connected to the bit line via the memory cell transistor. When attention is paid to a plurality of memory cells constituting one row (row), the gates of the respective memory cell transistors are connected to a common word line. A word driver drives the word line. When selected by the output of the row decoder, the word driver supplies a low level voltage signal to the corresponding word line. As a result, all the PMOS memory cell transistors belonging to the row are activated, and the read operation or write operation of the row is started.

As one of conventional semiconductor memory devices, a DRAM having a word driver having a level shifter having an address decoding function and an output stage inverter having a CMOS structure is known. The output stage inverter is composed of, for example, a PMOS transistor and an NMOS transistor, and the drains of both MOS transistors are commonly connected to a word line, and the gates of both MOS transistors are connected to each other so as to receive a common gate signal. Configured. When the level shifter is selected by a plurality of input signals driven by a certain power supply voltage, the level shifter operates at another power supply voltage higher than the power supply voltage (hereinafter referred to as a high power supply voltage), and changes to the high power supply voltage. A gate signal having a set high level voltage is supplied to the output stage inverter. In the output stage inverter, the source of the PMOS transistor is connected to the high power supply voltage, the source of the NMOS transistor is connected to the ground voltage, and the output stage inverter that receives the gate signal having the high level voltage from the level shifter receives the corresponding word line. The voltage is activated to a low level voltage (= ground voltage). On the other hand, the output stage inverter of the word driver assigned to the unselected row receives the gate signal having the low level voltage set to the ground voltage from the level shifter, and converts the corresponding word line voltage to the high level voltage (= high power supply voltage). (See Patent Document 1).
JP 2003-100076 A

  In recent years, DRAMs formed on the same semiconductor substrate together with analog circuits and other logic circuits have not only high integration for realizing SOC (System On Chip) at low cost, but also large capacity SRAMs (Static Random). There is a demand for high-speed access performance that can be used as an alternative to (Access Memory).

  In order to speed up DRAM access, high-speed operation of the word driver is indispensable. However, in the conventional DRAM, since the level shifter in the word driver and the output stage inverter operate with the same power supply voltage (= high power supply voltage), the capacity of the MOS transistor in the output stage inverter will be increased. Then, the size of the MOS transistor has to be increased. This requires the number of word drivers corresponding to the number of word lines having a large number, leading to an increase in the DRAM layout area.

  An object of the present invention is to provide a semiconductor memory device including a word driver capable of driving a word line at a high speed without increasing a layout area.

  To achieve the above object, according to the present invention, a high level voltage of a gate signal supplied to a PMOS transistor and an NMOS transistor constituting an output stage inverter of a word driver is used as a power supply voltage for operating the output stage inverter, that is, a word line. The voltage is set higher than the high level voltage.

  For example, the word driver includes a level shifter that receives a plurality of input signals in addition to the output stage inverter. The level shifter is driven by a first power supply voltage at least one of a plurality of input signals, operates at a second power supply voltage higher than the first power supply voltage, and is a high level of a gate signal supplied to the output stage inverter The voltage is set to the second power supply voltage. The output stage inverter operates at a third power supply voltage lower than the second power supply voltage, and sets a high level voltage of a signal supplied to the corresponding word line of the plurality of word lines to the third power supply voltage. To do.

  Alternatively, a row predecoder having a level shifter for boosting the high level voltage of each of the plurality of row predecode signals to be output from the first power supply voltage to a second power supply voltage higher than the first power supply voltage. And a row decoder for generating a plurality of row decode signals having the second power supply voltage as a high level voltage from the plurality of boosted row predecode signals. Each word driver has an input stage inverter that receives a corresponding row decode signal among a plurality of row decode signals in addition to the output stage inverter. The input stage inverter sets the high level voltage of the gate signal supplied to the output stage inverter to the second power supply voltage. The output stage inverter operates at a third power supply voltage lower than the second power supply voltage, and sets a high level voltage of a signal supplied to the corresponding word line of the plurality of word lines to the third power supply voltage. To do.

  According to the present invention, the high-speed operation of the output stage inverter can be achieved without increasing the layout area by making the high level voltage of the gate signal applied to the output stage inverter of the word driver higher than the conventional one.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a system LSI chip on which a DRAM according to the present invention is mounted. A system LSI chip 100 shown in FIG. 1 includes a DRAM 101, a logic circuit 102, and an analog circuit 103 formed on the same semiconductor substrate. A large number of pads 104 are formed on the periphery of the chip. The logic circuit 102 receives supply of the first power supply voltage VDD (for example, 1.5 V), and the analog circuit 103 receives supply of the second power supply voltage VPP (for example, 3.3 V) from the outside of the chip. The DRAM 101 receives supply of the first power supply voltage VDD and the second power supply voltage VPP from the outside of the chip. Further, the DRAM 101 receives supply of a row address strobe signal / RAS, a row address signal Xad, a column address signal Yad, and the like from the logic circuit 102. Each of the row address signal Xad and the column address signal Yad is, for example, an 8-bit signal. The second power supply voltage VPP is the highest power supply voltage among the plurality of power supply voltages supplied from the outside to the system LSI chip 100.

  In general, in order to realize high-speed circuit operation at a low voltage, it is necessary to thin the gate oxide film of a MOS transistor and increase its saturation current. However, applying a high gate voltage to a thin gate oxide film is not reliable. It becomes a problem. Therefore, for example, in the system LSI chip 100 of FIG. 1 belonging to the 0.15 μm process generation, the logic circuit 102 operating with the first power supply voltage VDD (= 1.5 V) is formed by a thin gate oxide MOS transistor, The analog circuit 103 operating at a second power supply voltage VPP (= 3.3 V) higher than this is formed by a thick gate oxide MOS transistor. These MOS transistors with different gate oxide thicknesses are optimal in saturation current, threshold voltage, minimum gate length, element isolation length, etc., assuming that each voltage (VDD or VPP) is applied to the gate. It becomes.

  FIG. 2 shows a schematic configuration of the DRAM 101 in FIG. The memory array 201 included in the DRAM 101 in FIG. 2 includes a plurality of word lines 202, a plurality of bit lines 203, and a plurality of memory cells 204 respectively disposed at intersections thereof. Corresponding to the 8-bit row address signal Xad, the number of word lines 202 is 256. Two adjacent bit lines 203 operate in a complementary manner as a pair of bit lines BL and / BL. The DRAM 101 in FIG. 2 further includes an address latch circuit 205, a row predecoder 206, a row decoder 207, a word driver block 208, and a sense amplifier block 210. The configuration of the column decoder that receives the column address signal Yad and other controllers is the same as that of a general DRAM, and is therefore omitted.

  In FIG. 2, the address latch circuit 205 is supplied with the row address signal Xad and the row address strobe signal / RAS, and the row predecoder 206 is supplied with the output of the address latch circuit 205 and the row address strobe signal / RAS. The output of the row predecoder 206 is supplied to the row decoder 207, and the output of the row decoder 207 is supplied to the word driver block 208. The word driver block 208 includes a plurality of word drivers for driving the corresponding word lines of the plurality of word lines 202. A signal read from the memory cell 204 onto the bit line 203 is amplified by the sense amplifier block 210. At this time, the sense amplifier block 210 sets the high level voltage of the bit line 203 to the first power supply voltage VDD.

  FIG. 3 shows a detailed configuration of the memory cell 204 in FIG. 3 includes a PMOS memory cell transistor 221 having a gate connected to the corresponding word line 202, and a memory cell capacitor 222 connected to the corresponding bit line 203 via the PMOS memory cell transistor 221. It is what has.

  FIG. 4 shows a detailed configuration of the address latch circuit 205 in FIG. The address latch circuit 205 shown in FIG. 4 includes eight D flip-flops, latches an 8-bit row address signal Xad (that is, Xad0 to Xad7) in synchronization with the row address strobe signal / RAS, The row address latch signals AX0 to AX7 are output.

  FIG. 5 shows a detailed configuration of the row predecoder 206 in FIG. The row predecoder 206 shown in FIG. 5 includes eight inverters and 24 AND gates, and activates a word line based on the least significant two bits AX0 and AX1 of the row address latch signal and the row address strobe signal / RAS. In response to the signal IRAS, 4-bit word driver unit selection signals XPW0-XPW3 are generated, and 8-bit first row predecode signals XPA0-XPA7 are generated from the middle 3 bits AX2-AX4 of the row address latch signal. The second set of row predecode signals XPB0 to XPB7 of 8 bits are generated from the most significant 3 bits AX5 to AX7 of the row address latch signal. In the following description, the bits of the 4-bit word driver unit selection signals XPW0 to XPW3 are referred to as first, second, third, and fourth word driver unit selection signals, respectively, as necessary.

  FIG. 6 shows a detailed configuration of the row decoder 207 and the word driver block 208 in FIG. The row decoder 207 shown in FIG. 6 includes 64 AND gates and 64 inverters, and is a combination of the first set of row predecode signals XPA0 to XPA7 and the second set of row predecode signals XPB0 to XPB7. Accordingly, any one of 64 pairs of row decode signals AD0 to AD63, / AD0 to / AD63 is activated. The word driver unit selection signals XPW0 to XPW3 are supplied to the word driver block 208 without being subjected to any processing by the row decoder 207.

  The word driver block 208 of FIG. 6 is divided into first, second, third and fourth word driver units 701, 702, 703 and 704. When the first word driver unit 701 is selected by the first word driver unit selection signal XPW0, the first word driver unit 701 responds to the activated signal of the 64 pairs of row decode signals AD0 to AD63, / AD0 to / AD63. , / WL252 is activated by activating corresponding signals among the 64 word line drive signals / WL0, / WL4, / WL8,. When the second word driver unit 702 is selected by the second word driver unit selection signal XPW1, the second word driver unit 702 responds to the activated signal of the 64 pairs of row decode signals AD0 to AD63, / AD0 to / AD63. , / WL253 activates the corresponding signal among the 64 word line drive signals / WL1, / WL5, / WL9,. When the third word driver unit 703 is selected by the third word driver unit selection signal XPW2, the third word driver unit 703 responds to the activated signal of the 64 pairs of row decode signals AD0 to AD63, / AD0 to / AD63. , / WL254 activates the corresponding signal among the 64 word line drive signals / WL2, / WL6, / WL10,..., / WL254, thereby driving the corresponding word line. When the fourth word driver unit 704 is selected by the fourth word driver unit selection signal XPW3, the fourth word driver unit 704 responds to the activated signal of the 64 pairs of row decode signals AD0 to AD63, / AD0 to / AD63. , / WL255 is activated by driving a corresponding signal among the 64 word line drive signals / WL3, / WL7, / WL11,..., / WL255.

  FIG. 7 shows a more detailed configuration of the first to fourth word driver blocks 701 to 704 in FIG. The first word driver block 701 includes 64 word drivers 801, the second word driver block 702 includes the other 64 word drivers 841, and the third word driver block 703 includes the other 64 word drivers. 854, the fourth word driver block 704 further includes 64 other word drivers 861.

  FIG. 8 shows a more detailed configuration of the first word driver unit 701 in FIG. The detailed configuration of each of the second, third, and fourth word driver units 702 to 704 is the same as that shown in FIG.

  The word driver block 701 in FIG. 8 includes 64 word drivers 801 as already described with reference to FIG. An inverter 802 in FIG. 8 is an inverter for supplying an inverted selection signal / WD0 obtained by inverting the word driver unit selection signal XPW0 to each of the 64 word drivers 801. A word driver 801 that activates the word line drive signal / WL0 receives a pair of row decode signals AD0 and / AD0, and a word driver 801 that activates the word line drive signal / WL4 generates another pair of row decode signals. A word driver 801 that activates AD1, / AD1 and a word line drive signal / WL8 further receives another pair of row decode signals AD2, / AD2. Hereinafter, the detailed configuration of the word driver 801 that activates the word line drive signal / WL0 will be described. Each configuration of the word driver 801 that activates the other word line drive signals / WL4, / WL8,. Is the same.

  The word driver 801 includes a level shifter 51 and an output stage inverter 52. The level shifter 51 includes three NMOS transistors 803, 805, and 807 and two PMOS transistors 804 and 806, each of which is an inversion selection signal (= 1.5V) driven by the first power supply voltage VDD (= 1.5V). The first signal) / WD0, the non-inverted row decode signal (second signal) AD0, and the inverted row decode signal (third signal) / AD0 are received. LVL is the left node and LVR is the right node. The output stage inverter 52 is composed of one PMOS transistor 808 and one NMOS transistor 809.

  In the level shifter 51, the first PMOS transistor 804 includes a gate connected to the left node LVL, a source connected to the second power supply voltage VPP (= 3.3V), a drain connected to the right node LVR, have. The first NMOS transistor 805 has a gate connected to the inversion selection signal / WD0, a source connected to the ground voltage, and a drain connected to the right node LVR. Second PMOS transistor 806 has a gate connected to right node LVR, a source connected to second power supply voltage VPP, and a drain connected to left node LVL. Second NMOS transistor 807 has a gate connected to non-inverted row decode signal AD0, a source connected to inverted select signal / WD0, and a drain connected to left node LVL. Third NMOS transistor 803 has a gate connected to inverted row decode signal / AD0, a source connected to the ground voltage, and a drain connected to right node LVR.

  In the output stage inverter 52, the PMOS transistor 808 and the NMOS transistor 809 have their gates connected to each other and receive a common gate signal from the right node LVR of the level shifter 51, and their drains commonly connected to the word line drive signal / WL0. Has been. The source of the PMOS transistor 808 is connected to the third power supply voltage VINT (for example, 2.0 V), and the source of the NMOS transistor 809 is connected to the ground voltage. Here, the third power supply voltage VINT is, for example, a voltage generated from the second power supply voltage VPP by a circuit (not shown) in the DRAM 101 of FIG.

  As shown in parentheses in FIG. 8, the high level voltage of the gate signal in the output stage inverter 52 is the highest power supply voltage among the plurality of power supply voltages supplied to the system LSI chip 100 from the outside. It is also possible to set the fourth power supply voltage VINT1 (for example, 2.8V) lower than the power supply voltage VPP of 2 (= 3.3V). Here, the fourth power supply voltage VINT1 is also a voltage generated from the second power supply voltage VPP, for example, by a circuit (not shown) in the DRAM 101 of FIG. 1, similarly to the third power supply voltage VINT. However, VINT1> VINT> VDD is satisfied.

  FIG. 9 shows a read operation of the DRAM 101 of FIG. 2 when the word line drive signal / WL0 in FIG. 8 is activated to a low level voltage. In FIG. 9, GND represents the ground voltage.

  According to FIG. 9, first, the 8-bit row address signal Xad (that is, Xad0 to Xad7) is latched by the eight D flip-flops of the address latch circuit 205 at the falling edge of the row address strobe signal / RAS. The given row address is output as an 8-bit row address latch signal AX (that is, AX0 to AX7). Next, the upper 6 bits of the 8 bits of the row address latch signal AX are received, and the first set of row predecode signals XPA (that is, XPA0 to XPA7) and the second set of row predecode signals XPB are received from the row predecoder 206. (That is, XPB0 to XPB7) is output. At this time, of the 8 bits of the first set row predecode signal XPA, one bit determined by the middle 3 bits AX2 to AX4 of the row address latch signal is a high level voltage (VDD), and the other is a low level voltage (GND). Become. Similarly, of the 8 bits of the second set row predecode signal XPB, one bit determined by the most significant 3 bits AX5 to AX7 of the row address latch signal is a high level voltage (VDD), and the other is a low level voltage (GND). Become. Subsequently, the non-inverted and inverted row decode signals AD0 and / AD0 become the high level voltage (VDD) and the low level voltage (GND) by the operation of the row decoder 207 that has received these row predecode signals XPA and XPB, respectively. As a result, in the level shifter 51 of the word driver 801, the gate voltage of the second NMOS transistor 807 rises to the first power supply voltage VDD. Further, the gate voltage of the third NMOS transistor 803 becomes the ground voltage GND, and the third NMOS transistor 803 is turned off. On the other hand, since all the four bits of the word driver selection signals XPW0 to XPW3 are still at the low level voltage (GND), the level of the inverted selection signal / WD0 is the first power supply voltage VDD. At this time, the first NMOS transistor 805 is turned on, the right node LVR is set to a low level voltage (GND), and the PMOS transistor 808 of the output stage inverter 52 is turned on, so that the non-inverted and inverted row decode signals AD0 and / AD0 Selected word line drive signal / WL0 is held at third power supply voltage VINT. During this time, the bit line pair BL, / BL is precharged to an intermediate voltage between the first power supply voltage VDD and the ground voltage GND by the action of a precharge circuit (not shown).

  Next, when the word line activation signal IRAS becomes the high level voltage (VDD), one bit (here XPW0) determined by the least significant two bits AX0 and AX1 of the row address latch signal among the four bits of the word driver selection signals XPW0 to XPW3. ) Becomes a high level voltage (VDD), and the others become a low level voltage (GND). Therefore, the inversion selection signal / WD0 shown in FIGS. 8 and 9 becomes the low level voltage (GND). At this time, in the level shifter 51 of the word driver 801, the sizes of both the MOS transistors 806 and 807 can be set in advance so that the internal resistance of the second PMOS transistor 806 is larger than the internal resistance of the second NMOS transistor 807. For example, the voltage of the left node LVL is substantially equal to the ground voltage GND. Accordingly, the first PMOS transistor 804 is turned on and the voltage of the right node LVR becomes the second power supply voltage VPP (or the fourth power supply voltage VINT1), whereby the NMOS transistor 809 of the output stage inverter 52 is turned on. Word line drive signal / WL0 is discharged to ground voltage GND. As a result, the data stored in the memory cell 204 connected to the word line 202 related to the word line drive signal / WL0 is read out to the bit line 203, and the voltage of each of the bit line pair BL, / BL is changed to the sense amplifier block 210. Determined by the work of Specifically, the voltage of one bit line determined by the stored data in the bit line pair BL, / BL becomes the first power supply voltage VDD, and the voltage of the other bit line becomes the ground voltage GND.

  Thereafter, when the word line activation signal IRAS becomes the low level voltage (GND), all four bits of the word driver selection signals XPW0 to XPW3 become the low level voltage (GND), and the inverted selection signal / WD0 is the first power supply voltage VDD. Is charged. At this time, in the level shifter 51, the left node LVL is lower than the first power supply voltage VDD by the threshold voltage of the second NMOS transistor 807, and the first PMOS transistor 804 is turned off. At the same time, since the first NMOS transistor 805 is turned on, the right node LVR is discharged to the ground voltage GND, the PMOS transistor 808 of the output stage inverter 52 is turned on, and the word line drive signal / WL0 is again supplied to the third power supply voltage VINT. Is charged.

  As described above, according to the configuration of FIG. 8, the high level voltage VINT of the word line 202 is set to a voltage higher than the high level voltage VDD (= 1.5 V) of the bit line 203. Here, the high level voltage VINT of the word line 202 is preferably set so that the off-leak current of the PMOS memory cell transistor 221 is minimized in order to ensure a long charge retention time of the memory cell capacitor 222 (see FIG. 3). ). Specifically, when the high level voltage VDD of the bit line 203 is 1.5V as described above, the high level voltage VINT of the word line 202 is set to a voltage higher by about 0.5V than that, that is, about 2.0V. As a result, the off-leakage current of the PMOS memory cell transistor 221 can be minimized. When the gate voltage of the PMOS memory cell transistor 221 is lower than 2.0V, the channel leakage increases. Conversely, when the gate voltage is higher than 2.0V, GIDL (Gate Induced Drain Leakage) increases.

  In addition, according to the configuration of FIG. 8, the high level voltage of the right node LVR in the level shifter 51, that is, the high level voltage of the gate signal in the output stage inverter 52 (VPP = 3.3V or VINT1 = 2.8V) The high level voltage of the line drive signal / WL0, that is, a voltage higher than the high level voltage VINT (= 2.0 V) of the word line 202 is set. As a result, the on-state current of the NMOS transistor 809 of the output stage inverter 52 can be increased as compared with the prior art, and the word line 202 can be driven at high speed with a small element. However, when the level shift ratio (P / N transistor constant ratio) of the level shifter 51 cannot be increased so much due to the layout area limitation, the operating voltage of the level shifter 51 is supplied from the outside as described above. It is preferable to set the fourth power supply voltage VINT1 lower than the power supply voltage VPP.

  Further, according to the configuration of FIG. 8, since the level shifter 51 has an address decoding function, the configuration of the row decoder 207 can be simplified, so that the layout area of the DRAM 101 can be reduced.

  The MOS transistors 803 to 807 constituting the level shifter 51 and the MOS transistors 808 and 809 constituting the output stage inverter 52 are the logic circuit 102, the address latch circuit 205, the row predecoder 206, the row decoder 207, and the sense amplifier block. It is assumed that the gate oxide film is thicker than the MOS transistors constituting 210 and the like. This is in consideration of reliability such as the breakdown voltage of the gate oxide film.

  Since the operating voltage VINT of the output stage inverter 52 is lower than the operating voltage VPP (or VINT1) of the level shifter 51, each of the MOS transistors 808 and 809 constituting the output stage inverter 52 is provided for high-speed operation of the output stage inverter 52. Can be set to a value (LVt) lower than that of the MOS transistors 803 to 807 constituting the level shifter 51. For the same reason, the gate lengths of the MOS transistors 808 and 809 constituting the output stage inverter 52 can be set shorter than those of the MOS transistors 803 to 807 constituting the level shifter 51. By reducing the gate length of each of the MOS transistors 808 and 809, their on-resistance is reduced, so that even if the source-drain voltage is the same, more current can flow and high-speed switching can be achieved.

  FIG. 10 shows a modification of the word driver unit 701 in FIG. According to FIG. 10, a level shifter 821 is provided at the output stage of the row decoder 207. One inverter 820 is provided in the front stage of the level shifter 821, and two inverters 822 and 823 are provided in the subsequent stage. The pre-stage inverter 820 supplies a signal obtained by inverting the word driver unit selection signal XPW0 with the first power supply voltage VDD as a high level voltage to the level shifter 821. The level shifter 821 has a function of boosting the high level voltage of the signal supplied from the previous inverter 820 from the first power supply voltage VDD to the second power supply voltage VPP (or the fourth power supply voltage VINT1). Therefore, according to the output of the level shifter 821, one rear stage inverter 822 is obtained by inverting the non-inverted selection signal WD0 based on the word driver unit selection signal XPW0, and the other rear stage inverter 823 is obtained by inverting the word driver unit selection signal XPW0. The inversion selection signal / WD0 is distributed to 64 word drivers 801, respectively. The high level voltages of the non-inverted and inverted selection signals WD0 and / WD0 are set to the second power supply voltage VPP (or the fourth power supply voltage VINT1). A word driver 801 that activates the word line drive signal / WL0 receives a pair of row decode signals AD0 and / AD0, and a word driver 801 that activates the word line drive signal / WL4 generates another pair of row decode signals. A word driver 801 that activates AD1, / AD1 and a word line drive signal / WL8 further receives another pair of row decode signals AD2, / AD2. The high level voltages of these row decode signals are all the first power supply voltage VDD.

  The word driver 801 of FIG. 10 is different from the configuration of FIG. 8 in that the level shifter 51 further includes a third PMOS transistor 810. 10 includes an inversion selection signal (first signal) / WD0, a non-inversion selection signal (second signal) WD0, a non-inversion row decode signal (third signal) AD0, and an inversion row decode. The signal (fourth signal) / AD0 is received. In the level shifter 51, the first PMOS transistor 804 is connected to the gate connected to the left node LVL, the source connected to the second power supply voltage VPP (or the fourth power supply voltage VINT1), and the right node LVR. With a drain. The first NMOS transistor 805 has a gate connected to the inversion selection signal / WD0, a source connected to the ground voltage, and a drain connected to the right node LVR. The second PMOS transistor 806 includes a gate connected to the right node LVR, a source connected to the second power supply voltage VPP (or the fourth power supply voltage VINT1), and a drain connected to the left node LVL. Have. Second NMOS transistor 807 has a gate connected to non-inverted row decode signal AD0, a source connected to inverted select signal / WD0, and a drain connected to left node LVL. Third NMOS transistor 803 has a gate connected to inverted row decode signal / AD0, a source connected to the ground voltage, and a drain connected to right node LVR. The third PMOS transistor 810 has a gate connected to the non-inverting selection signal WD0, a source connected to the second power supply voltage VPP (or the fourth power supply voltage VINT1), and a drain connected to the left node LVL. And have. The gate signal to be supplied to the output stage inverter 52 is obtained from the right node LVR.

  According to the configuration of FIG. 10, the second power supply voltage VPP (or the fourth power supply voltage VINT1) is set to the high level voltage by boosting the word driver unit selection signal XPW0 activated by the word line activation signal IRAS. Non-inverted and inverted selection signals WD0 and / WD0 to be generated and these non-inverted and inverted selection signals WD0 and / WD0 are distributed to the 64 word drivers 801. Therefore, the level of the level shifter 51 is limited due to the layout area restriction. Even when the shift ratio (P / N transistor constant ratio) cannot be increased so much, the on-current of the NMOS transistor 809 of the output stage inverter 52 can be increased as compared with the prior art, and the word line 202 can be made faster with a smaller element. Can be driven.

  In addition, when the voltage of the word line drive signal / WL0 is restored from the low level voltage (GND) to the high level voltage (VINT), the non-inversion selection signal WD0 input to the gate of the third PMOS transistor 810 is the low level voltage. (GND), the left node LVL is charged to the second power supply voltage VPP (or the fourth power supply voltage VINT1) at a high speed, the first PMOS transistor 804 is turned off, and at the same time, the inverted selection signal / WD0 is The voltage rises to the second power supply voltage VPP (or the fourth power supply voltage VINT1), the first NMOS transistor 805 is turned on, and the right node LVR is rapidly lowered to the ground voltage GND, so that the word line drive signal / WL0 Is charged to the third power supply voltage VINT at high speed.

  Further, only one level shifter 821 in the row decoder 207 is arranged for the 64 word drivers 801, and the influence of the area increase is small. Rather, the level shift ratio of the level shifter 51 provided in each word driver 801 is set. The area reduction effect by being able to be smaller is greater.

  Note that the high level voltage of the non-inversion and inversion selection signals WD0 and / WD0 may be higher than the high level voltage of the node LVR. For example, the operating voltage of the level shifter 821 in the row decoder 207 can be the second power supply voltage VPP, and the operating voltage of the level shifter 51 in each word driver 801 can be the fourth power supply voltage VINT1.

  FIG. 11 shows a first modification of the row predecoder 206 of FIG. According to FIG. 11, a level shifter 400 is provided at the output stage of the row predecoder 206. The level shifter 400 includes a 4-bit word driver unit selection signal XPW0 to XPW3, an 8-bit first set row predecode signal XPA0 to XPA7, and an 8-bit second set row predecode signal XPB0 to XPB7. The predecoder 206 has a function of boosting the high level voltage of all output signals from the first power supply voltage VDD to the second power supply voltage VPP (or the fourth power supply voltage VINT1). Although not shown, the row decoder 207 located at the next stage of the row predecoder 206 in FIG. 11 uses the second power supply voltage VPP (or the fourth power supply voltage VINT1) as an operating voltage.

  FIG. 12 shows a configuration of a word driver unit 701 suitable when the row predecoder 206 of FIG. 11 is employed. The word driver unit 701 in FIG. 12 includes 64 word drivers 801 as in the case of FIGS. A buffer 830 in FIG. 12 is a buffer for supplying a non-inverted selection signal WD0 based on the word driver unit selection signal XPW0 to each of the 64 word drivers 801. The high level voltage of the non-inversion selection signal WD0 is set to the second power supply voltage VPP (or the fourth power supply voltage VINT1) by the buffer 830. Then, the word driver 801 that activates the word line drive signal / WL0 receives the inverted row decode signal / AD0, the word driver 801 that activates the word line drive signal / WL4 receives the other inverted row decode signal / AD1, and the word line The word driver 801 that activates the drive signal / WL8 further receives another inverted row decode signal / AD2. The high level voltages of the inverted row decode signals / AD0, / AD1, / AD2,... / AD63 are set to the second power supply voltage VPP (or the fourth power supply voltage VINT1) by the row decoder 207. Hereinafter, the detailed configuration of the word driver 801 that activates the word line drive signal / WL0 will be described. Each configuration of the word driver 801 that activates the other word line drive signals / WL4, / WL8,. Is the same.

  The word driver 801 includes an input stage inverter 61 and an output stage inverter 62. The input stage inverter 61 is composed of a first PMOS transistor 831 and a first NMOS transistor 832, and each is driven by a second power supply voltage VPP (or a fourth power supply voltage VINT1). The first signal) WD0 and the inverted row decode signal (second signal) / AD0 are received. N1 is an output node (first node) of the input stage inverter 61, and N2 is an output node (second node) of the output stage inverter 62. The output stage inverter 62 includes a second PMOS transistor 833 and second and third NMOS transistors 834 and 835.

  In the input stage inverter 61, the first PMOS transistor 831 includes a gate connected to the inverted row decode signal / AD0, a source connected to the non-inverted selection signal WD0, and a drain connected to the first node N1. have. First NMOS transistor 832 has a gate connected to inverted row decode signal / AD0, a source connected to ground voltage, and a drain connected to first node N1.

  In the output stage inverter 62, the second PMOS transistor 833 includes a gate connected to the first node N1, a source connected to the third power supply voltage VINT, and a drain connected to the second node N2. have. Second NMOS transistor 834 has a gate connected to first node N1, a source connected to ground voltage, and a drain connected to second node N2. Third NMOS transistor 835 has a gate connected to second node N2, a source connected to ground voltage, and a drain connected to first node N1. The second node N2 is a node that applies the word line drive signal / WL0 to the specific word line 202.

  11 and 12 also, the high level voltage of the output node N1 in the input stage inverter 61, that is, the high level voltage of the gate signal in the output stage inverter 62 (VPP = 3.3V or VINT1 = 2.8V) is obtained. The high level voltage of the word line drive signal / WL0, that is, a voltage higher than the high level voltage VINT (= 2.0 V) of the word line 202 is set. As a result, the on-current of the NMOS transistor 834 of the output stage inverter 62 can be increased as compared with the prior art, and the word line 202 can be driven at high speed with a small element.

  In addition, according to the configuration of FIGS. 11 and 12, since it is not necessary to provide a level shifter for each word driver 801, the number of level shifters can be dramatically reduced. Since the level shifter 400 in the row predecoder 206 can select a transistor size with a large level shift ratio, a high-speed level shift operation is possible. Further, since each word driver 801 does not require a level shift operation, the degree of freedom in setting the transistor size of each word driver 801 is increased (the transistor size level shift ratio need not be considered), and the layout size can be reduced. . Therefore, a high-speed and area-saving word driver 801 can be realized.

  The MOS transistors constituting each of the level shifter 400, the row decoder 207, and the word driver block 208 in the row predecoder 206 are the logic circuit 102, the address latch circuit 205, other portions in the row predecoder 206, and the sense amplifier block. It is assumed that the gate oxide film is thicker than the MOS transistors constituting 210 and the like. This is in consideration of reliability such as the breakdown voltage of the gate oxide film.

  Since the operating voltage VINT of the output stage inverter 62 is lower than the operating voltage VPP (or VINT1) of the input stage inverter 61, the second PMOS transistor 833 and the second NMOS transistor 834 are used for the high speed operation of the output stage inverter 62. Can be set to a lower value (LVt) than the first PMOS transistor 831 and the first and third NMOS transistors 32 and 835. For the same reason, the gate length of each of the second PMOS transistor 833 and the second NMOS transistor 834 is set shorter than that of the first PMOS transistor 831 and the first and third NMOS transistors 32 and 835. It can also be left. By reducing the gate length of each of the MOS transistors 833 and 834, their on-resistance is reduced, so that even if the source-drain voltage is the same, more current can flow and high-speed switching can be achieved.

  FIG. 13 shows a second modification of the row predecoder 206 of FIG. According to FIG. 13, a level shifter 401 is provided at the input stage of the row predecoder 206. The level shifter 401 converts the high level voltages of all input signals of the row predecoder 206 including the word line activation signal IRAS and the 8-bit row address latch signals AX0 to AX7 from the first power supply voltage VDD to the second power supply. The voltage VPP (or the fourth power supply voltage VINT1) is boosted. If the configurations of FIGS. 12 and 13 are employed, the number of level shifters can be further reduced. A similar level shifter can be provided at the input stage of the address latch circuit 205.

  FIG. 14 shows a system LSI chip suitable when the row predecoder 206 shown in FIG. 11 or FIG. 13 is adopted. In the system LSI chip 100 of FIG. 14, the DRAM 101 is supplied with the memory main power supply voltage VDD_DRAM (first power supply voltage: 1.5V, for example) and the second power supply voltage VPP (for example, 3.3V). The logic circuit 102 is supplied with a logic main power supply voltage VDD_LOGIC (eg, 1.3 V) lower than the memory main power supply voltage VDD_DRAM in order to reduce power consumption. The analog circuit 103 is supplied with the second power supply voltage VPP.

  According to FIG. 14, the high level voltage of the signal such as the row address strobe signal / RAS, the row address signal Xad, and the column address signal Yad output from the logic circuit 102 is the logic main power supply voltage VDD_DRAM. Therefore, the row address strobe signal / RAS and the column address signal Yad are signals for setting the memory main power supply voltage VDD_DRAM to the high level voltage via the level shifters 105 and 106, respectively, and the row address signal Xad is a logic main power supply without using the level shifter. Each signal is input to the DRAM 101 as a signal for setting the voltage VDD_LOGIC to a high level voltage. The level shifter 400 in FIG. 11 or the level shifter 401 in FIG. 13 has a function of boosting the high level voltage of each signal from the logic main power supply voltage VDD_LOGIC to the second power supply voltage VPP (or the fourth power supply voltage VINT1) at once. Have.

  Needless to say, the present invention is not limited to the specific examples described above, and various modifications can be made without departing from the scope of the invention. For example, the row address has an 8-bit configuration, but other configurations may be used. Moreover, each said power supply voltage value can be changed as needed.

  As described above, the semiconductor memory device according to the present invention includes a word driver that can drive a word line at high speed without increasing the layout area, and in particular, a DRAM formed on the same semiconductor substrate together with an analog circuit and other logic circuits. It is useful for such as.

1 is a plan view of a system LSI chip on which a DRAM which is a semiconductor memory device according to the present invention is mounted. FIG. 2 is a block diagram showing a schematic configuration of a DRAM in FIG. 1. FIG. 3 is a circuit diagram showing a detailed configuration of a memory cell in FIG. 2. FIG. 3 is a circuit diagram showing a detailed configuration of an address latch circuit in FIG. 2. FIG. 3 is a circuit diagram showing a detailed configuration of a row predecoder in FIG. 2. FIG. 3 is a block diagram illustrating a detailed configuration of a row decoder and a word driver block in FIG. 2. FIG. 7 is a block diagram showing a more detailed configuration of the word driver block in FIG. 6. FIG. 7 is a circuit diagram showing a more detailed configuration of one word driver unit in FIG. 6. FIG. 3 is a timing chart showing the operation of the DRAM of FIG. 2. FIG. 9 is a circuit diagram showing a modification of the word driver unit of FIG. 8. FIG. 6 is a circuit diagram showing a first modification of the row predecoder of FIG. 5. FIG. 12 is a circuit diagram showing a configuration of a word driver unit suitable when the row predecoder of FIG. 11 is adopted. FIG. 6 is a circuit diagram showing a second modification of the row predecoder of FIG. 5. FIG. 14 is a plan view of a system LSI chip suitable for employing the row predecoder of FIG. 11 or FIG. 13.

Explanation of symbols

51 level shifter 52 output stage inverter 61 input stage inverter 62 output stage inverter 100 system LSI chip 101 DRAM
102 logic circuit 103 analog circuit 104 pad 105, 106 level shifter 201 memory array 202 word line 203 bit line 204 memory cell 205 address latch circuit 206 row predecoder 207 row decoder 208 word driver block 210 sense amplifier block 221 PMOS memory cell transistor 222 memory Cell capacitor 400, 401 Level shifter 701, 702, 703, 704 Word driver unit 801 Word driver 802 Inverter 803, 805, 807, 809 NMOS transistor 804, 806, 808, 810 PMOS transistor 820, 822, 823 Inverter 821 Level shifter 830 Buffer 831 833 PMOS transistor 832 834 835 NMOS transistors 841, 851, 861 Word drivers AD0 to AD63 Non-inverted row decode signal / AD0 to / AD63 Inverted row decode signals AX0 to AX7 Row address latch signal BL, / BL Bit line pair IRAS Word line start signal LVL, LVR Node N1 , N2 node / RAS row address strobe signal VDD first power supply voltage (1.5V)
VDD_DRAM Memory main power supply voltage (1.5V)
VDD_LOGIC Logic main power supply voltage (1.3V)
VINT Third power supply voltage (2.0V)
VINT1 Fourth power supply voltage (2.8V)
VPP Second power supply voltage (3.3V)
WD0, / WD0 Non-inversion and inversion selection signal / WL0 to / WL255 Word line drive signal Xad Row address signal (8 bits)
Xad0 to Xad7 Row address signal XPA0 to XPA7 Row predecode signal XPB0 to XPB7 Row predecode signal XPW0 to XPW3 Word driver unit selection signal Yad Column address signal

Claims (17)

Multiple word lines,
Multiple bit lines,
A plurality of memory cells each connected to one of the plurality of word lines and one of the plurality of bit lines;
A semiconductor memory device comprising a plurality of word drivers each for driving a corresponding word line of the plurality of word lines,
Each of the plurality of word drivers has an output stage inverter composed of a PMOS transistor and an NMOS transistor, and each drain of the PMOS transistor and the NMOS transistor is common to any one of the plurality of word lines. Connected to each other, the gates of the PMOS transistor and the NMOS transistor are connected to each other to receive a common gate signal,
The semiconductor memory device according to claim 1, wherein a high level voltage of the gate signal is set to a voltage higher than a high level voltage of each of the plurality of word lines. The semiconductor memory device according to claim 1.
The semiconductor memory device is formed on the same semiconductor substrate together with an analog circuit and other logic circuits,
The semiconductor memory device according to claim 1, wherein the high level voltage of the gate signal is set to the highest power supply voltage among a plurality of power supply voltages supplied to the semiconductor substrate. The semiconductor memory device according to claim 1.
The semiconductor memory device is formed on the same semiconductor substrate together with an analog circuit and other logic circuits,
The high-level voltage of the gate signal is set to a voltage lower than the highest power supply voltage among a plurality of power supply voltages supplied to the semiconductor substrate. The semiconductor memory device according to claim 1.
A semiconductor memory device, wherein a gate oxide film of each of the MOS transistors constituting the plurality of word drivers is thicker than a MOS transistor constituting another certain circuit portion in the semiconductor memory device. The semiconductor memory device according to claim 1.
Each of the plurality of memory cells includes
A PMOS memory cell transistor having a gate connected to a corresponding word line of the plurality of word lines;
A memory cell capacitor connected to a corresponding bit line of the plurality of bit lines via the PMOS memory cell transistor;
A semiconductor memory device, wherein a high level voltage of each of the plurality of word lines is set to a voltage higher than a high level voltage of each of the plurality of bit lines. The semiconductor memory device according to claim 1.
Each of the plurality of word drivers further includes a level shifter that receives a plurality of input signals in addition to the output stage inverter.
The level shifter is driven by a first power supply voltage at least one of the plurality of input signals, operates at a second power supply voltage higher than the first power supply voltage, and supplies the output stage inverter with the level shifter A high level voltage of the gate signal is set to the second power supply voltage;
The output stage inverter operates at a third power supply voltage lower than the second power supply voltage, and supplies a high level voltage of a signal supplied to a corresponding word line among the plurality of word lines. A semiconductor memory device, characterized by being set to a power supply voltage. The semiconductor memory device according to claim 6.
2. A semiconductor memory device according to claim 1, wherein a threshold voltage of each of the PMOS transistor and the NMOS transistor constituting the output stage inverter is lower than that of the MOS transistor constituting the level shifter. The semiconductor memory device according to claim 6.
A semiconductor memory device, wherein the gate length of each of the PMOS transistor and the NMOS transistor constituting the output stage inverter is shorter than that of the MOS transistor constituting the level shifter. The semiconductor memory device according to claim 6.
The level shifter included in each of the plurality of word drivers is:
Each receiving a first signal driven by the first power supply voltage, a second signal, and a third signal that is an inverted signal of the second signal; and
A first PMOS transistor having a gate connected to a first node, a source connected to the second power supply voltage, and a drain connected to a second node;
A first NMOS transistor having a gate connected to the first signal, a source connected to a ground voltage, and a drain connected to the second node;
A second PMOS transistor having a gate connected to the second node, a source connected to the second power supply voltage, and a drain connected to the first node;
A second NMOS transistor having a gate connected to the second signal, a source connected to the first signal, and a drain connected to the first node;
A third NMOS transistor having a gate connected to the third signal, a source connected to the ground voltage, and a drain connected to the second node;
The semiconductor memory device, wherein the gate signal to be supplied to the output stage inverter is supplied to the second node. The semiconductor memory device according to claim 6.
A row having a level shifter for boosting a high level voltage of an input signal common to some of the plurality of word drivers from the first power supply voltage to the second power supply voltage among the plurality of input signals. A semiconductor memory device further comprising a decoder. The semiconductor memory device according to claim 10.
The level shifter included in each of the plurality of word drivers is:
The row decoder receives a first signal driven by the second power supply voltage and a second signal which is an inverted signal of the first signal, and is driven by the first power supply voltage. And a fourth signal that is an inverted signal of the third signal, and
A first PMOS transistor having a gate connected to a first node, a source connected to the second power supply voltage, and a drain connected to a second node;
A first NMOS transistor having a gate connected to the first signal, a source connected to a ground voltage, and a drain connected to the second node;
A second PMOS transistor having a gate connected to the second node, a source connected to the second power supply voltage, and a drain connected to the first node;
A second NMOS transistor having a gate connected to the third signal, a source connected to the first signal, and a drain connected to the first node;
A third NMOS transistor having a gate connected to the fourth signal, a source connected to the ground voltage, and a drain connected to the second node;
A third PMOS transistor having a gate connected to the second signal, a source connected to the second power supply voltage, and a drain connected to the first node;
The semiconductor memory device, wherein the gate signal to be supplied to the output stage inverter is supplied to the second node. The semiconductor memory device according to claim 1.
A row predecoder having a level shifter for boosting the high level voltage of each of the plurality of row predecode signals to be output from the first power supply voltage to a second power supply voltage higher than the first power supply voltage;
A row decoder for generating a plurality of row decode signals having the second power supply voltage as a high level voltage from the boosted plurality of row predecode signals;
Each of the plurality of word drivers further includes an input stage inverter that receives a corresponding row decode signal among the plurality of row decode signals, in addition to the output stage inverter.
The input stage inverter sets the high level voltage of the gate signal supplied to the output stage inverter to the second power supply voltage,
The output stage inverter operates at a third power supply voltage lower than the second power supply voltage, and supplies a high level voltage of a signal supplied to a corresponding word line among the plurality of word lines. A semiconductor memory device, characterized by being set to a power supply voltage. The semiconductor memory device according to claim 12.
A threshold voltage of each of said PMOS transistor and said NMOS transistor constituting said output stage inverter is lower than that of a MOS transistor constituting said input stage inverter. The semiconductor memory device according to claim 12.
A semiconductor memory device, wherein the gate length of each of the PMOS transistor and the NMOS transistor constituting the output stage inverter is shorter than that of the MOS transistor constituting the input stage inverter. The semiconductor memory device according to claim 12.
The input stage inverter of each of the plurality of word drivers receives a first signal driven by the second power supply voltage and a second signal from the row predecoder or the row decoder, And,
A first PMOS transistor having a source connected to the first signal, a drain connected to a first node, and a gate connected to the second signal;
A first NMOS transistor having a source connected to ground voltage, a drain connected to the first node, and a gate connected to the second signal;
The output stage inverter included in each of the plurality of word drivers is:
A second PMOS transistor having a gate connected to the first node, a source connected to the third power supply voltage, and a drain connected to a second node;
A second NMOS transistor having a gate connected to the first node, a source connected to the ground voltage, and a drain connected to the second node;
A third NMOS transistor having a gate connected to the second node, a source connected to the ground voltage, and a drain connected to the first node;
A semiconductor memory device, wherein a signal to be supplied to a corresponding word line of the plurality of word lines is supplied to the second node. The semiconductor memory device according to claim 12.
The level shifter of the row predecoder is arranged at an output stage or an input stage of the row predecoder. The semiconductor memory device according to claim 12.
The semiconductor memory device is formed on the same semiconductor substrate together with other logic circuits, the other logic circuit operates at a logic main power supply voltage, and the semiconductor memory device operates at a memory main power supply voltage higher than the logic main power supply voltage. To do,
The high level voltage of the row address signal, column address signal and other control signals output from the other logic circuit is the logic main power supply voltage,
The column address signal and the other control signals are each set as a signal for setting the memory main power supply voltage to a high level voltage via a level shifter, and the row address signal is used for setting the logic main power supply voltage to a high level voltage without passing through a level shifter. Input to the semiconductor memory device as a signal to be
The level shifter of the row predecoder boosts the high level voltage of each of the plurality of row predecode signals from the logic main power supply voltage to the second power supply voltage higher than the logic main power supply voltage. A semiconductor memory device.

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