JP2005222620A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To restrain an off-leak current without fail and improve an access speed. <P>SOLUTION: An NMOS transistor 313 is turned on and a word line 142 is set to a ground level, until the word line 142 is selected by a selection signal XW0, in a pre-charging time period of a bit line. When the word line 142 is selected, consequently, the word line 142 is lifted quickly to a VINT level. In a word line 142 which is not selected, the NMOS transistor 314 is turned on in a period of time during the operation of a sense amplifier, and the potential of the word line 142 is decreased to a negative electric potential (VNB). Consequently, the off-leak current of an access transistor is reduced, and data-sustaining characteristics of a memory cell are improved. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device such as a DRAM (dynamic random access memory).

  For example, in a DRAM, a predetermined voltage is selectively applied to a word line, and an access transistor whose gate is connected to the word line is turned on, so that the bit line is changed according to the electric charge accumulated in the capacitor. The generated potential difference is amplified by a sense amplifier to read the stored data, or a voltage corresponding to the write data is applied to the bit line to accumulate the electric charge in the capacitor to write the data. On the other hand, since the access transistor whose gate is connected to the non-selected word line, that is, the word line to which the predetermined voltage is not applied (for example, 0 V is applied) is turned off, the charge accumulated in the capacitor is maintained. Is done.

However, even when a voltage of 0 V is applied to the word line, the access transistor is not necessarily turned off completely, and when an off-leakage current flows, data retention characteristics deteriorate. In recent years, this problem has become more prominent as the threshold voltage of the transistor decreases due to the lowering of the operating voltage. In order to improve data retention characteristics, a technique for applying a negative voltage to non-selected word lines has been proposed (see, for example, Patent Document 1).
JP-A-8-63964

  However, when a negative voltage is applied to a non-selected word line as described above, when a predetermined voltage is applied to the word line and selected, the voltage of the word line rises to the applied voltage. It takes a long time to complete. Therefore, it has been difficult to increase the speed of memory access.

  The present invention has been made in view of the above points, and an object of the present invention is to make it possible to easily suppress an off-leakage current and to easily increase the access speed.

In view of the above points, the invention of claim 1
Multiple word lines,
Multiple bit lines,
A semiconductor memory device having a plurality of access switching elements that are turned on when a power supply potential source is connected to a corresponding word line when selected,
Two types of power source potential sources are switched and connected to the non-selected word line.

The invention of claim 2
The semiconductor memory device according to claim 1,
The potentials of the two types of power source potential sources are a first potential and a second potential between the first potential and the potential of the power source potential source at the time of selection.
Before the connection of the power supply potential source at the time of selection to the selected word line is started, the power supply potential source of the second potential is connected to the word line,
After the connection of the power supply potential source at the time of selection to the selected word line is started, the power supply potential source of the first potential is switched and connected to the unselected word line. It is characterized by that.

The invention of claim 3
The semiconductor memory device according to claim 2,
The access switching element is an N-type transistor and the first potential is lower than a second potential, or the access switching element is a P-type transistor and the first potential is a second potential The potential is higher than the potential.

  As a result, when a word line is selected, the power supply potential is quickly set at the time of selection so that the access can be performed at high speed, while the non-selected word line is set to a reverse bias potential and an off-leakage current is generated. It is possible to easily reduce the data retention characteristics of the DRAM.

The invention of claim 4
The semiconductor memory device according to claim 3,
The second potential is a ground potential, and an absolute value of a potential difference between the first potential and the second potential is lower than a threshold voltage of the access switching element.

  Thereby, it is possible to easily improve the reliability by preventing the access switching element from deteriorating.

The invention of claim 5
The semiconductor memory device according to claim 3,
The power supply potential source having the first potential is connected to the non-selected word line during a period in which an operation for amplifying a potential difference generated in the bit line is performed.

The invention of claim 6
6. The semiconductor memory device according to claim 5, wherein
A plurality of first switching elements each connecting and disconnecting each word line and the power source potential source of the first potential;
A plurality of second switching elements each connecting and disconnecting each word line and the power source potential source of the second potential,
The first switching element is turned on during a period in which the corresponding word line is not selected and the amplification operation is performed,
The second switching element is in an ON state during a period when the corresponding word line is not selected and the precharge operation to the bit line is being performed.

The invention of claim 7
The semiconductor memory device according to claim 3,
The power supply potential source having the first potential is connected to the non-selected word line during a period when the precharge operation to the bit line is not performed.

The invention of claim 8
8. The semiconductor memory device according to claim 7, wherein
A plurality of first switching elements each connecting and disconnecting each word line and the power source potential source of the first potential;
A plurality of second switching elements each connecting and disconnecting each word line and the power source potential source of the second potential,
The first switching element is turned on during a period in which the corresponding word line is not selected and the precharge operation is not performed.
The second switching element is in an on state during a period when the corresponding word line is not selected and the precharge operation is performed.

  As a result, the potential of the word line can be easily controlled as described above.

  According to the present invention, even when the threshold voltage of the access transistor is low, it is easy to reliably suppress the off-leakage current, and it is possible to easily increase the access speed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 of the Invention
As shown in FIG. 1, a DRAM 100 that is a semiconductor memory device includes a memory circuit 101 and a power supply circuit 201.

  The memory circuit 101 includes a memory cell array 111, a sense amplifier 112, a precharge / equalize circuit 113, a row address buffer 121, a row decoder 122, a word driver 123, a column address buffer 131, a column decoder 132, a data I / O buffer 133, And a read / write amplifier 134. The memory cell array 111 has a memory cell 141 composed of a capacitor 141a and an access transistor 141b, a word line 142, and a bit line pair 143 in which a bit line 143a and an inverted bit line 143b are paired. For example, a MIS (Metal Insulator Semiconductor) type transistor is used as the transistor constituting each circuit.

  The power supply circuit 201 supplies the following voltages to the respective units.

VINT: Voltage supplied from the external power supply voltage supplied to the word driver 123 VDD: Voltage supplied to the sense amplifier 112, an operation control circuit (for example, the row decoder 122) for controlling the operation of the DRAM 100, etc. VBP: Bit line The voltage supplied to the precharge and equalize circuit 113 to precharge 143a and 143b, for example, a voltage approximately equal to VDD / 2, for example, VCP: the voltage supplied to the common counter electrode of each capacitor 141a VBB: supplied to the substrate of the access transistor 141b Voltage VNB: A negative bias voltage supplied to the word driver 123 and applied to the word line 142 that is not selected based on the row address in order to reduce leakage current.

  The sense amplifier 112 of the memory circuit 101 amplifies the voltage difference between the bit lines 143a and 143b when the sense signal SE is at the VDD level.

  The precharge / equalize circuit 113 sets both the voltages of the bit lines 143a and 143b to the VBP level in response to the precharge signal PR becoming the VDD level before the sense signal SE becomes the VDD level. It has become.

  The word driver 123 selectively applies the voltage VINT to any one of the word lines 142 according to the decoding result of the row address by the row decoder 122. Specifically, the word driver 123 includes a level shifter circuit 311, a PMOS transistor 312 (PMOS: P-type Metal Oxide Semiconductor), and two NMOSs as shown in FIG. 2, for example, for a circuit for one word line 142. It has transistors 313 and 314 (NMOS: N-type Metal Oxide Semiconductor), an AND circuit 316, and a NOT circuit 317, and applies the voltage VINT when the word line 142 is selected, while it does not select it. A negative bias voltage VNB is applied. The word line 142 is set to the VSS level (ground level) before selection is started.

  More specifically, the level shifter circuit 311 performs the selection when the word line 142 is selected by the decoding result of the row address by the row decoder 122 (when the selection signal XW0 becomes the VDD level). The level of the signal XW0 is converted to the VINT level and input to the gate of the PMOS transistor 312.

  The PMOS transistor 312 outputs the voltage VINT to the word line 142 when it is indicated that the word line 142 is selected according to the signal input to the gate from the level shifter circuit 311. . That is, the word line 142 is set to the VINT level when the selection signal XW0 becomes the VDD level.

  The NMOS transistor 313 is turned on when the precharge signal PR is at the VDD level, and the word line 142 is set at the VSS level.

  On the other hand, the NMOS transistor 314 is turned on when the selection signal XW0 is at the VSS level and the sense signal SE is at the VDD level, and the word line 142 is set to the VNB level lower than the ground level. Here, when the NMOS transistor is used as the access transistor 141b, for example, as described above, the VNB level can reduce the off-leakage current of the access transistor 141b. However, the reliability of the access transistor 141b is not improved. From the viewpoint of preventing the transistor from being turned on, it is preferable that the absolute value of the VNB level is lower than the threshold voltage of the access transistor 141b or the NMOS transistor 313.

  Next, regarding the operation of the DRAM 100 configured as described above, as shown in FIG. 3, when (1) the selection signal XW0 is at the VDD level and the word line 142 is selected, (2) the selection signal XW0 is The case where the word line 142 is not selected at the VSS level will be described separately.

(1) When the selection signal XW0 becomes VDD level (Period a) When the precharge signal PR becomes VDD level, the precharge / equalize circuit 113 sets the voltages of the bit lines 143a and 143b to VBP level. At this time, the NMOS transistor 313 is turned on, and the voltage of the word line 142 is reliably set to the VSS level.

  (Period b) When the precharge signal PR becomes VSS level, the NMOS transistor 313 is turned OFF, and when the selection signal XW0 becomes VDD level, the voltage of the word line 142 also starts to rise. At this time, since the voltage of the word line 142 is set to the VSS level in (period a) as described above, the voltage rises more rapidly than when the voltage is set to the VNB level.

  (Period c) When the voltage of the word line 142 exceeds a predetermined threshold voltage, the access transistor 141b is turned on, and the voltages of the bit lines 143a and 143b become voltages corresponding to the charges accumulated in the capacitor 141a.

  (Period d) When the sense signal SE becomes the VDD level, the voltage difference between the bit lines 143a and 143b is amplified by the sense amplifier 112, and the bit lines 143a and 143b become the VDD level or the VSS level, respectively, and are stored in the capacitor 141a. Data corresponding to the stored charge is output from the data I / O buffer 133.

(2) When the selection signal XW0 remains at the VSS level (Period a) When the selection signal XW0 returns to the VSS level and the precharge signal PR becomes the VDD level as in (Period a) of (1) above, The voltage of the bit lines 143a and 143b is set to the VBP level, the NMOS transistor 313 is turned on, and the voltage of the word line 142 is reliably set to the VSS level.

  (Period b) Thereafter, if the selection signal XW0 does not become the VDD level, the PMOS transistor 312 is kept in the OFF state, and the word line 142 is kept at the VSS level.

  (Period c) Since the selection signal XW0 is at the VSS level, the voltage of the word line 142 is maintained at the VSS level. On the other hand, when the selection signal XW0 corresponding to another word line (for example, the word line 142 ′ in FIG. 1) at the VDD level becomes the same as (period c) in (1) above, the access transistor 141b ′ is turned ON. Thus, the voltage of the bit lines 143a and 143b becomes a voltage corresponding to the electric charge accumulated in the capacitor 141a ′.

  (Period d) When the sense signal SE becomes the VDD level, the voltage difference between the bit lines 143a and 143b is amplified by the sense amplifier 112 as in (Period d) in (1) above, and the charge accumulated in the capacitor 141a ′ The data corresponding to the data is output from the data I / O buffer 133. At this time, the voltage of the word line 142 is lowered to the VNB level by turning on the NMOS transistor 314 because the sense signal SE is at the VDD level while the selection signal XW0 is at the VSS level. Therefore, the off-leakage current of the access transistor 141b connected to the word line 142 is kept small. Therefore, the fluctuation of the electric charge accumulated in the capacitor 141a can be suppressed small, and the data retention characteristic is improved.

<< Embodiment 2 of the Invention >>
In the DRAM which is the semiconductor memory device of the second embodiment, a word driver 423 as shown in FIG. 4 is used instead of the word driver 123. The word driver 423 is provided with a NOR circuit 416 instead of the AND circuit 316 and the NOT circuit 317 of the word driver 123 in the first embodiment. Other components are the same as those of the first embodiment, and the same reference numerals are given and description thereof is omitted.

  The NMOS transistor 313 is controlled by the precharge signal PR, and the ON / OFF operation timing is the same as in the first embodiment. On the other hand, the NMOS transistor 314 is controlled by the NOR circuit 416. As shown in FIG. 5, when the selection signal XW0 remains at the VSS level (when the word line 142 is not selected), the precharge signal PR is During the VSS level, the word line 142 is pulled down to the VNB level.

  Also in the above configuration, the voltage of the word line 142 is reliably set to the VSS level during the precharge period (the precharge signal PR is at the VDD level) and the selection signal XW0 is at the VSS level (for example, ( Since the period a) of 1), the voltage rises quickly when the word line 142 is selected. On the other hand, when the selection signal XW0 is at the VSS level and the period other than the precharge (the precharge signal PR is at the VSS level), the voltage of the word line 142 is lowered to the VNB level (period d in (2)), and access is performed. The off-leakage current of the transistor 141b is suppressed and data retention characteristics are improved. In particular, since the period during which the voltage of the word line 142 is lowered is longer than that in the first embodiment, the data retention characteristic can be further improved.

  In the above example, only the case where the stored data is read has been described. However, the word line 142 may be driven in the same manner even when writing is performed.

  Further, although an example in which an NMOS transistor is used as the access transistor 141b is shown, the present invention is not limited to this, and the present invention can be applied even when a PMOS transistor is used. That is, when a PMOS transistor is used, the voltage applied to the non-selected word line is set to be higher in, for example, the period during which the sense amplifier is operating or the period other than the precharge period than the precharge period. You can do it.

  Moreover, while the AND circuit 316 is used for the word driver 123 of the first embodiment, the NOR circuit 416 is used for the word driver 423 of the second embodiment. The potential of 142 may be controlled similarly.

  In addition, although the example in which the selection signal XW0 and the precharge signal PR or the sense signal SE is used to control the word line 142 to the VSS level or the VNB level has been shown, the present invention is not limited thereto, and for example, it is selected. The potential of the word line 142 (to which the voltage VINT is applied) is set to the ground level before rising, and the potential of the unselected word line 142 is set to the VNB level after it is determined that the selection is not selected. Various signals may be used as long as the signals can be controlled as described above. That is, within a range satisfying the above conditions, the period during which the non-selected word line 142 is at the VNB level is lengthened, or the potential of the selected word line 142 is decreased (the application of the voltage VINT is It may be once set to the VNB level even after it is stopped. In that case, if the potential of the word line 142 becomes the ground level or is sufficiently lowered and then connected to the negative power supply (VNB), the capacity of the negative power supply can be kept small.

  In the above example, the case where the semiconductor memory device is a DRAM has been described. However, the present invention is not limited to this, and if the semiconductor memory device has a switching element connected to a word line, the off-leakage current is reduced by the mechanism described above. It can be reduced and the access speed can be increased.

  The semiconductor memory device according to the present invention has an effect that the off-leak current can be easily suppressed even when the threshold voltage of the access transistor is low, and the access speed can be easily increased. It is useful as a semiconductor memory device such as a DRAM (dynamic random access memory).

1 is a circuit diagram showing a configuration of a DRAM 100 of Embodiment 1. FIG. 2 is a circuit diagram showing a specific configuration of a word driver 123. FIG. 3 is a timing chart showing changes in each signal. FIG. 10 is a circuit diagram illustrating a specific configuration of a word driver 423 according to the second embodiment. 3 is a timing chart showing changes in each signal.

Explanation of symbols

100 DRAM
DESCRIPTION OF SYMBOLS 101 Memory circuit 111 Memory cell array 112 Sense amplifier 113 Precharge equalization circuit 121 Row address buffer 122 Row decoder 123 Word driver 131 Column address buffer 132 Column decoder 133 Data I / O buffer 134 Read / write amplifier 141 Memory cell 141a Capacitor 141a 'Capacitor 141b access transistor 141b 'access transistor 142 word line 142' word line 143 bit line pair 143a bit line 143b inversion bit line 201 power supply circuit 311 level shifter circuit 312 PMOS transistor 313 NMOS transistor 314 NMOS transistor 316 AND circuit 317 NOT circuit 416 NOR circuit 423 Word driver X 0 selection signal

Claims (8)

Multiple word lines,
Multiple bit lines,
A semiconductor memory device having a plurality of access switching elements that are turned on when a power supply potential source is connected to a corresponding word line when selected,
2. A semiconductor memory device, wherein two types of power source potential sources are switched and connected to the unselected word line. The semiconductor memory device according to claim 1,
The potentials of the two types of power source potential sources are a first potential and a second potential between the first potential and the potential of the power source potential source at the time of selection.
Before the connection of the power supply potential source at the time of selection to the selected word line is started, the power supply potential source of the second potential is connected to the word line,
After the connection of the power supply potential source at the time of selection to the selected word line is started, the power supply potential source of the first potential is switched and connected to the unselected word line. A semiconductor memory device. The semiconductor memory device according to claim 2,
The access switching element is an N-type transistor and the first potential is lower than a second potential, or the access switching element is a P-type transistor and the first potential is a second potential A semiconductor memory device, wherein the potential is higher than the potential. The semiconductor memory device according to claim 3,
The semiconductor memory device, wherein the second potential is a ground potential, and an absolute value of a potential difference between the first potential and the second potential is lower than a threshold voltage of the access switching element. The semiconductor memory device according to claim 3,
A semiconductor memory device, wherein the power source potential source of the first potential is connected to the non-selected word line during a period in which an operation of amplifying a potential difference generated in the bit line is performed. 6. The semiconductor memory device according to claim 5, wherein
A plurality of first switching elements each connecting and disconnecting each word line and the power source potential source of the first potential;
A plurality of second switching elements each connecting and disconnecting each word line and the power source potential source of the second potential,
The first switching element is turned on during a period in which the corresponding word line is not selected and the amplification operation is performed,
2. The semiconductor memory device according to claim 1, wherein the second switching element is turned on during a period when the corresponding word line is not selected and the precharge operation for the bit line is performed. The semiconductor memory device according to claim 3,
A semiconductor memory device, wherein the power source potential source of the first potential is connected to the non-selected word line during a period when the precharge operation to the bit line is not performed. . 8. The semiconductor memory device according to claim 7, wherein
A plurality of first switching elements each connecting and disconnecting each word line and the power source potential source of the first potential;
A plurality of second switching elements each connecting and disconnecting each word line and the power source potential source of the second potential,
The first switching element is turned on during a period in which the corresponding word line is not selected and the precharge operation is not performed.
The semiconductor memory device, wherein the second switching element is in an ON state during a period when the corresponding word line is not selected and the precharge operation is performed.

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