JP2005217159A - Insulating gate semiconductor element and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an insulating gate semiconductor element capable of extending the lifetime of the hard breakdown. <P>SOLUTION: The insulating gate semiconductor element is provided with a gate insulation film 15 wherein the nitrogen concentration at a channel region side is higher than the nitrogen concentration at the side of a gate electrode 16, the nitrogen concentration at the side of the gate electrode 16 is higher than the nitrogen concentration in the middle, and a metal concentration at the channel region side and the side of the gate electrode 16 is respectively lower than the metal concentration in the middle. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to an insulated gate semiconductor device and a manufacturing method thereof.

  In recent years, MOS transistors have been miniaturized in accordance with higher performance and higher speed of LSI. Along with this, the gate insulating film of the MOS transistor is rapidly thinned, and a technique for forming an extremely thin silicon insulating film uniformly and with high reliability is required.

  In a MOS transistor, in a voltage range in which the gate voltage is less than 3.0 V, the life from the occurrence of soft breakdown (SBD) to hard breakdown (HBD) is abruptly increased. Therefore, when the power supply voltage is lowered due to the miniaturization of the element, the time until the SBD (pseudo breakdown) once reaches the HBD (complete breakdown) (hereinafter referred to as “complete breakdown”). It is known that the dielectric breakdown lifetime is increased) (for example, see Non-Patent Document 1).

Further, it is known that the SBD frequency is increased by performing high-temperature heat treatment in the manufacturing process of the MOS transistor (see, for example, Non-Patent Document 2). Furthermore, it is known that crystallization is suppressed by adding nitrogen atoms to the high dielectric gate insulating film (see, for example, Non-Patent Document 3).
K. Okada et al., “A Concept of Gate Oxide Lifetime Limited by“ B-mode ” "Stress Induced Leakage Currents in Direct Tunneling Regime" Symposium on VLSI Technology Digest of Technical Paper, 1999 p. 57-58 T. Yamaguchi et al., “Novel dielectric breakdown model of Hf-silicate with high temperature annealing” Reliability Physics Symposium proceedings ), 2003 p. 34-40 M. Koyama et al., “Effects of nitrogen in HfSiON gate dielectrics on the electrical and thermal characteristics” International Electron Device Conference Technology Digest (International Electron Devices Meeting Technical Digest), 2002 p. 849-852

  If SBD (pseudo breakdown) can be selectively caused, the complete dielectric breakdown life can be increased, and as a result, the lifetime of the element can be increased. However, whether the breakdown of the gate insulating film occurs becomes SBD or HBD depends on probability by chance. For this reason, it is difficult to selectively raise only the SBD, and it is difficult to extend the complete dielectric breakdown life.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an insulated gate semiconductor device capable of extending the complete dielectric breakdown lifetime and a method for manufacturing the same.

  In order to achieve the above object, the first feature of the present invention is that the nitrogen concentration on the channel region side is higher than the nitrogen concentration on the gate electrode side, the nitrogen concentration on the gate electrode side is higher than the nitrogen concentration on the center, and the channel The gist of the invention is that it is an insulated gate semiconductor device including a gate insulating film in which the metal concentration on the region side and the gate electrode side is lower than the metal concentration in the central portion.

  The second feature of the present invention is: (a) a step of depositing a first insulating layer on the upper surface of the semiconductor layer; and (b) a nitrogen concentration lower than that of the first insulating layer and a metal concentration on the upper surface of the first insulating layer. A step of depositing a second insulating layer having a high thickness; and (c) a third insulating layer having a higher nitrogen concentration than the first insulating layer and the second insulating layer and a lower metal concentration than the second insulating layer on the upper surface of the second insulating layer. The gist of the present invention is a method for manufacturing an insulated gate semiconductor device, which includes a step of depositing a layer and (d) a step of crystallizing the metal oxide of the second insulating layer by performing a heat treatment.

  ADVANTAGE OF THE INVENTION According to this invention, the insulated gate semiconductor element which can extend a complete dielectric breakdown lifetime, and its manufacturing method can be provided.

  In the following, embodiments of the present invention will be described. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and width of the component, the ratio of the thickness of each component, and the like are different from the actual ones. In addition, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

(Embodiment)
As shown in FIG. 1, the MIS type semiconductor element (MISFET) according to the embodiment of the present invention has a nitrogen (N) concentration on the channel region side higher than the N concentration on the gate electrode 16 side, and N on the gate electrode 16 side. A gate insulating film 15 having a concentration higher than the N concentration in the central portion and a metal concentration on the channel region side and the gate electrode 16 side lower than the metal concentration in the central portion is provided. The gate insulating film 15 has a three-layer structure as shown in FIG. 2, and includes a first insulating layer 15a on the channel region side, a second insulating layer 15b disposed on the upper surface of the first insulating layer 15a, and a second insulating layer. A third insulating layer 15c on the gate electrode 16 side disposed on the upper surface of the layer 15b is provided. The thickness of the first to third insulating layers 15a to 15c is, for example, about 0.5 to 3 nm.

  The first insulating layer 15a includes, for example, at least N atoms and silicon (Si) atoms. The second insulating layer 15b is, for example, a crystallized layer containing at least metal atoms and oxygen (O) atoms, and metal oxide crystal grains 1 made of metal atoms and O atoms are deposited. For example, the third insulating layer 15c contains at least N atoms and Si atoms. The gate insulating film 15 includes at least metal atoms, N atoms, and O atoms. As the metal atom, for example, a hafnium (Hf) atom is used. In addition to Hf atoms as metal atoms, for example, zirconium (Zr), aluminum (Al), lanthanum (La), cesium (Ce), praseodymium (Pr), rubidium (Ru), tantalum (Ta), gadolinium (Gd) Dysprosium (Dy), erbium (Er), thallium (Tm), ytterbium (Yb), lutetium (Lu), etc. can be used.

  In FIG. 2, the positions in the film thickness direction of the first insulating layer 15a, the second insulating layer 15b, and the third insulating layer 15c shown in FIG. 1 are shown from the left of the horizontal axis, and the N concentration distribution and the metal (Hf) are shown on the vertical axis. ) Show the concentration distribution. As shown in FIG. 2, regarding the N concentration distribution, the N concentration of the first insulating layer 15a is higher than the N concentration of the third insulating layer 15c, and the N concentration of the third insulating layer 15c is the N concentration of the second insulating layer 15b. taller than. On the other hand, regarding the metal concentration distribution, as shown in FIG. 2, the metal concentration of the second insulating layer 15b is higher than the metal concentration of the third insulating layer 15c, and the metal concentration of the third insulating layer 15c is the metal of the first insulating layer 15a. Higher than concentration.

  The MIS type semiconductor device shown in FIG. 1 includes a first conductivity type semiconductor layer 11, a second conductivity type first main electrode region 13 formed on the semiconductor layer 11, and a first conductivity type semiconductor layer 11 on the semiconductor layer 11. A p-type second main electrode region 14 formed apart from the first main electrode region 13 and an upper surface of the channel region of the semiconductor layer 11 sandwiched between the first main electrode region 13 and the second main electrode region 14 And the gate electrode 16 disposed on the upper surface of the gate insulating film 15. Here, the “first conductivity type” and the “second conductivity type” are opposite conductivity types. That is, if the first conductivity type is n-type, the second conductivity type is p-type. If the first conductivity type is p-type, the second conductivity type is n-type. In the embodiment, the first conductivity type is p-type and the second conductivity type is n-type. However, the first conductivity type may be n-type and the second conductivity type may be p-type.

An element isolation region 12 having a depth of about 0.6 μm is formed from the upper surface to the inside of the semiconductor layer 11 so as to sandwich the first main electrode region (source region) 13 and the second main electrode region (drain region) 14. ing. Side wall nitride films 17 a and 17 b such as a silicon nitride film (SiN film) are provided on the side surface of the gate electrode 16. An interlayer insulating film (SiO ₂ film) 18 is disposed so as to cover the upper surface of the semiconductor layer 11 and the upper surface of the gate electrode (poly Si layer) 16. A part of each of the source region 13 and the drain region 14 exposed through the opening provided in the interlayer insulating film 18 is connected to the source electrode 19 and the drain electrode 21, respectively.

  As the semiconductor layer 11, for example, an n-type Si substrate having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm can be used. The gate electrode 16 is made of, for example, a poly-Si layer having a thickness of 200 nm disposed on the upper surface of the gate insulating film 15. A metal layer 20 such as aluminum (Al) connected to the gate electrode 16 through the opening of the interlayer insulating film 18 is disposed on the upper surface of the gate electrode 16. The gate electrode 16 controls a current flowing between the source region 13 and the drain region 14.

  As shown in FIG. 2, the second insulating layer 15b has a lower N concentration and a higher metal concentration than the first insulating layer 15a and the third insulating layer 15c. Therefore, this metal oxide crystal grain 1 is used as an electrical defect and SBD is likely to occur. Here, as shown in FIG. 3, in the voltage range in which the gate voltage is less than 3.0 V, the life from the occurrence of SBD to the HBD is abruptly increased. For this reason, rather than causing HBD directly, once SBD is caused, the life until reaching HBD can be obtained, and the complete dielectric breakdown life can be extended. Therefore, according to the MIS type semiconductor device shown in FIG. 1, the dielectric breakdown of the gate insulating film 15 composed of the first to third insulating layers 15a to 15c can be intentionally kept at the SBD. Destruction life can be extended.

  In addition, since the first insulating layer 15a and the third insulating layer 15c have fewer metal (Hf) atoms than the second insulating layer 15b, relatively few defects are generated, and the interface with the semiconductor layer 11 and the gate electrode 16 The amount of decrease in carrier mobility at the interface is also small. Furthermore, since the N concentration in the first insulating layer 15a and the third insulating layer 15c is higher than that in the second insulating layer 15b, even if a metal (Hf) atom is included, an electrical phenomenon caused by the metal (Hf) atom is caused. The generation of defects can be suppressed. Therefore, generation of unnecessary defects in the first insulating layer 15a and the third insulating layer 15c can be suppressed. As a result, defects are not connected from the channel region side to the gate electrode 16 side of the gate insulating film 15 composed of the first to third insulating layers 15a to 15c, the gate leakage current can be suppressed, and the deterioration of the breakdown life is prevented. It becomes possible.

  Here, in order to suppress a decrease in carrier mobility at the interface between the channel region of the semiconductor layer 11 and the first insulating layer 15a, the Hf concentration of the third insulating layer 15c is set higher than the Hf concentration of the first insulating layer 15a. Thus, it is preferable that metal (Hf) atoms that reduce carrier mobility are introduced as far as possible from the channel region.

Further, when the N concentration of the first insulating layer 15a is higher than 1 × 10 ¹⁹ cm ⁻³ and the N concentration of the third insulating layer 15c is twice or more higher than the N concentration of the third insulating layer 15c, the frequency of SBD generation Is significantly higher. Accordingly, the N concentration of the first insulating layer 15a is preferably about 1 × 10 ¹⁹ to 10 ²¹ cm ^{−3, and} more preferably about 1 × 10 ²⁰ to 10 ²¹ cm ⁻³ . Further, the N concentration of the third insulating layer 15c is preferably at least twice as high as the N concentration of the third insulating layer 15c.

  As described above, according to the MIS type semiconductor device according to the embodiment of the present invention, the gate insulating film 15 composed of the first to third insulating layers 15a to 15c is provided, so that it is completely reliable and complete. It is possible to extend the fracture life.

  Next, a method for manufacturing the MIS type semiconductor element according to the embodiment of the present invention will be described with reference to FIGS.

  (A) First, as the semiconductor layer 11, for example, an n-type Si substrate having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm is prepared. Then, an element isolation region 12 having a depth of about 0.6 μm is formed in the depth direction from the upper surface of the semiconductor layer 11 by a shallow trench isolation (STI) method or the like, as shown in FIG.

(B) Next, for example, at room temperature to about 800 ° C. and about 0.1 mPa to 0.1 kPa, for example, in a mixed gas of N ₂ gas and O ₂ gas diluted with argon (Ar) gas, by sputtering or the like, As shown in FIG. 5, a first insulating layer 15x containing N atoms and Si atoms having a thickness of 0.5 to 3 nm, for example, is deposited on the upper surface of the semiconductor layer 11.

(C) Next, for example, at room temperature to about 800 ° C. and about 0.1 mPa to 0.1 kPa, for example, in a mixed gas of N ₂ gas and O ₂ gas diluted with Ar gas, but the first insulating layer 15a is formed. gas pressure or gas flow rate of the N ₂ gas at reduced criteria than condition, by sputtering or the like, O atoms and Hf of the top surface to a thickness of the first insulating layer 15x 0.5 to 3 nm, as shown in FIG. 6 A second insulating layer 15y containing atoms is deposited. Here, the second insulating layer 15y is deposited with a lower N concentration and a higher Hf concentration than the first insulating layer 15x.

(D) Next, the first insulating layer 15a is formed in a mixed gas of N ₂ gas and O ₂ gas diluted with Ar gas, for example, at room temperature to about 800 ° C. and about 0.1 mPa to 0.1 kPa. On the upper surface of the second insulating layer 15y as shown in FIG. 7 by sputtering or the like under a gas pressure or gas flow rate of N ₂ gas lower than the conditions and higher than the conditions for forming the second insulating layer 15b. A third insulating layer 15z containing Ni atoms and Si atoms having a thickness of 0.5 to 3 nm is deposited. Here, the third insulating layer 15z is deposited with a higher N concentration than the first insulating layer 15x and the second insulating layer 15y and a lower Hf concentration than the second insulating layer 15y.

  (E) Next, a metal film 16x having a film thickness of, for example, 100 to 300 nm is deposited on the upper surface of the third insulating layer 15z shown in FIG. 8 by low pressure chemical vapor deposition (RPCVD) at, for example, about 400 to 600 ° C. To do. Then, as shown in FIG. 8, a resist 23 is applied on the upper surface of the metal film 16x, and the resist 23 is patterned using a photolithography technique or the like. Subsequently, each of the metal film 16x, the third insulating layer 15z, the second insulating layer 15y, and the first insulating layer 15x is formed by, for example, reactive ion etching (RIE) using the patterned resist 23 as a mask. Parts are selectively removed. As a result, as shown in FIG. 9, the first to third insulating layers 15a to 15c and the gate electrode (poly Si layer) 16 are formed. Thereafter, the remaining resist 23 is removed using a registry mover or the like.

  (F) Next, an insulating film (SiN film) 17x having a film thickness of 100 to 300 nm, for example, is deposited on the upper surface of the semiconductor layer 11, as shown in FIG. . Then, a part of the SiN film 17x is selectively removed by etching back using a dry etching method. As a result, as shown in FIG. 11, sidewall nitride films 17 a and 17 b remain around the first to third insulating layers 15 a to 15 c and the gate electrode (poly Si layer) 16.

(G) When the MIS type semiconductor element shown in FIG. 1 is a part of an integrated circuit, etc., the upper surface of the semiconductor layer 11 and the gate electrode as shown in FIG. A resist 24 is applied to the upper surface of the (poly-Si layer) 16, and the resist 24 is patterned as shown in FIG. Subsequently, using the patterned resist 24 as a mask, boron difluoride (BF ₂ ) is ion-implanted under conditions such as an acceleration voltage of 0.5 to 10 kV and a dose of 10 ¹⁴ to 10 ¹⁶ cm ⁻² . The remaining resist 24 is removed using a registry mover or the like. When the MIS type semiconductor device shown in FIG. 1 is manufactured alone, the semiconductor layer 11 and the gate electrode (poly Si layer) are formed in a self-aligned manner after the sidewall nitride films 17a and 17b shown in FIG. 11 are formed. Alternatively, ions may be directly implanted into the upper portion of 16.

  (H) Thereafter, heat treatment is performed in an inert gas atmosphere at, for example, about 800 to 1100 ° C., for example, for 1 to 100 seconds to activate the introduced boron (B) atoms. As a result, a source region 13 and a drain region 14 are formed as shown in FIG. At the same time, the second insulating layer 15b is crystallized by heat treatment to precipitate the metal oxide crystal grains 1, and defects are introduced into the bulk at a high density.

(I) Further, as shown in FIG. 15, an interlayer insulating film (SiO ₂ film) 18 having a thickness of, for example, 100 to 300 nm is formed on the upper surface of the semiconductor layer 11 and the upper surface of the gate electrode (poly Si layer) 16 by the CVD method. accumulate. Then, as shown in FIG. 16, a resist 25 is applied on the SiO ₂ film 18, and the resist 25 is patterned using a photolithography technique or the like. Subsequently, using the patterned resist 25 as a mask, a part of the SiO ₂ film 18 is selectively removed by RIE or the like to open a contact hole as shown in FIG. The remaining resist 25 is removed using a registry mover or the like.

(N) Next, as shown in FIG. 18, on the semiconductor layer 11, the SiO ₂ film 18, and the gate electrode (poly-Si layer) 16, for example, Al containing 0.5% each of Si and copper (Cu). A metal film 19x having a thickness of 200 to 800 nm is deposited. Then, as shown in FIG. 19, a resist 26 is applied on the upper surface of the metal film 19x, and the resist 26 is patterned using a photolithography technique or the like. Subsequently, using the patterned resist 26 as a mask, a part of the metal film 19x is selectively removed by the RIE method or the like to form the source electrode 19, the metal layer 20, and the drain electrode 21, as shown in FIG. To do. Thereafter, the remaining resist 26 is removed using a registry mover or the like. Finally, heat treatment is performed in an N ₂ atmosphere containing hydrogen (H ₂ ), for example, at about 200 to 500 ° C. for 1 to 120 minutes, for example.

  According to the MIS type semiconductor device manufacturing method described above, the MIS type semiconductor device shown in FIG. 1 can be realized. When structural control for suppressing crystallization peculiar to the high dielectric gate insulating film is not performed, for example, the source region 13 and the drain region 14 are utilized by utilizing the feature that crystallization is easily caused by high-temperature heat treatment. Since the central portion (second insulating layer) 15b of the gate insulating film 15 is crystallized by the activation heat treatment, an insulated gate semiconductor element capable of keeping the dielectric breakdown of the gate insulating film 15 in the SBD mode can be manufactured.

  In addition, although defects that are electrically vulnerable to stress are formed in the second insulating layer 15b, crystallization occurs because N atoms are introduced into the first insulating layer 15a and the third insulating layer 15c at a high concentration. It can be suppressed and it is not necessary to introduce many defects unnecessarily. Therefore, it is possible to manufacture an insulated gate semiconductor device that can extend the complete dielectric breakdown lifetime of the gate insulating film 15 with high reliability.

Next, the evaluation result regarding the improvement of the SBD generation frequency will be described. First, the N introduction method was changed at 950 ° C., and a gate insulating film (SiON film) was formed to a thickness of 6.0 nm on the semiconductor layer (Si substrate). Then, the N concentration on the gate electrode 16 side of the SiON film and the N concentration on the channel region side of the semiconductor layer 11 were evaluated using a mass spectrometer. As shown in FIG. 21, in the SiON film formed using N ₂ O gas, the N concentration on the channel region side is slightly higher than the N concentration on the gate electrode 16 side. It can be seen that the amount of N atoms introduced on either side is less than 10 ¹⁹ cm ⁻³ . In addition, in the SiON film formed using NO gas, N atoms of about 10 ¹⁹ to 10 ²⁰ cm ⁻³ are introduced into the gate electrode 16 side, but the N atom amount on the channel region side is less than 10 ¹⁹ cm ⁻³ . It can be seen that there are few. On the other hand, in the SiON film formed using ammonia (NH ₃ ) gas, it can be seen that N atoms can be introduced at a high concentration of about 10 ²⁰ to 10 ²¹ cm ⁻³ on both the gate electrode 16 side and the channel region side. .

Furthermore, the SBD generation frequency of the MOS type capacitor in which the SiON film was formed using each of the above-described N introduction methods was evaluated. As shown in FIG. 22, it can be seen that when N ₂ O gas and NO gas are used, HBD occurs in a MOS capacitor of 80% or more. On the other hand, in the MIS type capacitor in which N atoms are introduced at a high concentration of about 10 ²⁰ to 10 ²¹ cm ⁻³ on the channel region side and the gate electrode 16 side of the SiON film using NH ₃ gas, the frequency exceeds 80%. It turns out that SBD occurs. Therefore, in order to obtain a high generation frequency of SBD, it is preferable to introduce N atoms at a high concentration into the channel region side and the gate electrode 16 side using NH ₃ gas.

(Modification)
As shown in FIG. 23, the insulated gate semiconductor device according to the modification of the embodiment of the present invention has metal films 16 x, 19 x, and 16 n on the source region 13, the drain region 14, and the gate electrode (poly Si layer) 16. The difference from the insulated gate semiconductor device shown in FIG. 1 is that 21x is provided. As the metal films 16x, 19x, and 21x, thin films such as tungsten (W), nickel (Ni), and cobalt (Co) can be employed. Other configurations are substantially the same as those of the insulated gate semiconductor device shown in FIG.

  According to the insulated gate semiconductor device shown in FIG. 23, the dielectric breakdown of the gate insulating film 15 can be intentionally kept at the SBD as in the insulated gate semiconductor device shown in FIG. Lifespan can be extended.

  In the method for manufacturing an insulated gate semiconductor device according to the modification of the embodiment of the present invention, the metal films 16x, 19x, and 21x are formed using a salicide process after the procedure shown in FIG. The other procedures are substantially the same as the procedures shown in FIGS.

(Other embodiments)
Although the present invention has been described with reference to the embodiments, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operational techniques will be apparent to those skilled in the art. For example, FIG. 1 shows a gate insulating film 15 having a three-layer structure composed of first to third insulating layers 15a to 15c. If the gate insulating film 15 has a profile of N concentration and metal concentration as shown in FIG. Is not particularly limited, and may be a gate insulating film having a structure of four or more layers.

  2, the metal (Hf) concentration of the third insulating layer 15c illustrated in FIG. 1 is higher than the metal (Hf) concentration of the first insulating layer 15a. Any structure that does not lead to electrical defects from the channel region side to the gate electrode 16 side may be used. Therefore, the metal (Hf) concentration of the third insulating layer 15c may be lower than the metal (Hf) concentration of the first insulating layer 15a. .

  In the method for manufacturing an insulated gate semiconductor device according to the embodiment, a part of the first insulating layer 15a to the third insulating layer 15c shown in the drawing is selectively removed by anisotropic dry etching such as RIE. However, isotropic etching using a solution may be used. As described above, the method for manufacturing an insulated gate semiconductor device according to the above-described embodiment is an example, and the insulated gate semiconductor device according to the embodiment can be realized by various procedures.

  Further, although the MISFET is shown in FIG. 1 as the insulated gate semiconductor device according to the embodiment, the insulated gate bipolar transistor (IGBT), the insulated gate static induction transistor (IGSIT), and the MOS control thyristor are also shown. Of course, it can be expanded to. For example, in the case of an IGBT, each of the first main electrode region 13 and the second main electrode region 14 shown in FIG. 1 is a semiconductor region that serves as either the main electrode of the emitter region or the collector region.

  Furthermore, the structure of the gate insulating film 15 shown in FIG. 1 can be easily applied to, for example, a random noise generator (RNG). As described above, the present invention includes various embodiments and the like that are not described herein, and the technical scope of the present invention is determined by the invention-specifying matters according to the scope of claims reasonable from the above description. It is only determined.

It is sectional drawing which shows the structure of the insulated gate semiconductor element which concerns on embodiment of this invention. It is a graph of the metal element and nitrogen element distribution in the gate insulating film which concerns on embodiment of this invention. It is a graph which shows the relationship between a gate voltage and lifetime from a pseudo breakdown (SBD) to a complete breakdown (HBD). It is process sectional drawing (the 1) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 2) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 3) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 4) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 5) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 6) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 7) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 8) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 9) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 10) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 11) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 12) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 13) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 14) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 15) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 16) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is process sectional drawing (the 17) of the manufacturing method of the insulated gate semiconductor element which concerns on embodiment of this invention. It is a graph which shows the relationship of the N density | concentration of the interface of a gate insulating film and a gate electrode at the time of changing the formation method of a gate insulating film (SiON film), and the interface of a gate insulating film and a semiconductor layer. It is a graph which shows the relationship of the pseudo destruction (SBD) production | generation frequency at the time of changing the formation method of a gate insulating film (SiON film | membrane). It is sectional drawing which shows the structure of the insulated gate semiconductor element which concerns on the modification of embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Metal oxide crystal grain 11 ... Semiconductor layer 12 ... Element isolation region 13 ... 1st main electrode region (source region)
14: Second main electrode region (drain region)
DESCRIPTION OF SYMBOLS 15 ... Gate insulating film 15a ... 1st insulating layer 15b ... 2nd insulating layer 15c ... 3rd insulating layer 15x ... 1st insulating layer 15y ... 2nd insulating layer 15z ... 3rd insulating layer 16 ... Gate electrode (poly Si layer)
16x, 19x, 21x ... metal film 17x ... insulating film (SiN film)
17a, 17b ... sidewall nitride film 18 ... interlayer insulating film (silicon oxide film)
DESCRIPTION OF SYMBOLS 19 ... Source electrode 20 ... Metal layer 21 ... Drain electrode 23-26 ... Resist

Claims (5)

The nitrogen concentration on the channel region side is higher than the nitrogen concentration on the gate electrode side, the nitrogen concentration on the gate electrode side is higher than the nitrogen concentration on the central portion, and the metal concentrations on the channel region side and the gate electrode side are respectively the central portion An insulated gate semiconductor device comprising a gate insulating film having a lower metal concentration than the above.
2. The insulated gate semiconductor device according to claim 1, wherein the gate insulating film has a metal concentration on the gate electrode side higher than a metal concentration on the channel region side.
3. The insulated gate semiconductor device according to claim 1, wherein the gate insulating film has a nitrogen concentration on the channel region side higher than twice the nitrogen concentration on the gate electrode side.
4. The insulated gate semiconductor device according to claim 1, wherein the gate insulating film has a nitrogen concentration of 10 ²⁰ to 10 ²¹ cm ⁻³ on the channel region side. 5.
Depositing a first insulating layer on the upper surface of the semiconductor layer;
Depositing a second insulating layer having a lower nitrogen concentration than the first insulating layer and a higher metal concentration than the first insulating layer on an upper surface of the first insulating layer;
Depositing a third insulating layer having a higher nitrogen concentration than the first insulating layer and the second insulating layer and a lower metal concentration than the second insulating layer on the upper surface of the second insulating layer;
And a step of crystallizing the metal oxide of the second insulating layer by performing a heat treatment.

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