JP2005210488A - Data-decoding device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem in which wasteful blank data output processing, are carried out and print processing speed is decreasing. <P>SOLUTION: A data decoding device comprises a data input means of inputting compressed data, a decoding means of interpreting and decoding the inputted compressed data, a data output means of outputting the data, a counter which counts pieces of output data, an output data byte number setting means for setting the number of bytes of the output data, a data number comparing means of comparing the counted value of the counter with a value set in the output data byte number setting means, an added data specifying means of specifying added data outputted, before and after decoding, and an added data generating means of generating the added data. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data decoding apparatus for decoding compressed data.

  Conventionally, when print data is created by a host computer and transmitted to a printer, the print data is generated in units of rectangular areas including graphic objects. The rectangular area is from the left end to the right end of the printable range of the printing paper. This will be described with reference to FIG.

  In FIG. 5, reference numeral 501 represents a print sheet, and 502 and 503 are rectangular areas including print data. For example, as shown in 502, a rectangular area including a certain graphic object is used as one unit of print data, and print data to be sent to the printer is generated by the host computer and sent to the printer. 502 includes graphic objects such as triangles, quadrangles, and circles, and 503 includes elliptical graphic objects and character data. The print data transmitted to the printer is multi-valued color data (RGB each color 8 bits). The printer interprets the received print data, performs color space conversion, and then uses the dither method or error diffusion method to convert the multivalued color data into binary data that becomes on / off data for each color of CMYK or CMYKcm ink. Generate color data.

  Various data compression methods have been used to reduce the amount of print data transmitted from the host computer to the printer. One of the data compression methods is the pack bits method. In addition to reducing the amount of print data by compressing data using the Packbits method, pay attention to the rectangular area that is the unit for generating print data, and the left and right margins of the graphic object are the targets of the print data A method has been adopted in which the amount of print data is reduced by excluding it from being included in the print data.

  According to this method, the host computer performs packbits compression using a graphic object in the rectangular area 502 as target data, adds a termination code to the end of the compressed data, and sends the data to the printer. The data from the left end to the front and from the right end to the back is generated and passed to the printer engine. When the color space of the data transmitted from the host computer is RGB, “1” is generated, and when the color space is CMYK or CMYKcm, “0” (data representing white) is generated and passed to the printer engine.

  The processing described above will be described with reference to the drawings. FIG. 6 is a detailed representation of a rectangular area including a graphic object such as the rectangular area 502 shown in FIG. 5 in line units, and shows an example in which the rectangular area is composed of n lines. A hatched portion 602 indicates a portion where a graphic object exists, and 601 and 603 indicate blank portions where no graphic object exists. Line 3 indicates a case where a graphic object exists only at the right end of the rectangular area. Line 4 indicates a case where a graphic object exists only at the left end of the rectangular area. Line 5 shows a case where a graphic object exists from the left end to the right end of the rectangular area and there is no blank portion.

  The printer driver operating on the host computer processes the rectangular area shown in FIG. 6 line by line. First, pay attention to the blank portion 601 of the line 1, count the number of data bytes in the blank portion, add it to the beginning of the print data as the top address offset of the graphic object, and then pay attention to the hatched portion 602 to display the graphic object data. Is compressed using the Packbits method, and an end code is added to the end of the compressed data to obtain Line 1 print data. Next, the number of data bytes in the blank portion at the left end of Line 2 is counted, added to the print data as a graphic data head address offset, and the hatched portion is compressed using the Packbits method, and finally a termination code is added. After repeating this process up to Line n, the print data of the rectangular area is transmitted to the printer.

  In the printer, after extracting the graphic data start address offset of the line to be processed from the received print data, the end code is searched for, the compressed data for each line is cut out, and the pack bits decoding process is performed for each line. The line-by-line decoding process is performed according to the procedure shown in FIG. First, processing for outputting white data to a memory area for storing decoded print data is performed (S1101). As described above, this is performed to fill the data representing “white” from the left end of the graphic object to the front and from the right end of the graphic object to the back. Reference numeral 701 in FIG. 7 denotes a memory area corresponding to a rectangular area in which white data is written. White data output processing is performed from the top address 702 of the memory area 701.

  Next, data obtained by decoding the data compressed by the Packbits method is written into the memory. This is a hatched portion 904 shown in FIG. Writing is started from an address 903 obtained by adding a graphic data start address offset to the start address 902, and writing is ended at an address 905 where the decoded data ends (S1102 in FIG. 11). When the data 904 decoded in S1102 and the remaining areas 901 and 906 in which the white data is written in S1101 are combined, print data for one line of a rectangular area is obtained.

  After the process shown in FIG. 11 is repeated for the number of lines in the rectangular area, the print data expanded on the memory is transferred to the image processing block, and the print data of FIG. 9 is transferred to the printer engine in the image processing block. Convert to

  As another conventional example, Patent Document 1 describes a method in which a special code and subsequent data bytes are continuously added and expanded from the data portion of interest toward the end of the subsequent band.

Japanese Patent Laid-Open No. 10-287003

  In the processing according to the conventional example as described above, since the result of decoding the data compressed by the Packbits method is written in the memory area where the white data output processing has been performed, a rectangular shape as shown in Line2, Line4, and Line5 in FIG. When there is a graphic object in most or all of the area, most or all of the area where the white data output processing has been performed is rewritten with the decoding result, so that unnecessary white data output processing is performed, resulting in a decrease in printing processing speed. It was one of the factors.

  In order to increase the efficiency of such white data output, it is only necessary to write white data only in necessary portions other than graphic data, instead of writing white data in the entire width from the left end to the right end of the rectangular area.

  The method described in Patent Document 1 is a method in which a special code and subsequent data bytes are continuously added and expanded from the data portion of interest toward the end of the subsequent band. Although it can be one solution of the white data output process on the right side, it cannot be applied to the white data output on the left side from the left end of the graphic data.

  The present invention has been made in view of the above-described conventional problems, and is configured such that a pack bit decoder installed in a printer adds white data to the left and right of the graphic data as a decoding result and writes the data to the memory, and decodes the compressed data. It is an object of the present invention to provide a data decoding apparatus that can efficiently generate print data including not only white data but also white data.

  In order to solve such a problem, a data decoding apparatus according to the present invention is a data decoding apparatus for decoding compressed data, a data input means for inputting compressed data, and input compressed data Decoding means for interpreting and decoding, data output means for outputting data, a counter for counting the number of output data, an output data byte number setting means for setting the number of output data bytes, and a count value of the counter Data number comparing means for comparing the output data byte number setting means with the value set in the output data byte number setting means, additional data specifying means for specifying additional data to be output before and after decoding, and additional data for generating the additional data And a data generation means.

  Conventionally, the data compressed by the Packbits method is overwritten as the decoded data in the memory area where the white data was written out, so unnecessary white data output processing is performed on the overwritten portion, resulting in a decrease in printing processing speed. It was one of the factors inviting.

  According to the present invention, the Packbits decoder installed in the printer writes white data from the left end of the rectangular area to the left side of the graphic data, then writes the decoded data of the graphic data, and finally white data from the right end to the right side of the graphic data. Since one line of print data is processed while switching between white data output and decode data output, the unnecessary white data output process overwritten with the decode data, which has been a problem in the past, is unnecessary. There is an effect that it is possible to perform efficient print data decoding processing.

<Embodiment 1>
Embodiment 1 of the present invention will be described below with reference to the drawings.

  FIG. 3 is a schematic block diagram of a printer system in which the present invention is implemented.

  A printer main body 301 is connected to the host PC 304. The host PC is connected via a network (wired LAN, wireless LAN), USB, IEEE 1394, or the like. The printer 301 includes a controller 302 and a printer engine 303. The controller interprets the print data transmitted from the host PC 304 and the interface function with the host PC 304, decodes the compressed print data, performs image processing, converts it into binary data, and passes it to the printer engine. The printer engine 303 receives the binarized print data from the controller 302, and in the case of an ink jet printer, performs print head scan control, ink discharge control, paper feed control, and the like to perform printing.

  FIG. 4 is a block diagram of the controller.

  The controller 401 is connected to the host PC 415 via the USB interface, the host PC 418 via the IEEE 1394 interface, and a plurality of host PCs via the LAN interface, and further connected to the printer engine 413 via the engine interface. .

  The controller 401 includes a controller chip 402, a ROM 405, a RAM 407, an operation panel 409, an IEEE 1394 interface 417, a LAN controller 419, and an expansion interface 420. The controller chip 402, the IEEE 1394 interface 417, the USB interface 414, and the expansion interface 420 provide an expansion bus. Connected through.

  The controller chip 402 is a so-called SOC (System On a Chip), and includes a CPU 403, a ROM controller 404, a RAM controller 406, an operation panel interface 408, a bus interface 416, a pack bits decoder 410, an image data processing block 411, a USB interface 414, An LSI composed of an engine interface 412 and connected to each other by an internal bus.

  The CPU 403 operates according to a program stored in the ROM 405, and communicates with the host PC and printer engine and controls each unit through various interfaces. The ROM controller 404 performs an interface with the connected ROM 405. The RAM controller 406 interfaces with the connected RAM 407, and inputs / outputs data to / from the RAM in accordance with requests from the CPU 403 and other blocks while controlling the RAM access timing. An operation panel interface 408 interfaces with an operation panel 409 equipped with operation keys, LEDs, and an LCD, transmits operation key inputs from the user to the CPU 403, and the display of the LEDs and LCD is controlled by commands from the CPU 403. The bus interface 416 is a block that controls the expansion bus, and performs communication control with each controller connected to the expansion bus.

  The pack bits decoder 410 reads print data compressed by the pack bits method transmitted from the host PC from the RAM 407, decodes it, and writes it back to the RAM (stores it). The image data processing block 411 is a block that reads out image data transmitted from the host PC as print data from the RAM 407, converts it into dot data of each ink color, and writes back (stores) it in the RAM 407. The engine interface 412 performs control for reading out dot data of each ink color from the RAM 407 and transmitting (outputting) the data to the printer engine 413.

  Print data transmitted from the host PC is input from each interface of the controller. Print data input via the IEEE 1394 interface 417 or the LAN controller 419 is written to the RAM 417 via the expansion bus via the bus interface 416 of the controller chip 402 and under the control of the RAM controller 406. The USB interface 414 is built in the controller chip 402, and print data input from the host PC 415 is similarly written to the RAM 407.

  The print data written in the RAM 407 is transferred to the Packbits decoder 410 after being decoded by the CPU 403 and the communication protocol is decoded. The decoded print data is transferred to the image data processing block 411, converted into dot data of each ink color, and then transmitted to the printer engine 413 through the engine interface 412 for printing.

  FIG. 2 is an internal block diagram of the pack bits decoder 410 shown in FIG. The pack bits decoder 410 is denoted by 201 in the figure, and comprises an internal bus interface block 202, a pack bits decoder block 204, and a register block 203. The register block 203 is connected to the internal interface block 202 and the pack bits decoder 204. The information set in the register is transmitted to each block.

  The register block 203 holds various setting information such as a DMA source address, a DMA destination address, a read data length, an area length, a graphic data head address offset, and an operation mode set by the CPU 403 in an internal register.

  The internal bus interface block 202 is connected to the internal bus of the controller chip 401, and has a DMA controller function for accessing the RAM 407 as a bus master on the internal bus. It operates in accordance with various setting information of the register block 203 and has a function of generating and outputting white data (00H or FFH byte data). Data sequentially read from the memory area having the DMA source address as the head address is transferred to the Packbits decoder block 204, and the decoded data received from the Packbits decoder block 204 is an address obtained by adding the DMA destination address and the graphic data head address offset. Sequentially write to the memory area as the start address.

  According to the setting of the register block 203, white data is output before and after the start of pack bits decoding. Also included in the DMA controller function are an address counter, input data byte number counter, output data byte number counter, and counter value comparator (not shown).

  The pack bits decoder block 204 interprets compressed data compressed according to the pack bits method and performs pack bits decoding. Interpret the command byte, determine the copy operation or move operation, and output the data according to the command. Decoding is started from the beginning of the compressed data input from the internal bus interface block 202, and the decoding operation is terminated when the end code indicating the end of the compressed data is received.

  Next, the operation of the Packbits decoder will be described with reference to FIG. 1 and FIGS. FIGS. 8 to 10 schematically show memory areas in which print data is written, and are divided in the order in which the data is written. However, since the same areas are shown, the addresses and areas shown in FIG. The thing with the same end of the number which points to represents the same thing in each figure.

  First, the CPU 403 performs various settings for pack bits decoding processing on the register block 203. As the DMA source address, an address on the RAM 407 indicating the head of each line of the print data compressed in pack bits is set. An address (address 802 in FIG. 8) on the RAM 407 indicating the head of each line of the print data is set as the DMA destination address.

  Further, when there is a blank portion on the left side of the graphic data as in Line 1 and Line 2 in FIG. 6, the graphic data head address offset added to the print data sent from the host PC is cut out and set. In this case, the start address of the memory area in which the data obtained by decoding the packbits-compressed data is written becomes the address 803 obtained by adding the graphic data start address offset to the DMA destination address 802. The read data length sets the length of the data compressed by Packbits. The area length is the length of the rectangular area of the print data (the width of the rectangular area 502 in FIG. 5. The printable range width of the printing paper. In FIG. 8, the value is obtained by subtracting the address 802 from the address 807. ) Is set. It is set which byte data of 00H or FFH is output as white data. Whether 00H or FFH data is output depends on whether the received print data is RGB or CMYK color space data. FFH is set for RGB, and 00H is set for CMYK. After these settings, the DMA operation of the pack bits decoder 201 is started.

  FIG. 1 shows the processing after DMA activation.

  In S101, it is determined whether or not to perform white data output processing on the left side of the graphic data. If the value of the graphic data start address offset is “0”, the white data output process is not performed and the process proceeds to S104.

  In S102, white data output processing on the left side of the graphic data is performed. According to the setting of the register block 203, either 00H or FFH byte data is written. Output of white data is started from the DMA destination address 802. After white data is output, the address counter is incremented.

  In S103, the end of the white data output process on the left side of the graphic data is determined. When the value of the address counter (output address) becomes equal to the DMA destination address 802 and the address 803 obtained by adding the graphic data head address offset, the process proceeds to the next process S104, otherwise returns to S102 and repeats the white data output. When the white data output process on the left side of the graphic data is completed, the white data is output to the area 801 in FIG.

  In S104, pack bits decoding processing is performed. The internal bus interface block 202 reads the compressed data from the DMA source address, passes it to the Packbits decoder block 204, receives the decoded data output from the Packbits decoder block, and adds the DMA destination address and the graphic data head address offset 803 Start writing from. The decoding process is repeated for the compressed data, and ends when there is no more compressed data. In FIG. 9, the decoding data 904 starts to be written from the address 903 and the decoding process ends at the address 905. When the output from the decoder is completed, the print data of the hatched portion 904 in FIG. 9 is generated.

  In S105, it is determined whether or not to perform white data output processing on the right side of the graphic data. In the internal bus interface block 202, the output data byte counter and the area length set in the register block 203 are compared. If the area length is longer, the process proceeds to S106, and the right end white data output process is performed. In the example of FIG. 9, since the decode data 904 has not reached the area length (the area has not reached the right end address 907), white data writing processing is next performed on the right side of the graphic data. When the decode data is written to the right end of the area length as in Line 3 of FIG. 6, the right end white data output process is not performed and this process ends.

  In S106, white data output processing on the right side of the graphic data is performed. According to the setting of the register block 203, either 00H or FFH byte data is written. Output of white data is started from an address 1005 in FIG. After white data is output, the address counter is incremented.

  In S107, the end of the white data output process on the right side of the graphic data is determined. Until the output address value becomes equal to the address 1007 obtained by adding the area length to the DMA destination address 1002, the process returns to S106, and the white data output is repeated. When the output address value becomes equal to the address 1007, the white data output process is terminated. When the white data output process on the right side of the graphic data is completed, the white data is output to the area 1006 in FIG. 10, and the print data output process for one line from addresses 1002 to 1007 is completed.

  By repeating this process a number of times constituting the rectangular area, print data for the rectangular area can be generated. The generated print data is converted into binary data for the printer engine in the image data processing block 411, sent to the printer engine 413 via the engine interface 412, and printed. When the printer engine 413 is an inkjet system using a recording head (a monochrome recording head that discharges black ink, a color recording head that discharges cyan ink, or the like), the printer engine 413 corresponds to the white data (00H). No ink is ejected from the nozzles.

  As described above, in this embodiment, the Packbits decoder adds white data from the left end to the left side and the right end to the right side of the graphic data in the rectangular area and writes the decoding result to the memory. The unnecessary white data output process becomes unnecessary, and the print data decoding process can be made more efficient.

<Embodiment 2>
In the first embodiment, the output address counter, the left end white data output determination logic, the output data byte number counter, the right end white data output determination logic, and the white data generation unit are mounted on the internal bus interface block 202. The left end white data output determination logic, the output data byte count counter, the right end white data output determination logic, and the white data generation unit are mounted on the pack bits decoder block 204, and the output address counter value is referred to from the internal bus interface block 202. Even so, it can be operated in the same manner as in the first embodiment.

  In the present invention, the Packbits method has been described as a method of being compressed by the host PC. However, the present invention is not limited to the Packbits method, and other compression methods that can compress one line of print data in units. If a decoder having a corresponding decoding function is mounted on the controller chip 402 as the decoder block 204, the same operation can be performed.

  The present invention is applicable to a data decoding apparatus that decodes compressed data.

It is a flowchart which shows the processing operation of the data decoding apparatus in Embodiment 1 of this invention. It is a block diagram which shows the internal structure of the data decoding apparatus in Embodiment 1 of this invention. 1 is a block diagram illustrating a configuration of a printer system according to the present invention. FIG. 2 is a block diagram illustrating a configuration of a printer controller according to the present invention. It is a figure which shows the print data which this invention makes object. It is a figure which shows the detail in the rectangular area | region of the print data which this invention makes object. FIG. 6 is a diagram illustrating a state in which white data is written in a memory area corresponding to a rectangular area of print data targeted by the present invention. It is a figure which shows the state which output white data to the left side of figure data from the left end of the memory area corresponding to the rectangular area of the print data which this invention makes object. It is a figure which shows the state which output the decoded data to the memory area corresponding to the rectangular area of the print data which this invention makes object. FIG. 6 is a diagram illustrating a state in which white data is output from the right end to the right side of graphic data in a memory area corresponding to a rectangular area of print data targeted by the present invention. It is a flowchart which shows the processing operation | movement of the data decoding in a prior art example.

Explanation of symbols

S101 Processing for determining whether left-end white data is output S102 Left-end white data output processing S103 Processing for determining end of left-end white data output processing S104 Packbits decoding processing S105 Processing for determining whether right-end white data is output S106 Right-end white data output process S107 Process for determining the end of the right-end white data output process

Claims (5)

A data decoding device for decoding compressed data, comprising:
A data input means for inputting compressed data; a decoding means for interpreting and decoding the input compressed data; a data output means for outputting data; a counter for counting the number of output data; and the number of output data bytes. Output data byte number setting means to be set, data number comparison means for comparing the count value of the counter with the value set in the output data byte number setting means, and additional data to be output before decoding and after decoding ends A data decoding apparatus comprising: additional data specifying means for specifying; and additional data generating means for generating the additional data.   The data output means includes an output address setting means for setting an output address, an address offset setting means for setting an offset with respect to the address set in the output address setting means, and an output address value set in the output address setting means. Address addition means for adding the address offset value set in the address offset setting means, output address generation means for counting the output address value to generate an output address, addition result of the address addition means and output address value Additional data generated by the additional data generating means according to the setting of the additional data designating means according to the comparison result by the data number comparing means and the comparison result by the address comparing means. Processing to generate and output the deco Data decoding apparatus according to claim 1, characterized in that it comprises a control means for controlling switching between the processing for outputting the decoded data compressed data using a draw means.   The additional data generation means can generate '0' or '1' data, and the additional data designation means selects and designates either '0' or '1' as additional data. The data decoding apparatus according to claim 1, wherein:   3. The data decoding according to claim 1, wherein the data input means and the data output means further perform DMA (Direct Memory Access), read compressed data, and output decoded data and additional data. Device.   5. The data decoding apparatus according to claim 4, wherein the decoding means is decoding means for decoding data compressed by a Packbits compression method.

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