JP2005208837A5 - - Google Patents
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- Publication number
- JP2005208837A5 JP2005208837A5 JP2004013387A JP2004013387A JP2005208837A5 JP 2005208837 A5 JP2005208837 A5 JP 2005208837A5 JP 2004013387 A JP2004013387 A JP 2004013387A JP 2004013387 A JP2004013387 A JP 2004013387A JP 2005208837 A5 JP2005208837 A5 JP 2005208837A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004013387A JP2005208837A (en) | 2004-01-21 | 2004-01-21 | Layout verification device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004013387A JP2005208837A (en) | 2004-01-21 | 2004-01-21 | Layout verification device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2005208837A JP2005208837A (en) | 2005-08-04 |
| JP2005208837A5 true JP2005208837A5 (en) | 2006-09-07 |
Family
ID=34899463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004013387A Pending JP2005208837A (en) | 2004-01-21 | 2004-01-21 | Layout verification device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2005208837A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008009964A (en) * | 2006-05-31 | 2008-01-17 | Toshiba Corp | Layout making equipment and method of making layout of semiconductor integrated circuit |
| JP2008097541A (en) * | 2006-10-16 | 2008-04-24 | Renesas Technology Corp | Layout verification method and layout verification device |
| JP4843583B2 (en) * | 2007-09-10 | 2011-12-21 | 株式会社東芝 | Information processing apparatus, power system tree creation method and program |
| JP4819074B2 (en) * | 2008-02-18 | 2011-11-16 | ルネサスエレクトロニクス株式会社 | Layout verification apparatus and layout verification method |
| JP2010211315A (en) | 2009-03-06 | 2010-09-24 | Fujitsu Semiconductor Ltd | Layout verification method and layout verification device |
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2004
- 2004-01-21 JP JP2004013387A patent/JP2005208837A/en active Pending