JP2005208634A - Display device and drive methods for system and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gate line drive method in which electric power consumption is reduced and the occurrence of flicker is prevented. <P>SOLUTION: Gate lines are made into a first block as first, third and fifth lines are driven with a positive polarity in an Nth frame. Next, second, fourth and sixth lines are driven with a negative polarity to form a second block. The gate line region of the first block is overlapped with the gate line region of the second block. All the gate lines are allocated at block units by such segments. The contiguous blocks have the opposite polarities and the polarities are inverted in the one block. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a display device, and more particularly to a driver that drives a gate line of the display device.

  In order to minimize the space occupied by the display device, an LCD display device, a plasma display panel (PDP), and an EL (electro-lumination) display are used instead of the CRT (cathode-ray tube) display device which has been mainly used conventionally. Various flat panel display devices have been developed, such as devices. In particular, in the case of LCD display devices, liquid crystal technology has been developed because the optical properties of the liquid crystal material can be controlled in response to changes in the electric field applied to the display device.

  Liquid crystal display devices (hereinafter referred to as LCDs) and panels are mainly based on thin film transistor (hereinafter TFT) technology. Using such a technique and a low temperature process, various sizes of high quality image display devices can be manufactured. As will be appreciated by those skilled in the art, a conventional LCD device includes a transparent substrate (eg, glass) on which TFTs are mainly mounted, pixel electrodes, orthogonal gates and data lines, a color filter substrate, and the transparent substrate and the color filter substrate. A liquid crystal material disposed between the two. In order to use such TFT technology, it is generally necessary to use a separate peripheral integrated circuit for driving the gate and source (ie, data input) of the TFT array.

  The active matrix LCD includes matrix pixels that include red, green, and blue cells, respectively. Each cell has a transistor for controlling the operation of the cell. In general, cells in the same line in the display device have transistor gate electrodes in which each transistor is commonly connected to one gate line. In addition, cells in the same column generally have source electrodes commonly connected to one source line. Thus, each cell of each pixel can be individually addressed by selecting one gate line and one source line.

  One consideration in the operation of a display device such as an LCD is that the liquid crystal deteriorates if the electric field applied to the liquid crystal is always applied only in the same direction. Accordingly, in general, the liquid crystal display device periodically reverses the polarity of the electric field applied to the gate of the display device in order to reduce deterioration of the liquid crystal. Such inversion is performed, for example, by changing the common voltage applied to the liquid crystal panel and appropriately changing the gate voltage applied to the gate line of the LCD. In the past, several techniques have been used to achieve such inversion functions, including frame inversion, line inversion and n-line inversion. Each inversion method is specifically described below.

  In general, frame inversion supplies the same polarity to all gate lines in one frame. The polarity is reversed in the next frame. FIG. 1 shows an example of frame inversion. As shown in FIG. 1, each gate line has a positive polarity (+) in the Nth frame and a negative polarity (−) in the N + 1th frame. Accordingly, the voltage Vcom indicating the polarity of the gate drive signal is changed once for each frame as shown in FIG. However, frame inversion may cause flicker that is easily recognized during display. Flicker occurs because the light transmittance of the LCD is not the same for both polarities. In each successive frame, the entire frame changes from a bright frame to a dark frame, so that the difference in light transmittance between the two polarities is easily recognized by flicker.

  Line inversion methods have been used to reduce flicker in displays. FIG. 2 shows an example of line inversion. In line inversion, each frame has the opposite polarity in one frame. Also, such polarity is inverted in line units in each successive next frame. Therefore, as shown in FIG. 2, in the Nth frame, the first line is driven with the positive polarity and the second line is driven with the inverted polarity having the negative polarity. The third line is inverted again to have a positive polarity, and the fourth line is inverted again to have a negative polarity. In the (N + 1) th frame, each line is driven with a polarity opposite to that in the Nth frame. Therefore, the first line has a negative polarity, the second line is inverted and has a positive polarity, the third line is inverted again and driven with a negative polarity, and the fourth line is a positive polarity. Driven by sex. Such a change in polarity is indicated by a change in Vcom in FIG.

  Line inversion means that the display brightness is the same from frame to frame, and in general, the size of each scan line is the difference in light transmission between alternating frames when viewed from a typical viewing distance with the human eye. Since it is smaller than a distinguishable value, flicker can be reduced. However, because the driver circuit must switch the polarity for each scan line, the amount of power required to drive the gate line of the display device is reversed compared to the frame inversion method. It is a large amount in proportion to the number of times to make it.

  An n-line inversion method is used to reduce power consumption while reducing flicker. FIG. 3 shows an n-line inversion where n is 3. In n-line inversion, every n consecutive lines in one frame have the opposite polarity. Therefore, as shown in FIG. 3, in the Nth frame, the first three lines are driven with a positive polarity, and the second three lines are driven with an inverted negative polarity. The polarity is reversed again in the next third three lines to have a positive polarity, and the next fourth three lines are driven again in a reversed negative polarity. The polarity inversion in the (N + 1) th frame is driven in the opposite direction to the Nth frame. Accordingly, in the (N + 1) th frame, the first three lines are driven with negative polarity, the second three lines are driven with inverted positive polarity, and the third three lines have negative polarity, The fourth three lines are driven with positive polarity. Such a change in polarity is reflected in the change in Vcom in FIG.

  Since n-line inversion reduces the number of times the polarity is changed compared to line inversion, power consumption can be reduced compared to line inversion. In addition, since the n-line inversion has the opposite polarity in units of n lines in one frame, flicker can be reduced compared to the frame inversion. However, flicker can be recognized even in a display using n-line inversion, and flicker is more easily recognized as the number of n increases.

  FIG. 4 is a graph showing the relationship of power consumption due to frame inversion, n-line inversion, and line inversion. As shown in FIG. 4, line inversion consumes 1.85 mA of current per frame. Frame inversion consumes 1.35 mA of current per frame. The n-line inversion when n is 2 consumes 1.60 mA per frame and the n-line inversion when n is 3 consumes 1.47 mA per frame. If n increases, the power consumption amount approaches the power consumption amount of frame inversion.

  The technical problem to be achieved by the present invention is to provide a gate line driving method and an LCD that reduce power consumption and does not cause flickering of a display image.

  In order to achieve the object of the present invention, according to one embodiment of the present invention, a line scan of a display device in an over wrapping block-wise fashion, for example, a discontinuous block of gate lines. And a gate line driving method of a display device by overlapping in the block unit form.

  The gate line of the block unit in the gate line is composed only of gate lines that are not adjacent in the display device. Also, two consecutive gate line blocks include one or more gate lines adjacent from each of the two blocks. In addition, the gate line polarity of adjacent gate line blocks is inverted in units of blocks in one frame displayed on the display device. In the gate line block, the gate line polarity is inverted by successive frames displayed on the display device. Each block of gate line blocks may include less than half of the total number of gate lines of the display device.

  According to another embodiment of the present invention, the gate line block includes n gate lines, and the gate lines are distributed at k gate line intervals. At that time, n ≧ 2 and k ≧ 1. As an example, n = 3 and k = 1.

  According to yet another embodiment of the present invention, data corresponding to a driven gate line in a continuous overlapping block form is provided to a drive source line associated with the gate line driven from memory. .

  Data stored in memory may be stored in a continuous overlapping block form and may be read in a continuous overlapping block form. Data stored in the memory can be recorded / reproduced in / from the memory by changing the address j ′ (1 ≦ j ′ ≦ 2n), and a new address d can be provided. At that time, n is the number of lines in one block, and the address change is performed by sequentially changing the first address corresponding to the first block using the first count j (the first address d is then d = j '+ (J-1), (j is 1 to n, j' is 1 to n)) and sequential second address change corresponding to the second block using the first count j (the second address d at that time) Includes d = j ′ − (j−1), where j is n to 1 and j ′ is n + 1 to 2n.

  In yet another embodiment of the present invention, the display device includes an LCD. The display device may include an organic light emitting device (OLED).

  In another embodiment of the present invention, a system for controlling driving of a display apparatus receives data and drives a source line of the display apparatus in response to the received data, the display apparatus A gate driver circuit for selectively driving the gate lines, and a timing control circuit. The timing control circuit receives data to be displayed on the display device, controls the gate driver circuit, and selectively uses the discontinuous gate line block to select the gate line in an overlapping block form. The received data corresponding to the driven gate line is provided to the source driver circuit.

  In another embodiment of the present invention, the timing control circuit includes a driving voltage generator to invert the gate line electrode for each successive gate line block for one frame displayed on the display device. Further control. The timing control circuit further controls the driving voltage generator to invert the gate line electrode of the gate line block for each successive frame displayed on the display device.

  In still another embodiment of the present invention, the timing control circuit receives a memory scan address, changes the address in a continuous overlapping block form, and provides the changed address to the memory. A memory address changing circuit for storing / reproducing data displayed in / from the memory in a continuous overlapping block form is included. The timing control circuit further includes a line sequence change circuit that receives a gate line identifier, changes the gate line identifier according to an overlapping block form, and provides the changed gate line identifier to a gate driver circuit. . The memory address changing circuit provides an address d obtained by changing the memory scan address j 'of 1 to 2n (n is the number of lines in one block). At that time, the address change uses the first count j to sequentially change the first address corresponding to the first block (where the first address is d = j ′ + (j−1), (j is 1 to n and j ′ are 1 to n)), and the second address corresponding to the second block is sequentially changed using the first count j (the second address d is then d = j '-(J-1), (j is n to 1, j' is n + 1 to 2n).

  The memory address changing circuit includes a first inverter that receives the first input bit of the memory scan address, a second inverter that receives the second input bit of the memory scan address, and a third inverter that receives the third input bit of the memory scan address. Includes inverter. The first NAND gate receives the output of the first inverter and the second input bit. The second NAND gate receives the output of the second inverter and the first input bit. The third NAND gate receives the outputs of the third inverter and the second inverter. The fourth NAND gate receives the outputs of the second NAND gate and the second NAND gate. The fifth NAND gate receives the third input bit and the second input bit. The sixth NAND gate receives the output of the third NAND gate and the output of the first inverter. The seventh NAND gate receives the first input bit, the second input bit, and the third input bit. The eighth NAND gate receives the output of the fourth NAND gate and the output of the third inverter. The ninth NAND gate receives the output of the fourth NAND gate and the third input bit. The tenth NAND gate receives the output of the fifth NAND gate and the output of the sixth NAND gate and outputs the first output bit of the changed address. The eleventh NAND gate receives the output of the seventh NAND gate and the output of the eighth NAND gate and outputs the second output bit of the changed address. The twelfth NAND gate receives the output of the seventh NAND gate and the output of the ninth NAND gate, and outputs the third output bit of the changed address.

  According to still another embodiment of the present invention, the gate line of the display device drives a first subset including a number of non-adjacent gate lines of the display device gate line and is adjacent to the gate line of the first subset. It is driven by driving a second subset that includes multiple gate lines. The polarities of the voltages supplied to the first subset gate lines and the second subset gate lines are inverted.

  According to still another embodiment of the present invention, one or more of the second subset gate lines are interspersed between the first subset gate lines. The polarity of the voltage supplied to the gate line of the first subset gate line is inverted from the polarity of the voltage supplied to the gate line of the first subset gate line in the previous frame, The polarity of the voltage supplied to the gate line of the line is inverted from the polarity of the voltage supplied to the gate line of the second subset gate line in the previous frame.

  According to yet another embodiment of the present invention, the present invention partitions the display device gate lines into blocks of n non-adjacent gate lines with k gate line spacing between the gate lines in one block. The polarity of the voltage applied to the gate lines sequentially driven by the non-adjacent gate line block is inverted, and applied to the non-adjacent gate line block by the sequential frame of data displayed on the display device. The gate line of the display device is driven by reversing the polarity. Preferably, k is 1 and n is 3.

  For a full understanding of the invention and the operational advantages of the invention and the objects achieved by the practice of the invention, reference should be made to the accompanying drawings illustrating the preferred embodiment of the invention and the contents described in the accompanying drawings. I have to do it.

  According to the LCD of the present invention, the current consumption is reduced by changing the common electrode for every N lines to reduce the current consumption, inserting a tiny memory, and latching the data for each line in the memory. Since the scanning is performed by the interlace method with the k-line interval, the effect of one line polarity is obtained, and the power consumption is reduced and the image quality deterioration such as the flicker phenomenon is prevented.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals provided in each drawing denote the same members.

  Although terms such as first and second have been used to indicate various elements, configurations, regions, layers, and / or sections, the elements, configurations, regions, layers, and / or sections are described above. Not limited by terminology. The terms are used to distinguish one element, configuration, region, layer or section from another element, configuration, region, layer or section. Thus, the first region, layer or section may be referred to as the second region, layer or section.

  The present invention is provided to drive the gate lines in an overlapping block fashion. Accordingly, the gate lines are sequentially driven with the same polarity, and the polarity of the gate lines is inverted to drive the next gate line block. The gate line blocks are overlapped in a manner that the gate line region of the first block overlaps the gate line region of the second block. As described above, adjacent gate lines in the display device sequentially have addresses (identifiers), and the gate lines are pointed to by the addresses or identifiers of the gate lines. Thus, the physical location on the display device is indicated by pointing to the area of the gate lines of the two blocks that are overlapped, and the pixels controlled by the gate lines are crossed with each other. The spacing between gate lines in one block of gate lines may or may not be the same.

  In another embodiment of the present invention, the block has n gate lines, and the blocks have the same k-line spacing between sequential lines. In this embodiment, k + 1 sequential blocks are overlapped. Therefore, if k is 1, two sequential blocks are overlapped, and if k is 2, three sequential blocks are overlapped. Other schemes of overlapping blocks can be implemented without departing from the scope of the present invention.

  In another embodiment, the polarity of the corresponding block is inverted every m frames (where m ≧ 1). In another embodiment, the polarity of the corresponding block is reversed sequentially every frame. That is, m = 1.

  By driving the gate lines in units of overlapping blocks, the number of lines of the same polarity driven compared to n-line inversion is the same as that of 1 line inversion, and flicker is greatly reduced, as in n-line inversion. Power consumption can also be reduced.

  FIG. 5 shows a sequential frame in which the gate lines are driven in an overlapping block fashion. In FIG. 5, k is 1 and n is 3. As shown in FIG. 5, in the Nth frame, the first, third, and fifth lines are driven with positive polarity, and become the first block of gate lines. The gate line area provided in the first block is 1 to 5 lines. The next second, fourth, and sixth lines are driven with a negative polarity to form a second block of gate lines. The gate line area provided in the second block is 2 to 6 lines. Therefore, the gate line region of the first block overlaps with the gate line region of the second block.

  The third block of gate lines includes 7, 9, 11 lines, and the fourth block of gate lines includes 8, 10, 12 lines. In the Nth frame, the third block is driven with a positive polarity, and in the Nth frame, the fourth block is driven with a negative polarity. In such a section of the frame, all the gate lines of the display device are allocated in blocks. Sequential blocks have opposite polarities, and the polarity in the Nth frame of one block is inverted in the N + 1th frame. Therefore, unlike the conventional frame inversion, line inversion, and n-line inversion methods in which the gate lines are sequentially addressed, the gate lines according to the present invention are addressed non-sequentially.

  Table 1 shows an address sequence of a band of k = 1 and n = 3 on an xy display (y is a natural number divided by 3).

  FIG. 6 is a block diagram of a display system according to an embodiment of the present invention. Circuits and equivalent circuits described herein and / or circuit combinations and software for driving the gate lines of a display device implemented in an overlapping block form utilizing discontinuous blocks of gate lines. , Provided as a means for controlling the gate line driver. Also, although the address change providing an overlapping block scan of the gate line is described as being performed in the timing control circuit, the gate line can be easily analogized by those skilled in the art to which the present invention applies. This overlapping block scan method can also be achieved by other components of the system, such as gate line drivers and / or source line driver circuits. In addition, the gate line addressing is implemented in hardware by changing the connection between the gate driver and the display panel so that the continuous activation of the gate line has the desired overlapping block gate scan pattern. Can be done.

  Referring to FIG. 6, the display apparatus 300 includes a driver circuit 302 and a display panel 304. Display panel 304 is not related to any display device that uses gate lines or other select lines to control access to the pixels of display panel 304. For example, the display panel can be an LCD panel, PDP, OLED, or other display panel. In one embodiment of the present invention, the display panel 304 is a panel in which the polarity of the gate can be reversed to avoid burn-in or other degradation of the display panel 304. In one embodiment of the present invention, the polarity of the voltage driving the display panel may be controlled by a signal such as Vcom shown in FIG.

  Referring to FIG. 6, the driver circuit 302 includes a data line driver circuit 306 that drives a data line such as S1 to SN source lines on the display panel 304. The gate line driver circuit 308 drives gate lines such as G1 to GN gate lines of the display panel 304. The gate line driver circuit 308 and the data line driver circuit 306 are controlled by the timing control circuit 310 to drive the gate line and the data line in an overlapping block manner according to an embodiment of the present invention. The timing control circuit 310 controls the driving voltage generation circuit 312 to selectively invert the polarity of the gate signal provided to the display panel 304. The grayscale voltage generation circuit 314 supplies a voltage provided to the gate line driver circuit 306. The memory 316 is coupled to the timing control circuit 310 and buffers data supplied to the data line driver circuit 306.

  In one embodiment of the present invention, the data line driver circuit 306, the gate line driver circuit 308, the drive voltage generation circuit 312, the display panel 304, and / or the gray voltage generation circuit 314 are known as will be understood by those skilled in the art. The gate line is driven in an overlapping block manner under the control of the timing control circuit 310. In other embodiments of the present invention, some or all of the functions described in connection with the timing control circuit 310 may be provided by other components / circuits. Thus, embodiments of the invention are not limited to the specific arrangement of circuits / components / functions shown in FIG.

  The display device 300 is provided as part of data processing or other system to receive data to be displayed through an interface means such as the RGB interface 356 from the graphics processor 350 associated with the peripheral device 352 and / or the central processing unit 354. it can. In an embodiment of the present invention, the display device 300 may be attached to a single device such as a personal computer, a notebook computer, a smart device, a wireless telephone, a separate device such as a computer monitor, and / or a television, It may be mounted on a media display device such as a home theater or other component system. With such an embodiment, the distribution of specific components, techniques and functions provided to the display device may differ from that shown in FIG.

  The operation of the display device 300 will be described. The timing control circuit 310 receives RGB data RGB, vertical sync Vsync, horizontal sync Hsync, and clockCLK signals, and uses this information for driving the panel 304. In particular, the Vsync and Hsync signals may be used to detect the start of a frame of data and the start of a data line in one frame. Therefore, the timing control circuit 310 may use the signal to detect when the data line driver 306 and the gate line driver 308 should be driven. The timing control circuit 310 stores 2n data lines in the memory 316. At that time, n indicates the number of data lines per block. The timing control circuit 310 controls the gate line, transmits the data to the data line driver 306 in the block form described above, and generates a PICS signal that controls the polarity of the Vcom signal by the data block provided to the panel 304.

  FIG. 7 is a block diagram showing in detail a part of the driver circuit 302 according to an embodiment of the present invention. Referring to FIG. 7, the timing control circuit 310 includes a memory scan address generation circuit 402 and a gate drive line sequence generation circuit 404. The memory scan address generation circuit 402 generates sequential addresses for extracting data from the memory 316. The memory address changing circuit 406 changes the address provided from the memory scan address generating circuit 402 to make the memory 316 accessible in the overlapping block manner described above. The extracted data is provided to the data line driver circuit 306. The line sequence change circuit 408 changes the sequence of the driver driven by the gate line driver circuit 308 to correspond to the data provided to the data line driver circuit 306. Similarly, the gate driver line sequence generation circuit 404 controls the PICS signal to invert the polarity of the Vcom signal every n lines. For example, the address change circuit 406 and the line sequence change circuit 408 sequentially change the address and the line sequence according to the sequence shown in Table 1.

  In the embodiment shown in FIG. 7, the data for driving the line driver circuit 306 is stored in the memory 316 according to the line sequence and extracted from the memory in an overlapping block manner. On the other hand, the data may be stored in the memory 316 in an overlapping block manner, at which time it is sequentially extracted from the memory 316. In that case, the memory address changing circuit can change the recording address to the memory 316 instead of the read address.

  FIG. 8 shows a logic circuit of the memory address changing circuit 406 according to one embodiment of the present invention. The logic circuit of FIG. 8 receives INPUT [0], INPUT [1], and INPUT [2] as input address bits. The address bits are numbers that sequentially increase from 1 to 6, and are changed to generate output signals OUTPUT [0], OUTPUT [1], and OUTPUT [2]. The output signals have the order 1, 3, 5, 2, 4, 6 to extract data from the memory 316 in an overlapping block fashion.

  As shown in FIG. 8, the first input address bit INPUT [2] is provided as the first inverter INV1, and the output of the first inverter INV1 is provided as the input of the first NAND gate NAND1. The second input address bit INPUT [1] is provided as the second inverter INV2, and the output of the second inverter INV2 is provided as the input of the second NAND gate NAND2. The first input address bit INPUT [2] is also provided as an input of the second NAND gate NAND2, and the second input address bit INPUT [1] is also provided as an input of the first NAND gate NAND1. The third input address bit INPUT [0] is provided as the input of the third inverter INV3, and the output of the third inverter INV3 is provided as the input of the third NAND gate NAND3. The output of the second inverter INV2 is also provided as the input of the third NAND gate NAND3.

  The output of the first NAND gate NAND1 and the output of the second NAND gate NAND2 are provided as inputs to the fourth NAND gate NAND4. The third input address bit INPUT [0] and the second input address bit INPUT [1] are also provided as inputs of the fifth NAND gate NAND5. The output of the first inverter INV1 and the output of the third NAND gate NAND3 are provided as inputs of the sixth NAND gate NAND6. The third input address bit INPUT [0], the second input address bit INPUT [1] and the first input address bit INPUT [2] are also provided as inputs of the seventh NAND gate NAND7. The output of the third inverter INV3 and the output of the fourth NAND gate NAND4 are provided as inputs of the eighth NAND gate NAND8. The third input address bit INPUT [0] and the output of the fourth NAND gate NAND4 are provided as inputs of the ninth NAND gate NAND9.

  The output of the fifth NAND gate NAND5 and the output of the sixth NAND gate NAND6 are provided as inputs of the tenth NAND gate NAND10. The output of the tenth NAND gate NAND10 is provided as the first output bit OUTPUT [2]. The output of the seventh NAND gate NAND7 and the output of the eighth NAND gate NAND8 are provided as inputs of the eleventh NAND gate NAND11. The output of the eleventh NAND gate NAND11 is provided as the second output bit OUTPUT [1]. The output of the seventh NAND gate NAND7 and the output of the ninth NAND gate NAND9 are provided as inputs of the twelfth NAND gate NAND12. The output of the twelfth NAND gate NAND12 is provided as the third output bit OUTPUT [0].

In general, when the block size is n and the gate line interval k in one block is 1, the address change can be divided into two parts. This is the case with the first part where the count j increases from 1 to n and the second part where the count j decreases from n to 1. The output of the sequential address counter j ′ increases sequentially from 1 to 2n. In that case, the new address d for the first part corresponding to the first block is
d = j ′ + (j−1), (j is 1 to n, j ′ is 1 to n), and the new address d for the second part corresponding to the second block is
d = j ′ − (j−1), (j is n to 1, j ′ is n + 1 to 2n).

  For example, such an address change implements an arithmetic logic unit (ALU) for the first and second parts, and uses the combinational logic described above or other techniques known in the art. It may be implemented and executed.

  While various embodiments of the present invention have been described with reference to driving gate lines in an overlapping block fashion, the present invention is not limited to driving gate lines, and the lines of a display device can be scanned sequentially. It can be applied to any display device. Thus, embodiments of the present invention can be applied to scan the lines of a display in an overlapping block fashion regardless of the predetermined technique used to scan each line of the display device.

  Note that the embodiments of the present invention have been described with reference to sequentially driven overlapping blocks. However, an intervening operation may occur while driving or scanning the lines of two overlapping blocks.

  Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely an example, and it will be understood by those skilled in the art that various modifications and other equivalent embodiments are possible. You will understand that. Therefore, the true technical protection scope of the present invention must be determined by the technical idea of the claims.

  The LCD according to the present invention can be used for a single device such as a personal computer, a notebook personal computer, a smart device, a wireless telephone, etc., a separate device such as a computer monitor, and / or a media display device such as a television or a home theater, or others. It can also be used for other component systems.

Two sequential frames showing frame inversion. Two sequential frames showing line inversion. Two sequential frames showing n-line inversion. 3 is a graphic showing power consumption related to frame inversion, line inversion, and n-line inversion. 2 is two sequential frames showing overlapping block-like inversion according to one embodiment of the present invention. 1 is a block diagram illustrating a display system according to an embodiment of the present invention. 1 is a block diagram of a timing control circuit according to an embodiment of the present invention. FIG. 3 is a block diagram of an address generation circuit according to an embodiment of the present invention.

Explanation of symbols

300 Display Device 302 Driver Circuit 304 Display Panel 306 Data Line Driver Circuit 308 Gate Line Driver Circuit 310 Timing Control Circuit 312 Drive Voltage Generation Circuit 314 Grayscale Voltage Generation Circuit 316 Memory

Claims (42)

In a method of scanning a line on a display device,
Scanning the lines of the display device in an overlapping block form embodying a block of non-adjacent lines of the display device.   The method of claim 1, wherein scanning the lines of the display device includes driving the gate lines of the display device in an overlapping block form embodying a block of non-adjacent gate lines. Method.   The method of claim 2, wherein the gate lines in the gate line block include only non-adjacent gate lines of the display device.   The method of claim 2, wherein two consecutive gate line blocks are gate lines in which one or more of the respective gate lines of the two blocks are adjacent to each other. The method
The method of claim 2, further comprising reversing the polarity of the gate line for each successive gate line block in one frame displayed on the display device. The method
6. The method of claim 5, further comprising reversing the polarity of the gate lines of the gate line block for each successive frame displayed on the display device. The method
The method of claim 2, further comprising reversing the polarity of the gate lines of the gate line block on successive frames displayed on the display device.   The method of claim 2, wherein each block of the gate line block includes less than half of the total number of gate lines of the display device.   3. The method of claim 2, wherein the gate line block includes n gate lines, arranged at k gate line intervals, n ≧, and k ≧ 1.   The method according to claim 9, wherein n = 3 and k = 1. The method
Outputting data corresponding to the driven gate line from the memory and providing for driving a source line associated with the driven gate line in the order of the overlapping block form; The method according to claim 2.   The method of claim 11, wherein the data stored in the memory is stored in the order of the overlapping block form or read from the memory in the order of the overlapping block form. . When the number of lines in one block is n, the data stored in the memory is changed to the address j ′ that increases from 1 to 2n, and a new address d is generated. Recorded / played,
The address changing step includes changing a first sequential address corresponding to the first block using a first count j;
d = j ′ + (j−1), (j is 1 to n, j ′ is 1 to n) and a second sequential address corresponding to the second block using the first count j. The change stage of
and d = j ′ − (j−1), wherein j is n to 1 and j ′ is n + 1 to 2n.   The method of claim 2, wherein the display device comprises a liquid crystal display device.   The method of claim 2, wherein the display device comprises an OLED. In a system for controlling the driving of a display device,
A source driver circuit for receiving data and driving a source line of the display device based on the received data;
A gate driver circuit for selectively driving gate lines of the display device;
The gate line is driven by controlling the gate driver circuit to receive data to be displayed on the display device and to selectively drive the gate line in an overlapping block form embodying a non-adjacent gate line block. Including a timing control circuit for providing the source driver circuit with received data corresponding to   The timing control circuit controls the driving voltage generator to invert the polarity of the gate line for each continuous gate line block in one frame displayed on the display device. 16. The system according to 16.   The timing control circuit controls the driving voltage generator to invert the polarity of the gate line of the gate line block for each successive frame displayed on the display device. The system described in.   The timing control circuit controls the driving voltage generator to invert the polarity of the gate line of the gate line block for each successive frame displayed on the display device. The system described in. The timing control circuit includes:
Data received from the memory in the order of the overlapping block form, receiving the memory scan address, modifying the address in the order of the overlapping block form, and providing the modified address to the memory A memory address changing circuit for storing and / or extracting
A line sequence change circuit that receives a gate line identifier, modifies the gate line identifier in the order of the overlapping block form, and provides the modified gate line identifier to the gate driver circuit. The system according to claim 16. The memory address changing circuit generates a new address d by changing the memory scan address j ′ that increases from 1 to 2n when the number of lines in one block is n,
The address change is a first sequential address change corresponding to the first block using a first count j, ie,
d = j ′ + (j−1), where j is 1 to n and j ′ is 1 to n,
Using the first count j, the second sequential address corresponding to the second block is changed, that is, d = j ′ − (j−1), where j is n to 1, j ′ is n + 1 to 2n 21. The system of claim 20, comprising: The memory address changing circuit is
A first inverter for receiving a first input bit of the memory scan address;
A second inverter for receiving a second input bit of the memory scan address;
A third inverter for receiving a third input bit of the memory scan address;
A first NAND gate receiving the output of the first inverter and the second input bit;
A second NAND gate receiving the output of the second inverter and the first input bit;
A third NAND gate receiving the output of the third inverter and the output of the second inverter;
A fourth NAND gate receiving the output of the first NAND gate and the output of the second NAND gate;
A fifth NAND gate receiving the third input bit and the second input bit;
A sixth NAND gate receiving the output of the third NAND gate and the output of the first inverter;
A seventh NAND gate receiving the first input bit, the second input bit, and the third input bit;
An eighth NAND gate receiving the output of the fourth NAND gate and the output of the third inverter;
A ninth NAND gate receiving the output of the fourth NAND gate and the third input bit;
A tenth NAND gate receiving the output of the fifth NAND gate and the output of the sixth NAND gate and outputting a first output bit of the modified address;
An eleventh NAND gate receiving the output of the seventh NAND gate and the output of the eighth NAND gate and outputting a second output bit of the corrected address;
21. The system of claim 20, further comprising: a twelfth NAND gate that receives an output of the seventh NAND gate and an output of the ninth NAND gate and outputs a third output bit of the corrected address.   The system of claim 16, wherein the display device includes a liquid crystal display device.   The system of claim 16, wherein the display device comprises an OLED.   The system of claim 16, wherein gate lines in the gate line block include only non-adjacent gate lines of the display device.   The system of claim 16, wherein two consecutive gate line blocks are gate lines in which one or more of the respective gate lines of the two blocks are adjacent to each other.   The system of claim 16, wherein each block of the gate line block includes less than half of the total number of gate lines of the display device.   The system of claim 16, wherein the gate line block includes n gate lines and is arranged at k gate line intervals, where n ≧ and k ≧ 1.   29. The system of claim 28, wherein n = 3 and k = 1. In a method of driving a gate line of a display device, the method includes:
Driving a first subset of the display device gate lines including a plurality of non-adjacent gate lines;
Driving a second subset of gate lines of the display device including a plurality of gate lines adjacent to the gate lines of the first subset;
Reversing the polarity of the voltages supplied to the first subset of gate lines and the second subset of gate lines.   31. The method of claim 30, wherein one or more of the second subset of gate lines are crossed with the first subset of gate lines. The method
Reversing the polarity of the voltage supplied to the gate line of the first subset gate line from the polarity of the voltage supplied to the gate line of the first subset gate line during a previous frame;
Reversing the polarity of the voltage supplied to the gate line of the second subset gate line from the polarity of the voltage supplied to the gate line of the second subset gate line during a previous frame. 32. The method of claim 30, wherein:   The method of claim 30, wherein the display device comprises an LCD or an OLED.   The method of claim 30, wherein the first subset of gate lines includes only non-adjacent gate lines of the display device.   The first subset of gate lines includes less than half of the total number of gate lines of the display device, and the second subset of gate lines includes less than half of the total number of gate lines of the display device. 32. The method of claim 30, comprising.   31. The gate line of claim 30, wherein each gate line of the first and second subsets includes n gate lines and is arranged at k gate line intervals, where n ≧ and k ≧ 1. the method of.   37. The method of claim 36, wherein n is 3 and k is 1. In a method of driving a gate line of a display device, the method includes:
A gate line of the display device is divided into a block of non-adjacent gate lines having k gate lines between gate lines of blocks and a block of non-adjacent gate lines having n non-adjacent gate lines in one block. A stage of classification;
Reversing the polarity of the voltage supplied to the sequentially driven blocks of the non-adjacent gate line blocks;
Reversing the polarity of the voltage supplied to the block of non-adjacent gate lines for each successive frame displayed on the display device.   40. The method of claim 38, wherein k is 1 and n is 3.   The method of claim 38, wherein the display device comprises an LCD or an OLED. In a system for driving a gate line of a display device,
A plurality of gate line drivers, each gate line driver associated with each gate line of the display device;
Means for controlling the plurality of gate drivers to drive the gate lines in an overlapping block form embodying non-adjacent gate line blocks. 42. The method of claim 41, wherein the display device comprises an LCD or an OLED.

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