JP2005203513A - Manufacturing method of semiconductor memory and semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor memory that allows the upper surface at a trench wall to touch the lower surface of an interlayer insulation film with a width at the trench wall and memory node electrodes of adjacent trenches to be electrically isolated sufficiently, and to provide a semiconductor memory manufactured by that method. <P>SOLUTION: A mask layer where a plurality of trenches TR open in an arranged pattern is formed on a substrate 10 and used as a mask for forming a plurality of trenches partitioned by trench walls 10a in the substrate while being arranged. The mask layer is removed and a plate electrode PL (12) is formed on the surface layer of the inner wall of the trench and a capacitor insulation film 13 is formed on the surface of the inner wall of the trench. Subsequently, a conductive film is formed of a conductive material insulated by insulation processing to become thicker than the depth of the trench. Thereafter, the conductive film is subjected to insulation processing from the upper surface until the conductive film reaches the upper surface of the trench wall and an interlayer insulation film 15 is formed, thus separating the conductive film to the memory node electrode MN (14) of each trench. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a semiconductor memory device and a semiconductor memory device, and more particularly to a method of manufacturing a semiconductor memory device having a DRAM (dynamic random access memory) and a semiconductor memory device manufactured by the manufacturing method.

In recent years, semiconductor devices such as VLSI have been reduced by 70% in three years to achieve higher integration and higher performance.
For example, a MOS type DRAM in which one memory cell is composed of one transistor for switching (metal-oxide-semiconductor stacked field effect transistor (MOSFET) and one memory capacitor is highly integrated as a process driver in a semiconductor device. It is going on.
As the device is miniaturized, the area of the memory cell is reduced, so that the area occupied by the memory capacitor is also reduced.

However, in order to secure an operating margin and to secure the soft error tolerance due to alpha rays, the storage capacity of the memory capacitor is a constant value of 20 to 30 fF per bit regardless of the generation of the DRAM. It is kept in.
Therefore, although the occupation area of the memory capacitor is reduced as the memory capacitor is miniaturized, it is necessary to secure a necessary amount of the storage capacity, and various contrivances have been made for that purpose.

For example, a method of reducing the film thickness of the capacitor insulating film and a method of increasing the storage capacity using a material having a higher relative dielectric constant as the capacitor insulating film have been developed.
On the other hand, the electrode structure of the capacitor has been devised, and those having various structures have been developed. The memory capacitor has a storage node electrode (electrode connected to the capacitor transistor), a plate electrode (electrode grounded to the capacitor), and a capacitor insulating film therebetween. For example, the capacitors are stacked. The stack surface type or the trench type structure that forms the storage node electrode in the depth direction with respect to the semiconductor substrate, thereby increasing the surface area of the opposing surface of the storage node electrode and the plate electrode. The storage capacity can be increased.

A DRAM having the above trench type capacitor will be described.
FIG. 7A is a cross-sectional view of a conventional DRAM memory cell, and FIG. 7B is a plan view. FIG. 7A corresponds to a cross-sectional view taken along the line XX ′ in FIG.
A trench TR is formed in a region excluding the first n-type semiconductor layer 101 to be an active region AA formed in the p-type semiconductor substrate 100, and a second n-type semiconductor layer 102 is formed at a predetermined depth from the inner wall surface of the trench TR. This becomes the plate electrode PL of the memory capacitor.
A capacitor insulating film 103 is formed so as to cover the inner wall surface of the trench TR, and a third n-type semiconductor layer 104 made of polysilicon is embedded therein, which becomes a storage node electrode MN of the memory capacitor.
As described above, the second n-type semiconductor layer 102 (plate electrode PL), the capacitor insulating film 103, and the third n-type semiconductor layer 104 (storage node electrode MN) constitute a memory capacitor.

The first n-type semiconductor layer 101 (active area AA) is made of STI (Shallow) made of silicon oxide.
Trench Isolation) type element isolation insulating film 105, and fourth element layer 106 made of polysilicon is embedded in element isolation insulating film 105.

The first n-type semiconductor layer 101 (active region AA) includes a channel formation region and a source / drain region (not shown) sandwiching the channel formation region, and the first n-type semiconductor layer 101 (active region AA) in the channel formation region. A gate electrode 107 is formed thereon via a gate insulating film (not shown).
The MOSFET is configured as described above.

In the MOSFET configured as described above, one source / drain is electrically connected to the third n-type semiconductor layer 104 (the storage node electrode MN of the memory capacitor) via the semiconductor layer 106, and the other source / drain is a bit. It is connected to a bit line (not shown) via a contact 108. Further, the gate electrode 107 is connected to a word line.
A memory cell having the above configuration is integrated in a matrix to form a DRAM.

In the above configuration, the connection between the fourth semiconductor layer 106 and the source / drain region in the first n-type semiconductor layer 101 is connected by a junction from the fourth semiconductor layer 106 to the first n-type semiconductor layer 101 by impurity diffusion. It has become so.
In the above method, the following restrictions are imposed on the area of the trench.
(1) Since a junction is formed by impurity diffusion from the fourth semiconductor layer 106 to the first n-type semiconductor layer 101, the channel formation of the first n-type semiconductor layer 101 in the fourth semiconductor layer 106 is ensured to ensure the characteristics of the MOSFET. It is necessary to keep away from the region sufficiently, that is, to secure a certain distance between the end of the trench and the end of the gate electrode.
(2) It is necessary to ensure a certain distance from the active area AA of the cells constituting another adjacent bit.

However, if an attempt is made to satisfy the above constraints in a trench capacitor, it becomes impossible to sufficiently secure the diameter of the trench as the miniaturization proceeds.
Therefore, in order to secure the surface area of the opposing surfaces of the storage node electrode and the plate electrode and secure the storage capacity of the memory capacitor, it is common to design the trench depth to be 5 μm or more.

  On the other hand, Patent Document 1 discloses a DRAM having a structure in which a storage node electrode, a capacitor insulating film, and a plate electrode are buried in a substrate as a trench capacitor and planarized, and another silicon substrate is bonded with an insulating layer interposed therebetween. Is described.

A DRAM in which the above trench type capacitor is embedded in a substrate will be described.
FIG. 8A is a cross-sectional view of a conventional DRAM memory cell, and FIG. 8B is a plan view. FIG. 8A corresponds to a cross-sectional view taken along line XX ′ in FIG.
A trench TR that is partitioned by the trench wall 10a and the mask layer 11 is formed in the semiconductor substrate 10. Mask layer 11 is a layer used as a mask when forming trench TR.
Further, the first n-type semiconductor layer 12 is formed at a predetermined depth from the inner wall surface of the trench TR, and this becomes the plate electrode PL of the memory capacitor.
Capacitor insulating film 13 is formed so as to cover the inner wall surface of trench TR, and second n-type semiconductor layer 14 made of polysilicon is embedded therein, which becomes storage node electrode MN of the memory capacitor.
As described above, the first n-type semiconductor layer 12 (plate electrode PL), the capacitor insulating film 13, and the second n-type semiconductor layer 14 (storage node electrode MN) constitute a memory capacitor.

  A silicon oxide interlayer insulating film 15 is formed so as to cover the memory capacitor, and a third n-type semiconductor layer 16 made of crystalline silicon and serving as an active region AA is laminated thereon.

The third n-type semiconductor layer 16 (active area AA) is isolated by an STI-type element isolation insulating film 17 made of silicon oxide.
A fourth semiconductor layer 18 made of polysilicon is buried in a contact hole reaching the second n-type semiconductor layer 14 (storage node electrode MN) provided in a boundary region between the element isolation insulating film 17 and the third n-type semiconductor layer 16. Yes.

Further, in the third n-type semiconductor layer 16 (active region AA), a channel formation region and a source / drain region (not shown) are formed so as to sandwich the channel formation region, and the third n-type semiconductor layer 16 (active region AA) in the channel formation region is formed. A gate electrode 19 is formed on a non-illustrated gate insulating film.
The MOSFET is configured as described above.

In the MOSFET configured as described above, one source / drain is electrically connected to the second n-type semiconductor layer 14 (storage node electrode MN) via the fourth semiconductor layer 18, and the other source / drain is connected to the bit contact. 20 is connected to a bit line (not shown). Furthermore, the gate electrode 19 is connected to a word line.
A memory cell having the above configuration is integrated in a matrix to form a DRAM.

  Since the DRAM having the memory cell has a structure in which the MOSFET and the memory capacitor are stacked in the vertical direction with the interlayer insulating film 15 interposed therebetween, the area of the memory capacitor is maximized without being restricted by the active region AA. Therefore, it is not necessary to dig deeper than necessary as described above. In addition, since the opening diameter of the trench can be increased, the difficulty of the photolithography process is reduced, and the etching time can be dramatically shortened.

The manufacturing method of the substrate portion in which the trench type capacitor of the DRAM having the memory cell is embedded is as follows.
For example, a mask layer 11 having a thickness of about 500 nm made of a stacked body of a silicon nitride layer 11a and a silicon oxide layer 11b is formed on the semiconductor substrate 10, and a trench pattern is opened in the upper layer of the mask layer 11 by a photolithography process. A resist film is patterned, and the trench pattern is transferred to the mask layer 11 by anisotropic etching using the resist film as a mask.
Next, a trench TR serving as a capacitor is formed in the semiconductor substrate 10 by anisotropic etching using the mask layer 11 processed into a trench pattern as a mask.
Next, the first n-type semiconductor layer 12 (plate electrode PL) is formed on the inner wall surface layer portion of the trench TR, the capacitor insulating film 13 is further formed on the inner wall surface of the trench TR, and the trench TR is buried to deposit polysilicon. Then, the polysilicon is etched back. However, it is necessary to make the surface of the polysilicon layer remaining in the trench TR substantially coincide with the surface of the mask layer 11 so that only the inside of the trench TR remains. In this way, the second n-type semiconductor layer 14 (storage node electrode MN) is formed. Here, CMP (mechanical chemical polishing) may be used instead of etch back. Further, silicon oxide is deposited to form an interlayer insulating film 15.

In the process following the above-described method for manufacturing the substrate portion, the third n-type semiconductor layer 16 made of crystalline silicon is formed on the interlayer insulating film 15 by a method similar to the method of forming an SOI (Silicon on insulator) substrate, for example. .
Next, the element isolation insulating film 17 is formed by the STI method, the fourth semiconductor layer 18 in contact with the second n-type semiconductor layer 14 (storage node electrode MN) is formed, and the gate electrode 19 is formed on the third n-type semiconductor layer 16. The source / drain regions and the bit contact 20 are formed to obtain the structure shown in FIG.

In the above manufacturing method, in order to avoid damage to the semiconductor substrate 10 when the etch-back process is performed on the polysilicon in the step of forming the second n-type semiconductor layer 14 (storage node electrode MN), the semiconductor substrate Therefore, it is necessary to leave the mask layer 11 used as a mask for the trench TR processing for 10. In the etch back of polysilicon in the step of forming the second n-type semiconductor layer 14 (storage node electrode MN) in the trench TR, it is very difficult to adjust the height.
On the other hand, when polishing the polysilicon by CMP, it is necessary to leave the mask layer 11 in the same manner as described above in order to avoid damage to the trench wall 10a of the substrate 10 between the memory capacitors.

By the way, the shape of the mask layer 11 that needs to be left on the upper portion of the trench wall portion 10a for the above-described reason is shown in FIG. 8A as the miniaturization progresses and the interval between the trenches decreases. As shown in FIG. 8C corresponding to an enlarged view of the Y portion in the middle, a so-called rounding shape RD with a shoulder portion removed after the trench etching process.
For this reason, the second n-type semiconductor layer 14 (storage node electrode MN) is originally designed to be separated for each second n-type semiconductor layer 14 by the mask layer 11, but is adjacent as the mask layer shape becomes rounding. There is a risk that electrical isolation of the trench from the second n-type semiconductor layer 14 is not sufficient, and electrical isolation cannot be achieved completely.
JP-A-6-104398

  The problem to be solved is that as the shape of the mask layer becomes rounding, the electrical isolation between the storage node electrodes of adjacent trenches may not be sufficient.

  A method of manufacturing a semiconductor memory device according to the present invention is a method of manufacturing a semiconductor memory device in which a plurality of memory cells each having a memory capacitor having a storage node electrode and a transistor are arranged, wherein a plurality of trenches are arranged on a substrate. A step of forming a mask layer opened in step, a step of arranging a plurality of trenches partitioned by a trench wall portion on the substrate using the mask layer as a mask, a step of removing the mask layer, A step of forming a plate electrode from the inner wall surface to a predetermined depth; a step of covering the inner wall surface of the trench to form a capacitor insulating film; and a conductive material that is insulated by an insulation process, and the capacitor insulating film. Forming the conductive film so as to be thicker than the depth of the trench; Isolating the conductive film from the upper surface until reaching the upper surface of the portion, forming an interlayer insulating film, and separating the conductive film into storage node electrodes for each trench; and on the interlayer insulating film Forming a semiconductor layer.

In the method of manufacturing a semiconductor memory device according to the present invention, first, a mask layer having a pattern in which a plurality of trenches are arranged on a substrate is formed, and the mask layer is used as a mask to form a plurality of partitions partitioned by trench walls. A trench is formed side by side on the substrate.
Next, the mask layer is removed, a plate electrode is formed from the inner wall surface of the trench to a predetermined depth, and the inner wall surface of the trench is covered to form a capacitor insulating film.
Next, with the conductive material that is insulated by the insulation treatment, the trench is embedded through the capacitor insulating film, a conductive film is formed so as to be thicker than the depth of the trench, and further until the upper surface of the trench wall is reached. The conductive film is insulated from the upper surface, and the conductive film is separated into storage node electrodes for each trench while forming an interlayer insulating film.
Next, a semiconductor layer is formed over the interlayer insulating film.

  A semiconductor memory device of the present invention is a semiconductor memory device in which a plurality of memory cells having memory capacitors and transistors having storage node electrodes are arranged, and a substrate in which a plurality of trenches partitioned by trench walls are arranged side by side A plate electrode formed at a predetermined depth from the inner wall surface of the trench, a capacitor insulating film formed so as to cover the inner wall surface of the trench, and the trench being embedded through the capacitor insulating film A storage node electrode formed thereon, an interlayer insulating film formed over the substrate and the storage node electrode, and a semiconductor layer formed on the interlayer insulating film and having the transistor formed thereon, The upper surface of the trench wall and the lower surface of the interlayer insulating film are in contact with each other with the width of the trench wall.

In the semiconductor memory device of the present invention described above, a plurality of trenches partitioned by the trench wall portion are formed side by side on the substrate, a plate electrode is formed at a predetermined depth from the inner wall surface of the trench, and the inner wall of the trench A capacitor insulating film is formed so as to cover the surface, and a storage node electrode is formed by filling a trench through the capacitor insulating film.
Further, an interlayer insulating film is formed on the entire surface so as to cover the substrate and the storage node electrode, and a semiconductor layer in which a transistor is formed is formed on the interlayer insulating film.
Here, the upper surface of the trench wall and the lower surface of the interlayer insulating film are in contact with each other with the width of the trench wall.

  In the method of manufacturing a semiconductor memory device according to the present invention, the trench is embedded with a conductive material to be insulated by the insulation process, and the insulation process is performed on the conductive film from the upper surface until reaching the upper surface of the trench wall. The upper surface of the portion and the lower surface of the interlayer insulating film are in contact with each other with the width of the trench wall portion, so that the storage node electrodes of adjacent trenches can be sufficiently electrically separated.

  Since the semiconductor memory device of the present invention has a structure in which the upper surface of the trench wall and the lower surface of the interlayer insulating film are in contact with each other with the width of the trench wall, the storage node electrodes of adjacent trenches are sufficiently electrically separated. Yes.

  Embodiments of a DRAM which is a semiconductor memory device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings.

First Embodiment FIG. 1A is a sectional view of a memory cell of a DRAM according to this embodiment, and FIG. 1B is a plan view. FIG. 1A corresponds to a cross-sectional view taken along the line XX ′ in FIG.
A trench TR partitioned by a trench wall 10a is formed in a semiconductor substrate (substrate) 10, and a first n-type semiconductor layer 12 is formed at a predetermined depth from the inner wall surface of the trench TR, which is a plate of a memory capacitor. It becomes the electrode PL.
Capacitor insulating film 13 is formed so as to cover the inner wall surface of trench TR, and second n-type semiconductor layer 14 made of polysilicon is embedded therein, which becomes storage node electrode MN of the memory capacitor.
As described above, the first n-type semiconductor layer 12 (plate electrode PL), the capacitor insulating film 13, and the second n-type semiconductor layer 14 (storage node electrode MN) constitute a memory capacitor.

  A silicon oxide interlayer insulating film 15 is formed so as to cover the memory capacitor, and a third n-type semiconductor layer 16 made of crystalline silicon and serving as an active region AA is laminated thereon.

The third n-type semiconductor layer 16 (active area AA) is isolated by an STI-type element isolation insulating film 17 made of silicon oxide.
A fourth semiconductor layer 18 made of polysilicon is formed in a contact hole provided at the boundary between the element isolation insulating film 17 and the third n-type semiconductor layer 16 (active area AA) and reaching the second n-type semiconductor layer 14 (storage node electrode MN). (Storage node contact) is embedded.

Further, in the third n-type semiconductor layer 16 (active region AA), a channel formation region and a source / drain region (not shown) are formed so as to sandwich the channel formation region, and the third n-type semiconductor layer 16 (active region AA) in the channel formation region is formed. A gate electrode 19 is formed on a non-illustrated gate insulating film.
The MOSFET is configured as described above.

In the MOSFET configured as described above, one source / drain is electrically connected to the second n-type semiconductor layer 14 (storage node electrode MN) via the fourth semiconductor layer 18, and the other source / drain is connected to the bit contact. 20 is connected to a bit line (not shown). Furthermore, the gate electrode 19 is connected to a word line.
A memory cell having the above configuration is integrated in a matrix to form a DRAM.

  Since the DRAM having the memory cell has a structure in which the MOSFET and the memory capacitor are stacked in the vertical direction with the interlayer insulating film 15 interposed therebetween, the area of the memory capacitor is maximized without being restricted by the active region AA. Therefore, it is not necessary to dig deeper than necessary, and the opening diameter of the trench can be increased, so that the difficulty of the photolithography process is reduced and the etching time can be dramatically shortened.

Here, as shown in FIG. 1C corresponding to an enlarged view of the Y portion in FIG. 1A, the upper surface S of the trench wall portion 10a and the lower surface of the interlayer insulating film 15 have the width of the trench wall portion 10a. It is the structure which touches.
Therefore, the mask layer for forming the trench is left as in the conventional example, and since this shape is rounded, there is no possibility that the electrical isolation between the storage node electrodes is not sufficient. The space is sufficiently electrically separated.

A method for manufacturing the DRAM according to the present embodiment will be described with reference to the drawings.
First, as shown in FIG. 2A, for example, a mask layer is formed on a semiconductor substrate (substrate) 10, and a resist film (not shown) opened in a trench pattern is formed thereon by a photolithography process. Then, the mask layer 11 to which the pattern of the trench is transferred by anisotropic etching using the resist film as a mask is used. The mask layer has a thickness of about 500 nm made of a laminate of a silicon nitride layer and a silicon oxide layer, for example.
Thereafter, the resist film is removed.

  Next, as shown in FIG. 2B, the trench TR partitioned by the trench wall 10a with respect to the semiconductor substrate 10 by anisotropic etching using the mask layer 11 processed into a trench pattern as a mask. Form. The trench TR is a region that becomes a capacitor.

Next, as shown in FIG. 3A, for example, amorphous silicon containing n-type impurities such as As is deposited on the entire surface covering the inside of the trench TR, and further heat-treated at about 1000 ° C. The first n-type semiconductor layer 12 is formed at a predetermined depth from the inner wall surface of the trench TR by diffusing the type impurities into the inner wall surface layer portion of the trench TR. This becomes the plate electrode PL of the memory capacitor.
Thereafter, the amorphous silicon is removed, and the mask layer 11 is further removed.

  Next, as shown in FIG. 3B, a capacitor insulating film 13 is formed on the inner wall surface of the trench TR by, for example, a CVD (Chemical Vapor Deposition) method or a thermal oxidation method. At this time, the capacitor insulating film 13 is also formed on the upper surface of the trench wall 10a.

Next, as shown in FIG. 4A, the inside of the trench TR is filled with a conductive material that can be insulated by an insulation process and deposited on the entire surface to form a conductive film 14a. In order to completely fill the trench TR, it is deposited about 200 nm higher than the upper end of the trench TR.
Here, a silicon material such as polysilicon is used as the conductive material, and the second n-type semiconductor layer is formed as the conductive film 14a. Such a silicon material can be transformed into silicon oxide which is an insulator by performing an oxidation treatment such as thermal oxidation as an insulation treatment.

Next, as shown in FIG. 4B, the conductive film (second n-type semiconductor layer) 14a is planarized by a CMP (mechanical chemical polishing) method or the like. At this time, only the conductive film 14 a is polished, and there is no damage to the trench wall portion 10 a of the semiconductor substrate 10.
The film thickness D above the upper surface of the trench wall portion 10a of the conductive film 14a left after polishing is an insulating film (oxidized) when an insulation (thermal oxidation) process is performed until the trench wall portion 10a is reached in a subsequent process. The silicon film is determined to have a desired film thickness.

Next, as shown in FIG. 5A, an insulating interlayer 15 is formed by insulating from the upper surface of the conductive film 14a until reaching the trench wall 10a.
For example, when polysilicon is used as the conductive film 14a, a silicon oxide film is formed by an oxidation process such as thermal oxidation, and the processing time is determined by the film thickness D above the upper surface of the trench wall 10a. The capacitor insulating film 13 on the upper portion of the trench wall 10 a is integrated with the interlayer insulating film 15.
At this time, the upper surface of the trench wall portion 10a and the lower surface of the interlayer insulating film 15 are in contact with each other with the width of the trench wall portion 10a, and the second n-type semiconductor layer 14 that is the storage node electrode MN of the adjacent trench is sufficiently electrically connected. Can be separated.

Next, as shown in FIG. 5B, for example, a third n-type semiconductor layer made of crystalline silicon having a thickness of 50 to 150 nm is formed on the interlayer insulating film 15 by a method similar to the method of forming an SOI substrate. 16 is formed.
That is, for example, the second silicon semiconductor substrate is bonded onto the interlayer insulating film 15 to leave a crystalline silicon layer having a desired film thickness, and from the surface opposite to the bonded surface of the second semiconductor substrate. A method of grinding and polishing, or by injecting hydrogen into the second silicon semiconductor substrate to a predetermined depth in advance, bonding the same onto the interlayer insulating film 15 in the same manner as described above, and dividing it in the hydrogen introduction region by heat treatment Depending on the method of leaving the crystalline silicon layer.

Next, as shown in FIG. 6A, an element isolation insulating film 17 is formed by the STI method.
That is, for example, the third n-type semiconductor layer 16 in the element isolation region is removed by etching using an etching gas configured to selectively remove silicon and stop at the silicon oxide, and is generated by removal. An insulator such as silicon oxide is embedded in the opening, and the insulator outside the opening is removed by a polishing process or the like.
The active region AA isolated by the element isolation insulating film 17 is disposed so as to be located above the trench TR.

Next, as shown in FIG. 6B, a fourth semiconductor layer 18 (storage node contact) that contacts the second n-type semiconductor layer 14 (storage node electrode MN) from the surface of the third n-type semiconductor layer 16 is formed. .
Here, a contact hole reaching the second n-type semiconductor layer 14 (storage node electrode MN) is formed so that the side surface of the third n-type semiconductor layer 16 is exposed in the boundary region between the third n-type semiconductor layer 16 and the element isolation insulating film 17. The opening is formed by filling a contact hole with a conductive material such as polysilicon.
As a result, the second n-type semiconductor layer 14 (storage node electrode MN) and the third n-type semiconductor layer 16 (specifically, the source / drain region of the MOSFET formed in a later step) are connected to the fourth semiconductor layer 18 (storage node contact). ).

Further, after introducing channel impurities or the like for well formation or threshold adjustment, and performing necessary heat treatment, an insulating film is formed with a gate (not shown) by thermal oxidation or the like, and a gate electrode 19 is formed thereon, Source / drain regions are formed by ion implantation of impurities using the gate electrode 19 as a mask.
Here, one source / drain region is formed to be connected to the fourth semiconductor layer 18 (storage node contact) as described above, and a bit contact 20 is formed to the other source / drain region. Connect to bit line which is upper layer wiring.
As described above, the DRAM having the structure shown in FIG. 1A can be manufactured.

  According to the above-described DRAM manufacturing method according to the present embodiment, the trench is buried with the conductive material to be insulated by the insulation process, and the insulation process is performed on the conductive film from the upper surface until reaching the upper surface of the trench wall. Therefore, the upper surface of the trench wall and the lower surface of the interlayer insulating film are in contact with each other with the width of the trench wall, and the storage node electrodes of the adjacent trenches can be sufficiently electrically separated.

Further, in the above-described insulating treatment process, the process of forming the interlayer insulating film for bonding to the semiconductor layer and the separation of the storage node electrode between the trenches can be performed simultaneously, and the process can be simplified.
Further, in the conventional DRAM, since the mask layer is left, the portion corresponding to the mask layer on the inner wall of the trench does not contribute to the storage capacity. However, in the trench of the memory capacitor of the DRAM of this embodiment, Since the mask layer is removed, the entire inner wall of the trench contributes to the storage capacity, and more storage capacity can be secured with respect to the trench depth.

The present invention is not limited to the above description.
For example, the material of the storage node electrode may be a conductive material that can be insulated by an insulation treatment such as oxidation, and is not limited to a silicon-based material.
In addition, various modifications can be made without departing from the scope of the present invention.

  The method for manufacturing a semiconductor memory device of the present invention can be applied to a method for manufacturing a DRAM whose capacity has been increased and miniaturized.

  The semiconductor memory device of the present invention can be applied as a DRAM whose capacity has been increased and miniaturized.

1A is a cross-sectional view of a memory cell of a DRAM according to an embodiment of the present invention, FIG. 1B is a plan view, and FIG. 1A is an XX in FIG. It corresponds to the cross-sectional view in '. FIG. 1C corresponds to an enlarged view of a Y portion in FIG. FIG. 2A and FIG. 2B are cross-sectional views showing the manufacturing process of the DRAM manufacturing method according to the embodiment of the present invention. FIG. 3A and FIG. 3B are cross-sectional views showing the manufacturing process of the DRAM manufacturing method according to the embodiment of the present invention. 4A and 4B are cross-sectional views showing the manufacturing process of the DRAM manufacturing method according to the embodiment of the present invention. FIG. 5A and FIG. 5B are cross-sectional views showing the manufacturing process of the DRAM manufacturing method according to the embodiment of the present invention. FIG. 6A and FIG. 6B are cross-sectional views showing the manufacturing process of the DRAM manufacturing method according to the embodiment of the present invention. 7A is a cross-sectional view of a memory cell of a DRAM according to the first conventional example, FIG. 7B is a plan view, and FIG. 7A is an XX ′ line in FIG. 7B. Corresponds to a cross-sectional view in FIG. 8A is a cross-sectional view of a memory cell of a DRAM according to the second conventional example, FIG. 8B is a plan view, and FIG. 8A is an XX ′ line in FIG. 8B. Corresponds to a cross-sectional view in FIG. FIG. 8C corresponds to an enlarged view of a Y portion in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 10a ... Trench wall part, 11 ... Mask layer, 11a ... Silicon nitride layer, 11b ... Silicon oxide layer, 12 ... 1st n-type semiconductor layer, 13 ... Capacitor insulating film, 14 ... 2nd n-type semiconductor layer, 14a ... conductive film (second n-type semiconductor layer), 15 ... interlayer insulating film, 16 ... third n-type semiconductor layer, 17 ... element isolation insulating film, 18 ... fourth semiconductor layer, 19 ... gate electrode, 20 ... bit contact, DESCRIPTION OF SYMBOLS 100 ... Semiconductor substrate, 101 ... 1st n-type semiconductor layer, 102 ... 2nd n-type semiconductor layer, 103 ... Capacitor insulating film, 104 ... 3rd n-type semiconductor layer, 105 ... Element isolation insulating film, 106 ... 4th semiconductor layer, 107 ... Gate electrode 108. Bit contact PL PL plate electrode MN Storage node contact AA Active region TR Trench

Claims (6)

A method of manufacturing a semiconductor memory device in which a plurality of memory cells each having a memory capacitor having a storage node electrode and a transistor are arranged,
Forming a mask layer that opens in a pattern in which a plurality of trenches are arranged in a substrate;
Using the mask layer as a mask, forming a plurality of trenches partitioned by trench walls on the substrate; and
Removing the mask layer;
Forming a plate electrode from the inner wall surface of the trench to a predetermined depth;
Forming a capacitor insulating film by covering the inner wall surface of the trench;
A step of filling the trench through the capacitor insulating film with a conductive material that is insulated by an insulation treatment, and forming a conductive film so as to be thicker than the depth of the trench;
Isolating the conductive film from the top surface until reaching the top surface of the trench wall and separating the conductive film into storage node electrodes for each trench while forming an interlayer insulating film;
Forming a semiconductor layer on the interlayer insulating film. A method for manufacturing a semiconductor memory device. In the step of forming an interlayer insulating film by performing an insulating process on the conductive film from the upper surface, the upper surface of the trench wall portion and the lower surface of the interlayer insulating film are formed in contact with each other with a width of the trench wall portion. Item 14. A method for manufacturing a semiconductor memory device according to Item 1. After the step of forming the semiconductor layer,
Forming a gate insulating film on the surface of the semiconductor layer;
Forming a gate electrode on the gate insulating film;
The method of manufacturing a semiconductor memory device according to claim 1, further comprising: forming a source / drain region in the semiconductor layer on both sides of the gate electrode. After the step of forming the semiconductor layer,
Opening a contact hole reaching the storage node electrode from the surface of the semiconductor layer;
The method of manufacturing a semiconductor memory device according to claim 1, further comprising: filling the contact hole with a conductive material, and connecting the storage node electrode and the semiconductor layer. As a conductive material to be insulated by the insulation treatment, silicon is used.
The method for manufacturing a semiconductor memory device according to claim 1, wherein in the insulating process, an oxidation process is performed to form silicon oxide. A semiconductor memory device in which a plurality of memory cells each having a memory capacitor having a storage node electrode and a transistor are arranged,
A substrate in which a plurality of trenches partitioned by trench walls are formed side by side;
A plate electrode formed at a predetermined depth from the inner wall surface of the trench;
A capacitor insulating film formed to cover the inner wall surface of the trench;
A storage node electrode formed by burying the trench through the capacitor insulating film;
An interlayer insulating film formed over the entire surface covering the substrate and the storage node electrode;
A semiconductor layer formed on the interlayer insulating film and having the transistor formed thereon;
An upper surface of the trench wall and a lower surface of the interlayer insulating film are in contact with each other with the width of the trench wall.

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