JP2005203400A - Simulation method of semiconductor device, device simulation method of semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a simulation method capable of precisely estimating imager characteristics to a micro-imager. <P>SOLUTION: The first analysis of AS implantation is made by a two-dimensional Monte Carlo simulation (step S1), a second analysis is made for analyzing an impurity profile after a thermal process by two-dimensional thermal diffusion simulation with the first analysis results 100, 200 as input information (step S2), a diffusion calculation is made based on a Gaussian function on the basis of the second analysis result 400 to obtain the impurity profile after three-dimensional thermal diffusion (step S3), and the impurity profile is set after the three-dimensional thermal diffusion to be input information, and the device simulation of a semiconductor device is made using a physical model, thus precisely estimating the characteristics of the imager to the micro-imager. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device such as a CCD imaging device, and more particularly to a semiconductor device simulation method and a semiconductor device device simulation method for analyzing characteristics of the semiconductor device.

  At present, a photoelectric conversion device such as a CCD image pickup device is miniaturized, and accordingly, it is difficult to secure individual device characteristics. In particular, securing the maximum accumulated charge amount of the photodiode and the vertical CCD, the reduction of smear, the reduction of the shutter voltage, the reduction of the readout voltage, and the like accompanying the miniaturization are problems that must be solved every time miniaturization is performed.

  FIG. 6 is a cross-sectional view showing a conventional configuration example of a solid-state imaging device. In the solid-state imaging device, a P well 65 is formed on an N substrate 60, and a photodiode unit 1 including an N layer 66 and a vertical CCD unit 3 including an N layer 69 are formed in the P well 65. The photodiode unit 1 and the vertical CCD unit 3 are separated by a transfer gate unit 2 that reads charges from the photodiode unit 1 to the vertical CCD unit 3, and the photodiode unit 1 is partitioned by a channel stop unit 4. The photodiode portion 1 has a structure in which dark current is reduced by the p + layer 67 on the surface.

  In the vertical CCD unit 3, a p layer 68 is provided under the n layer 69 to increase the transfer charge amount and reduce smear. The transfer gate unit 2 performs control for transferring charges from the photodiode unit 1 to the vertical CCD unit 3. The transfer electrode portion formed via the silicon oxide film (insulating film) 64 has a transfer electrode 63. The transfer electrode 63 is covered with a light shielding film 62 such as aluminum or tungsten via an insulating film 64, and the light shielding film 62 is opened on the photodiode unit 1. The light shielding film 62 is coated with a cover film 70 made of a silicon oxide film 64 such as PSG, on which a planarizing layer 71 is formed, and a microlens 72 that collects light on the photodiode portion 1 is disposed thereon. ing. Light is incident on the photodiode portion 1 formed on the surface of the semiconductor substrate, and a video signal is obtained by signal charges generated in the photodiode portion 1.

  Here, the maximum accumulated charge amount of the photodiode unit 1 is the maximum charge amount accumulated by photoelectric conversion, and the maximum accumulated charge amount of the vertical CCD unit 2 can be transferred within the region of the vertical transfer element. This is the maximum charge amount. The read voltage indicates a minimum voltage value applied to the read electrode for reading all charges from the photodiode unit 1 to the vertical CCD unit 3. Further, the shutter voltage is an N substrate in a system in which charges are photoelectrically converted in the photodiode unit 1 and discharged to the substrate 60 with the N substrate 60 at a potential of about 20 V in order to discharge the charge to the substrate outside the desired storage time. A voltage for setting 60 to a desired potential is shown.

By the way, in order to solve the problem of the characteristics of the image sensor due to miniaturization, a device simulation for experimentally creating the operation of a semiconductor device by numerical analysis (for example, refer to Patent Document 1) or a simulation of a photoelectric conversion device is performed. Used. Device simulation is implanted into a semiconductor element, and then using at least a plurality of input parameters including the impurity concentration distribution in the depth direction from the substrate of the impurity profile after multiple thermal processes and the region into which the impurity is implanted, It is a simulation of a photoelectric conversion device that analyzes an electric potential using a physical model such as a Poisson equation or a current continuity type. Based on these simulations, device characteristics are analyzed in advance, and device prototypes and analysis are actually performed based on the analysis results.
JP 2001-308201 A (Page 9, FIG. 1)

  However, an important item when analyzing and examining the characteristics of the photoelectric conversion device in advance by conventional device simulation is the accuracy of the device simulation. Strict simulation accuracy is required with shrinking devices, but there are the following difficult problems to meet this. In particular, in the image pickup device, the following two points are factors that detract from accuracy due to device shrinkage.

  (1) As the device shrinks, the effective photodiode maximum charge amount tends to decrease due to horizontal diffusion in the Pwell or P + region. In particular, in a structure of 3 micron-cell CCD or less, the maximum charge amount tends to decrease due to the narrow channel effect due to the Pwell or P + region. In order to perform a high-precision simulation, it is necessary to capture not only the one-dimensional distribution in the depth direction but also the two-dimensional expansion in the horizontal direction as input data, after the thermal process of each implanted impurity. .

  However, a potential profile of an image sensor such as a CCD that is different from a simple structure such as a MOS is formed from a source, a drain, and a gate as shown in FIG. Since the thermal process for such a complex structure is performed by a combination of annealing, oxidation, etc., multiple times, if a three-dimensional semiconductor diffusion process simulation is performed for such a thermal process, the calculation time and the like are reduced. It takes too much to execute. Therefore, in the conventional simulation, even if the impurity distribution in the depth direction can be obtained, the impurity distribution in the horizontal direction cannot be obtained, and input information assuming that the impurity diffusion ratio in the depth direction / horizontal direction is 1. Since the device simulation was performed based on the analysis, the analysis accuracy was poor.

  (2) With the miniaturization (shrink) of the device, the mask shape at the time of design and the resist shape at the time of implantation tend to shift. In particular, a corner portion in the mask shape is rounded in the resist at the time of implantation. Furthermore, the photoelectric conversion unit of the CCD image pickup device injects MeV class N-type impurities in order to take in the charge photoelectrically converted in the deep region into the photodiode. For this reason, unlike a resist used for an element such as a MOS, a resist having a thickness of several microns is used, which is a further factor that shifts the resist shape from the mask shape. The resist shape shown in 27 of FIG. 3B is an example, and it can be seen that the shape at the corner is rounded after the lithography simulation. Conventionally, the lithography simulation is not performed, and the CAD / CAM information at the time of design is used. Since the device simulation was performed using this mask shape, only the analysis with poor accuracy could be performed.

  (3) In miniaturization of the CCD, in order to prevent punch-through from the photodiode unit 1 to the vertical CCD unit 3, the concentration of the P well 65 tends to increase. However, when the density is increased, the read voltage is increased. For this reason, the optimum design is performed by finely adjusting the tilt angle and the rotation angle at the time of implantation of the N-type impurity in the P + region or the photodiode 1.

  Here, in the actual semiconductor diffusion process simulator, from the profile extracted from SIMS or the like, the average projection range (Rp) which is a temporary moment and the standard deviation when the Rp corresponding to the second moment is averaged, Rp, When the channeling region is approximated by a similar function, the AS implant profile is analyzed based on an implant model that extracts a required value from a table (implant data) composed of 2Rp and its standard deviation, 2Rp, etc. Yes. In this method, it is difficult to accurately estimate the fluctuation of channeling depending on the tilt angle and the rotation angle from the implant data, and further, deviation due to interpolation has occurred.

  The present invention has been devised in view of the above circumstances, and an object of the present invention is to enable highly accurate estimation of photoelectric conversion element characteristics for a fine photoelectric conversion element, and before actually making a prototype. Semiconductor device simulation method and semiconductor device capable of providing a highly accurate simulation capable of providing an environment for performing highly accurate analysis, and thus contributing to improvement in photoelectric conversion characteristics as well as reduction in trial production costs And a semiconductor device manufactured using these simulation methods.

  In order to achieve the above object, the present invention uses a first analysis step for analyzing an AS implant by two-dimensional Monte Carlo simulation and a parameter extracted from an AS implant impurity distribution that is an analysis result of the first analysis step. The second analysis step for analyzing the impurity profile after the thermal process by two-dimensional thermal diffusion simulation and the diffusion ratio of the impurity concentration in the horizontal / depth direction as the analysis result of the second analysis step Based on the above, an extension step for obtaining an impurity profile after three-dimensional thermal diffusion by performing an extension calculation based on a Gaussian function of the impurity concentration in the horizontal direction is provided.

  The present invention also provides a first analysis step for analyzing an AS implant by two-dimensional Monte Carlo simulation, and a thermal process by two-dimensional thermal diffusion simulation using parameters extracted from the analysis result of the first analysis step. Based on the second analysis step for analyzing the impurity profile later and the diffusion ratio of the impurity concentration in the horizontal / depth direction as the analysis result of the second analysis step, the impurity concentration in the horizontal direction An extension step for obtaining an impurity profile after three-dimensional thermal diffusion by performing an extension calculation based on a Gaussian function, a parameter extracted from the obtained impurity profile after three-dimensional thermal diffusion, and separately provided, at least The parameters including the impurity implantation region information are used as input information, and the physical model is used for the semiconductor. Characterized by comprising the semiconductor device analyzing step of performing a device simulation for analyzing gas properties.

  As described above, in the semiconductor device simulation method of the present invention, AS implantation (a profile in which thermal diffusion is not performed immediately after impurity (for example, arsenic) injection) is analyzed by two-dimensional Monte Carlo simulation, and from the impurity concentration distribution information obtained by this analysis. Analyzing the impurity profile after the thermal process as a two-dimensional thermal diffusion simulation using the extracted parameters as input information, and obtaining the impurity concentration distribution information after the thermal process by this analysis, the horizontal / depth By obtaining the diffusion ratio of the impurity concentration in the vertical direction, and performing an extended calculation based on the Gaussian function of the impurity concentration in the horizontal direction based on the diffusion ratio of the impurity concentration to obtain the impurity profile after three-dimensional thermal diffusion, Fine structure that was difficult to analyze with conventional 3D simulators Which enables analyzed by 2-dimensional process simulation of a two-step process simulation, such as a photoelectric conversion element having. Moreover, since the analysis result is converted into three-dimensional analysis information by extended calculation based on a Gaussian function, highly accurate three-dimensional process simulation for a photoelectric conversion element having a fine structure can be performed within a practical time. be able to. Further, device simulation using the analysis result of this high-accuracy three-dimensional process simulation as input information is performed on, for example, a miniaturized photoelectric conversion element, and the accuracy of, for example, electric potential characteristics obtained as a result is improved. it can. Accordingly, it is possible to estimate the photoelectric conversion element characteristics with high accuracy in advance, and it is possible to provide an environment in which the semiconductor element is analyzed with high accuracy before actual trial manufacture.

  According to the present invention, the impurity implantation region information, which is one of the separately given parameters, is the opening shape information obtained by analyzing the resist shape when the impurity is implanted into the semiconductor device by lithography process simulation. Features.

  As described above, in the semiconductor device simulation method according to the present invention, the input shape information of the semiconductor device device simulation includes the above-described highly accurate three-dimensional process simulation analysis result and the resist shape when the impurity is implanted into the semiconductor device. Since highly accurate aperture shape information obtained by analysis by lithography process simulation is used, the accuracy of, for example, electric potential characteristics, which is a device simulation result of the photoelectric conversion element, can be further improved.

  In addition, the present invention analyzes the electrical characteristics of a semiconductor using a physical model, using as input information a parameter extracted from the impurity profile after thermal diffusion and a parameter that is provided separately and includes at least impurity implantation region information. An impurity implantation region information, which is one of the separately given parameters, is obtained by analyzing a resist shape when implanting impurities into the semiconductor device by lithography process simulation. It is characterized by being information.

  As described above, in the device simulation method of the semiconductor device of the present invention, a highly accurate opening shape obtained by analyzing the resist shape when the impurity is implanted into the semiconductor device by lithography process simulation as input information of the device simulation of the semiconductor device. Since information is used, the accuracy of, for example, electric potential characteristics, which are device simulation results of photoelectric conversion elements, can be improved.

  Further, the present invention analyzes the AS implant by two-dimensional Monte Carlo simulation, analyzes the impurity profile after the thermal process by two-dimensional thermal diffusion simulation using the parameters extracted from the analysis result of this analysis step, Using the diffusion ratio of the impurity concentration in the horizontal / depth direction, which is the analysis result of this analysis step, an extended calculation of the impurity concentration in the horizontal direction based on a Gaussian function is performed to calculate the impurity profile after three-dimensional thermal diffusion. The parameter extracted from the calculated impurity profile after the three-dimensional thermal diffusion and the parameter, which is separately provided and includes at least the impurity implantation region information, are used as input information, and the electrical characteristics of the semiconductor are determined using a physical model. Analyze electrical characteristics obtained by device simulation of semiconductor devices Characterized in that it is produced using the prior information to be optimized.

  As described above, in the semiconductor device of the present invention, the actual semiconductor device is obtained based on the characteristic information such as the electrical potential of the semiconductor device obtained by performing the device simulation using the analysis result of the highly accurate three-dimensional process simulation as input information. Prototyping or manufacturing can be performed, so that the intended semiconductor device can be manufactured in a short period of time, and at the same time, the cost of prototyping can be reduced and a method that contributes to the improvement of photoelectric conversion characteristics can be predicted early by simulation. It becomes possible to do.

According to the present invention, analysis of an AS implanter by two-dimensional Monte Carlo simulation is performed in the first analysis, and analysis of an impurity profile after a thermal process is performed by two-dimensional thermal diffusion simulation using the first analysis result as input information. The second analysis result is expanded based on a Gaussian function to obtain a three-dimensional thermal diffusion impurity profile, parameters extracted from the three-dimensional thermal diffusion impurity profile, and In order to perform device simulation of a semiconductor device using a physical model using as input information at least separately provided parameters including impurity implantation region information, it is possible to estimate the characteristics of photoelectric conversion elements with high accuracy and Highly accurate simulation that can provide an environment for highly accurate analysis It is possible to provide a. Therefore, it is possible to contribute to the improvement of the photoelectric conversion characteristics as well as the reduction of the trial production cost, and it is possible to predict the method contributing to the improvement of the photoelectric conversion characteristics at an early stage.
In addition, as input information for device simulation of the semiconductor device, together with the analysis result of the above-described highly accurate three-dimensional process simulation, the accuracy of the accuracy obtained by analyzing the resist shape when the impurity is implanted into the semiconductor device by the lithography process simulation is obtained. Since high aperture shape information is used, for example, the accuracy of, for example, electric potential characteristics, which is a device simulation result of a photoelectric conversion element, can be further improved.

  It is possible to perform highly accurate simulations that enable highly accurate estimation of photoelectric conversion device characteristics for minute photoelectric conversion devices and provide an environment for performing high-precision analysis before actual trial manufacture. Therefore, the purpose of contributing to the improvement of photoelectric conversion characteristics as well as the reduction of the prototype cost is to perform the analysis of the AS implant by the two-dimensional Monte Carlo simulation in the first analysis, and use the first analysis result as the input information for the two-dimensional Analysis of the impurity profile after the thermal process by thermal diffusion simulation is performed in the second analysis, and the second analysis result is expanded based on a Gaussian function to obtain an impurity profile after three-dimensional thermal diffusion. Separately extracted parameters including parameters extracted from the impurity profile after three-dimensional thermal diffusion and at least impurity implantation region information It was achieved by performing a device simulation of the semiconductor device using a physical model and a meter as input information.

  FIG. 1 is a diagram showing a flow of a semiconductor device simulation method according to the first embodiment of the present invention. The semiconductor device simulation method of the present embodiment mainly includes a process simulation of stages (A) to (C) and a device simulation of stage (D).

  Next, the simulation operation in each stage of this embodiment will be described. First, at stage (A), AS implant (profile without thermal diffusion immediately after impurity (for example, arsenic) implantation) analysis in the semiconductor by ion implantation by two-dimensional Monte Carlo simulation is performed (step S1). Then, the one-dimensional AS implant profile 100 in the depth direction, which is the analysis result, and the diffusion ratio 200 in the horizontal / depth direction at the time of AS implantation are extracted.

  Here, in the above-described two-dimensional Monte Carlo simulation, parameters extracted from the AS implant impurity distribution or the impurity profile at the time of AS implant are injected with individual blunt atoms or factors corresponding thereto, The standard deviation when the average projection range (Rp) and the Rp corresponding to the second moment are averaged by obtaining the diffusion distance due to the energy loss of individual impurity atoms by the stopping power such as nuclear stopping power. When Rp and the channeling region are approximated by a similar function, 2Rp and its standard deviation 2Rp are analyzed. By performing such a two-dimensional Monte Carlo simulation, analysis of the impurity profile during AS implantation is performed without depending on channeling fluctuations depending on the tilt angle and rotation angle and without fear of deviation due to interpolation. Can do.

  In the stage (B), after the thermal process by the two-dimensional thermal diffusion simulation, using the one-dimensional AS implant profile 100 in the depth direction obtained in the stage (A) and the horizontal / depth diffusion ratio 200 in the AS implantation. The impurity profile is analyzed (step S2), and the depth-wise one-dimensional thermal profile 300 after the thermal process and the horizontal / depth diffusion ratio 400 after the thermal process are extracted. .

  (C) In the stage, based on the impurity profile 300 after the one-dimensional thermal process in the depth direction and the horizontal / depth diffusion ratio 400 after the thermal process, which are the analysis results, the level of the impurities is calculated using a Gaussian function. The direction distribution is expanded (step S3), and three-dimensional impurity information (horizontal / depth direction diffusion ratio, etc.) after thermal diffusion is extracted.

  In the (D) stage, the impurity information 500 after the three-dimensional thermal diffusion obtained in the (C) stage, electrode information and substrate information of a semiconductor to be subjected to device simulation separately provided, and a region where impurities are implanted into this semiconductor are shown. Using the mask information 600 as an input parameter, an electrical potential analysis of the image sensor or the like is performed using a physical model such as a Poisson equation or a current continuity type (step S3) to obtain electrical potential information (generally electrical characteristic information) of the image sensor. .

  An example of a two-dimensional thermal diffusion simulator is SUPREM4 (Uses Manual of TSUPREM-4 Version 98.4). As an example of the expansion method based on the Gaussian function in step S3, there is an expansion method based on the following calculation.

  Note that Dose is determined based on the following equation (3).

  Next, FIG. 2A illustrates a method of extracting parameters used in the device simulation from the impurity profile 300 after the one-dimensional thermal process in the depth direction obtained by the analysis of the stage B in FIG. FIG. FIG. 2 (2) is a diagram for explaining the horizontal / depth diffusion ratio 400 after the thermal process. FIG. 2A shows an impurity profile in the depth direction, and FIG. 2B shows an impurity profile in the horizontal direction at the depth of the impurity peak concentration position. The region on the right side from what is depicted as the resist 30 in FIG. 2B is an implantation region for actual impurities and the like.

  First, in FIG. 2A, the depth a at the peak concentration and the depth c at which the concentration ratio b is 1/10 at a deeper position are obtained. Further, in FIG. 2 (2), the position closest to the edge of the resist 30 at the depth of the peak concentration in FIG. 2 (1) and where the impurity concentration begins to attenuate, and the horizontal direction where the concentration becomes 1/10 from this position. The distance d is obtained. Although the density ratio b is 1/10 this time, any value may be used for the parameter of the density ratio b.

  Using this concentration ratio b and parameter d, a desired three-dimensional impurity profile 500 can be obtained by performing horizontal diffusion based on a Gaussian distribution by a two-dimensional thermal diffusion simulator in the stage (C) of FIG. it can.

  4 and 5 are diagrams showing the results of analysis according to the above embodiment. 4 and 5 show the results of analysis using a 3.125 μm Locell, FIG. 4 shows the readout voltage, and FIG. 5 shows the analysis result of the shutter voltage. New1 shows a simulation result according to the first embodiment described above. In New1, (ca) and d are extracted from all impurities. CON is the result of the conventional simulation method, and the implantation region was analyzed assuming that the diffusion of impurities after thermal diffusion is isotropic as the shape of the mask, i.e., d / (c−a) = 1.

  As shown in FIGS. 4 and 5, the electric potential value NEW1 obtained by the simulation according to the present embodiment is closer to the measured value EXP than the electric potential value COV obtained by the conventional simulation method. It can be seen that the accuracy of the simulation is improved.

  According to the present embodiment, the impurity profile 500 after three-dimensional thermal diffusion is obtained by the process simulation from the stage (A) to the stage (C), and the highly accurate depth / horizontal impurity extracted therefrom. By inputting the diffusion ratio as a parameter for (D) stage device simulation, a semiconductor obtained by device simulation is compared to the conventional case where the diffusion ratio of impurities in the depth / horizontal direction is assumed to be 1 (here, The accuracy of the electric potential of the imaging element) can be improved. Therefore, since it is possible to estimate with high accuracy such as before manufacturing of the semiconductor element by such high accuracy device simulation, it is possible to secure the maximum accumulated charge amount of the photodiode and the vertical CCD accompanying the miniaturization, reduce smear, Various problems such as reduction of shutter voltage and reduction of readout voltage can be solved easily and in a short time.

  In the above embodiment, the diffusion ratio of the impurities in the horizontal / depth direction after the thermal process is obtained by a two-dimensional Monte Carlo simulation and a two-dimensional thermal diffusion simulation, both of which are two-dimensional simulations. Simulation can be performed in a short time even for a semiconductor having a complicated structure such as an image sensor. Thereby, it is possible to estimate the characteristics of the image sensor with high accuracy by performing a high-accuracy simulation with respect to a fine image sensor, and it is possible to provide an environment for performing high-accuracy analysis before actually making a prototype. Therefore, it is possible to predict a method that contributes to improvement of the imaging characteristics at an early stage as well as to reduce the trial production cost.

  By the way, when performing the device simulation of the (D) stage of the first embodiment described above, the CAD / CAM stage mask information is used in the input information indicated by 600. However, the resist shape deviates from the mask shape. Therefore, the accuracy of the simulation result according to the first embodiment is reduced accordingly. This is solved by the lithography process simulation described in the second embodiment described below.

  FIG. 3 is a diagram showing a lithography process simulation flow of a photoelectric conversion apparatus for obtaining input information used in the device simulation method for a semiconductor device according to the second embodiment of the present invention. In the lithography process simulation according to the present embodiment, an actual implantation region when an impurity is implanted into a semiconductor is obtained by simulation, and ProIith manufactured by KLA Tencer is used as the simulation.

  In FIG. 3A, the lithography process simulation of the present embodiment is performed in the following manner: an aerial simulation (Aerial simulation) in Step S11; a standing wave simulation in Step S12; and a thermal process and a melting process in Step S13. It consists of simulation (Thermal process and development simulation).

  First, in the aerial simulation of step S11, an optical image is calculated based on the optical conditions (wavelength / lens NA / σ) of the stepper and mask data. An image of this simulation is shown in FIG. 3B. The mask pattern 21 is irradiated with the laser beam 40 from above, and the laser beam transmitted through the mask pattern 21 is condensed by the lens 22 to be mask pattern 21. An optical image 23 corresponding to is obtained.

  Next, in the standing wave simulation in step S12, the standing wave generated in the resist film is calculated to obtain the light intensity that contributes to the dissolution of the resist soot. An image corresponding to this simulation is shown in FIG. 3B, and light intensity contributing to dissolution of the resist wave of the standing wave 26 in the resist film 25 formed on the substrate 24 is obtained.

  Finally, in the thermal process and dissolution process simulation in step 13, the final process is performed as shown in FIG. 3B by calculating the dissolution process between the thermal process and the alkaline developer.

  The analysis result (electric potential) for the image pickup device when the resist shape obtained by the lithography process simulation as described above is used as input information for device simulation in the conventional simulation method is a value indicated by New2 in FIGS. It is. 4 and 5 are closer to New2 than C0V with respect to the voltage value of the actual measurement value EXP, indicating that a highly accurate simulation can be realized.

  In the present embodiment, the final resist shape is analyzed by lithography process simulation to accurately determine the impurity implantation region, and this information is used to perform device simulation using a conventional method (the implantation region is a region after thermal diffusion). By performing isotropic that the spread of impurities is the same as the shape of the mask, that is, (analysis is performed with (ac) / d = 1), it is possible to perform device simulation with higher accuracy than in the past.

  A semiconductor simulation method according to the third embodiment of the present invention will be described below. In the simulation method of the present embodiment, the mask shape obtained by the lithography process simulation of the second embodiment is used as input information when performing the device simulation shown in the stage (D) of the first embodiment. Since this is a simulation method, its flow diagram is the same as FIG.

  The electric potential obtained by the analysis in this embodiment is indicated by New3 in FIGS. FIG. 4 shows the readout voltage, and FIG. 5 shows the analysis result of the shutter voltage. New2 shows a simulation result according to the second embodiment. 4 and 5 that the voltage of New3 is the closest to the actual measurement value EXP, it can be seen that a very accurate simulation is performed.

  According to the present embodiment, since a three-dimensional thermal diffusion profile is used as input information for device simulation and resist shape information obtained by lithography process simulation is used, a highly accurate device simulation can be performed. As a result, the electric potential of the semiconductor as a result can be a value closest to the actual measurement value.

  In addition, this invention is not limited to the said embodiment, In the range which does not deviate from the summary, it can implement also with another various form in a concrete structure, a function, an effect | action, and an effect. For example, in the above-described embodiment, an example in which the simulation of the present invention is used to analyze a semiconductor device having a complicated structure such as an image sensor is described. However, any semiconductor device having a complicated structure may be used. The same effect can be obtained for this.

It is the figure which showed the flow of the simulation method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is the figure which showed the impurity profile of the depth direction obtained from the two-dimensional thermal diffusion simulation of FIG. 1, and the impurity profile of a horizontal direction. It is the figure which showed the flow of the lithography process simulation of the photoelectric conversion apparatus which calculates | requires the input information used with the device simulation method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is the figure which compared the read voltage which is the analysis result of 1st-3rd Embodiment, the measured value, and the conventional analysis result mutually. It is the figure which compared the shutter voltage which is the analysis result of 1st-3rd Embodiment, the measured value, and the conventional analysis result mutually. It is sectional drawing which showed the example of the conventional structure of the solid-state imaging device.

Explanation of symbols

21 ... Mask pattern, 22 ... Lens, 23 ... Optical image, 24 ... Substrate, 25 ... Resist film, 26 ... Standing wave, 27 ... Resist shape, 30 ... Resist.

Claims (15)

A first analysis step for analyzing an AS implant by two-dimensional Monte Carlo simulation;
A second analysis step for analyzing an impurity profile after a thermal process by a two-dimensional thermal diffusion simulation using a parameter extracted from an AS implantation impurity distribution which is an analysis result of the first analysis step;
Three-dimensional thermal diffusion by performing an extended calculation based on the Gaussian function of the impurity concentration in the horizontal direction based on the diffusion ratio of the impurity concentration in the horizontal / depth direction, which is the analysis result of the second analysis step. An expansion step to determine the later impurity profile;
A method of simulating a semiconductor device, comprising: A first analysis step for analyzing an AS implant by two-dimensional Monte Carlo simulation;
A second analysis step of analyzing an impurity profile after a thermal process by a two-dimensional thermal diffusion simulation using parameters extracted from the analysis result of the first analysis step;
Three-dimensional thermal diffusion by performing an extended calculation based on the Gaussian function of the impurity concentration in the horizontal direction based on the diffusion ratio of the impurity concentration in the horizontal / depth direction, which is the analysis result of the second analysis step. An expansion step to determine the later impurity profile;
The parameter extracted from the obtained impurity profile after the three-dimensional thermal diffusion and the parameter that is separately given and includes at least the impurity implantation region information are used as input information, and the electrical characteristics of the semiconductor are determined using a physical model. A semiconductor device analysis step for performing device simulation to be analyzed;
A method of simulating a semiconductor device, comprising:   The parameters extracted from the AS implantation impurity distribution, which is the analysis result of the first analysis step, are obtained at the time of AS implantation using a semiconductor diffusion process simulator that can analyze at least the impurity concentration in the depth direction and the horizontal direction of the semiconductor. 3. The semiconductor device simulation method according to claim 1, wherein the parameter is extracted from an AS implantation impurity distribution obtained by analyzing an impurity profile.   The parameters extracted from the AS implantation impurity distribution, which is the analysis result of the first analysis step, include at least the impurity distribution in the depth direction and the impurity distribution in the horizontal direction with respect to the substrate during AS implantation. 3. A method for simulating a semiconductor device according to claim 1.   The parameter extracted from the analysis result of the second analysis step is the second analysis performed using the parameter extracted from the analysis result of the first analysis step as input information. 3. The semiconductor device simulation method according to claim 1, wherein the parameter represents a horizontal impurity concentration distribution extracted from the impurity profile.   The parameter representing the impurity concentration distribution in the horizontal direction from the impurity profile after diffusion is such that the depth of the peak concentration in the depth direction is a, deeper than that, and 1 / b (b is a constant) with respect to the peak concentration. D / (c−a) where c is the distance to the depth to be c, and d is the distance from the edge concentration of the implanted region to the outside of the implanted region where the concentration is 1 / b at the depth a. The semiconductor device simulation method according to claim 5, wherein the semiconductor device simulation method is provided.   3. The impurity implantation region information which is one of the separately given parameters is opening shape information obtained by analyzing a resist shape at the time of implanting impurities into a semiconductor device by lithography process simulation. The simulation method of the semiconductor device as described.   In the lithography process simulation, the optical image is calculated based on the optical conditions and mask data of the stepper, and the standing wave generated in the resist film is calculated to obtain the light intensity that contributes to the dissolution of the resist film. 8. The semiconductor device simulation method according to claim 7, further comprising: a step; and a step of calculating a thermal process and a resist dissolution process.   3. The semiconductor device simulation method according to claim 1, wherein the semiconductor device is a photoelectric conversion device that receives light and converts the light into an electric signal. Device simulation of a semiconductor device that analyzes the electrical characteristics of a semiconductor using a physical model, using as input information parameters extracted from the impurity profile after thermal diffusion and parameters that are provided separately and include at least impurity implantation region information A method,
The impurity implantation region information, which is one of the separately given parameters, is opening shape information obtained by analyzing the resist shape when the impurity is implanted into the semiconductor device by lithography process simulation. Device simulation method.   11. The device simulation method for a semiconductor device according to claim 10, wherein the semiconductor device is a photoelectric conversion device that receives light and converts it into an electric signal.   Analyzing the AS implant by two-dimensional Monte Carlo simulation, analyzing the impurity profile after the thermal process by two-dimensional thermal diffusion simulation using the parameters extracted from the analysis result of this analysis step, and the analysis result of this analysis step Using the diffusion ratio of the impurity concentration in the horizontal / depth direction of the impurity, the impurity concentration in the horizontal direction based on a Gaussian function is expanded to obtain a three-dimensional impurity profile after thermal diffusion, and this calculation is performed. A semiconductor device that analyzes electrical characteristics of a semiconductor using a physical model by using, as input information, a parameter extracted from an impurity profile after three-dimensional thermal diffusion and a parameter that is separately provided and includes at least impurity implantation region information Advance information to optimize the electrical characteristics obtained by device simulation Wherein a produced using.   13. The parameter extracted from the AS implant impurity distribution, which is an analysis result of the AS implanter, includes at least the impurity distribution in the depth direction and the impurity distribution in the horizontal direction with respect to the substrate during AS implantation. The semiconductor device described.   The parameter extracted from the analysis result by the two-dimensional thermal diffusion simulation is the second analysis performed by using the parameter extracted from the analysis result of the first analysis step as input information. Diffusion obtained through a heat treatment process 13. The semiconductor device according to claim 12, wherein the semiconductor device is a parameter representing a horizontal impurity concentration distribution extracted from a subsequent impurity profile. 13. The impurity implantation region information which is one of the separately given parameters is opening shape information obtained by analyzing a resist shape at the time of implanting impurities into a semiconductor device by lithography process simulation. The semiconductor device described.

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