JP2005197498A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent operation failure from being generated in a transistor at a peripheral circuit at the boundary to the memory cell of a DRAM. <P>SOLUTION: Light is applied to a negative photoresist film formed on the entire surface of a silicon substrate using a photomask 3 shown in Figure. The photomask 3 has a light-shielding section 31 in which a plurality of rectangular projections 31a project at a prescribed interval at the side of a memory cell region 1 from a line 31L set to a boundary line L1 between a memory cell region 1 and a peripheral circuit region 2. The projections 31a are arranged at positions that oppose the area between adjacent element regions 10 in the columnar direction (along a line in parallel with the line L1). The line 31L at the light-shielding section 31 of the photomask 3 is arranged to the line L1 of the silicon substrate for applying light. When applying light, no condensation in the shape of a wavy line caused by the element regions 10 arranged in an oblique matrix shape is generated. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention has a first region and a second region separated along a straight line, and the first region has elements arranged in a matrix, and the matrix includes rows along the straight line, In particular, the present invention relates to a method of manufacturing a semiconductor device including columns extending obliquely with respect to a straight line, and in particular, photolithography using a negative photoresist for making the second region an impurity diffusion region having a conductivity type different from that of a semiconductor substrate. It relates to the process.

A semiconductor memory device such as a DRAM (Dynamic Random Access Memory) includes a memory cell in which elements are densely arranged in a matrix and a peripheral circuit adjacent thereto.
FIG. 2 is a partial cross-sectional view showing an example of a DRAM and shows a state after the first metal wiring layer forming step. In this DRAM, a region isolation oxide film 12 is formed at the boundary between a region on the silicon substrate 5 where a memory cell is formed and a region where a peripheral circuit is formed. A P (P +) well 16 is formed on the P-type silicon substrate 5 on the memory cell formation region side, and an N well 15 is formed on the peripheral circuit formation region side with the width direction center of the region isolation oxide film 12 as a boundary.

  In the range shown in FIG. 2, in the memory cell formation region, the transistor 6 having source / drain regions 61a and 61b formed by diffusing n-type impurities in the P well 16 and the bit connected to the drain region 61b. A line 71, a capacitor 72 connected to the source region 61a, and a transfer gate line 73 are formed. In the peripheral circuit formation region, a transistor 8 including a source / drain region 81 formed by diffusing a p-type impurity in the N well 15 is formed. Reference numeral 91 denotes a first metal wiring, and reference numeral 92 denotes an interlayer insulating film.

  In recent years, in order to increase the degree of integration, the element regions 10 of the memory cells are arranged as shown in FIG. The line L1 is a straight line (boundary line) that separates the memory cell region and the peripheral circuit region. In the memory cell region 1, a large number of element regions 10 are densely formed in a matrix having lines L2 parallel to the lines L1 as rows and lines L3 extending obliquely with respect to the lines L1 as columns. The element region 11 is formed by using a photolithography technique to thermally oxidize a portion other than the element region 10 of the silicon substrate to form an element isolation oxide film 11. At that time, a region isolation oxide film 12 for separating the memory cell region 1 and the peripheral circuit region 2 is also formed at the same time. The line L4 is a line indicating the end of the region isolation oxide film 12 on the peripheral circuit region 2 side.

After this isolation oxide film forming step, a negative photoresist film is formed on the entire surface of the silicon substrate, and light is applied to the resist film through a photomask 30 that shields the peripheral circuit region as shown in FIG. Irradiate. The light-shielding portion 301 of the photomask 30 has an end formed in a straight line along the boundary line L1 between the memory cell region and the peripheral circuit region.
Thereby, as shown in FIG. 5, a resist pattern in which the resist cured film 4 remains on the memory cell region of the silicon substrate 5 is formed. Next, impurity diffusion is performed through the resist pattern 4. Here, N-type impurities (P: phosphorus) are ion-implanted. As a result, an N well 15 is formed in the peripheral circuit region of the silicon substrate 5 as shown in FIG.

The following Patent Documents 1 and 2 are cited as documents relating to the problems that occur due to the relationship between the memory cell region of DRAM and the peripheral circuit region. Patent Document 3 below describes a technique related to countermeasures for halation of a negative photoresist. However, in any of the documents, there is a memory cell region in which the element region is formed in the arrangement shown in FIG. 3, and a problem that occurs when a cured film of a negative resist is formed in this memory cell region, and a solution to the problem. There is no description.
JP 2000-19709 A JP-A-10-116969 JP 2002-50571 A

However, in a DRAM in which the element region is formed in the memory cell region in the arrangement shown in FIG. 3, malfunction may occur in the transistor at the boundary with the memory cell of the peripheral circuit when manufactured by the method described above. .
The present invention has been made paying attention to this point, and has a first region and a second region separated along a straight line, and elements are arranged in a matrix in the first region, In the method of manufacturing a semiconductor device, in which the matrix includes a row along the straight line and a column extending obliquely with respect to the straight line, the semiconductor element at the boundary of the second region with the first region has a malfunction. The problem is to prevent it from occurring.

  In order to solve the above problems, the present invention has a first region and a second region separated along a straight line, and elements are arranged in a matrix in the first region. A method of manufacturing a semiconductor device comprising a row along a straight line and a column extending obliquely with respect to the straight line, wherein an element isolation oxide film corresponding to each element arrangement is formed in each region of the semiconductor substrate. In addition, an isolation oxide film forming step for forming a region isolation oxide film at the boundary between the two regions, and after the isolation oxide film forming step, a negative photoresist film is formed on the entire surface of the semiconductor substrate, By irradiating light through a photomask that shields the region, a photolithography process for forming a resist pattern in which a resist cured film remains on the first region, and after the photolithography step, the resist pattern is formed. Diffusing impurities of a different conductivity type from the semiconductor substrate into the second region of the semiconductor substrate by performing impurity diffusion on the semiconductor substrate via an impurity, and used in the photolithography process The method of manufacturing a semiconductor device according to claim 1, wherein the light-shielding portion of the photomask has a protruding portion that protrudes toward the first region from the boundary at a position facing each element region adjacent in the row direction. provide.

As a semiconductor device suitably manufactured by the method of the present invention, a DRAM having a memory cell region as a first region and a peripheral circuit region as a second region can be cited.
Next, the operation and effect of the method of the present invention will be described in comparison with the aforementioned manufacturing method.
When the element region 10 is arranged in the arrangement shown in FIG. 3 in the first area (memory cell area in the case of DRAM) 1, the outline line L5 facing the line L1 of the element region 11 is in relation to the boundary line L1. It is in an inclined state. Further, the element region 10 and the element isolation oxide film 11 and the region isolation oxide film 12 have different reflectivities, and the element region 10 has a high reflectivity.

  From these facts, as shown in FIG. 7, when a conventional photomask 30 in which the end portion of the light shielding portion 301 is formed linearly along the line L1, a wavy line as indicated by symbol S in FIG. Condensation tends to occur. That is, light irradiated from the upper side through the photomask 30 to the memory cell region 1 side from the line L1 of the resist film moves laterally in the resist film and is on the peripheral circuit region (second region) side from the line L1. 2 and easily gathers at a position between the line L1 and the line L4 facing each element region 10 adjacent in the row direction (direction parallel to the line L1).

And since the negative resist is used, the edge part of a resist cured film becomes wavy shape with this condensing. That is, as shown by a two-dot chain line in FIG. 6, the end portion 4a of the resist cured film 4 is partially (along the condensing line S in FIG. Rather than the peripheral circuit area side.
When the impurity diffusion step is performed in this state, impurities are not diffused into the lower portion 15a of the region isolation oxide film 12 where the resist cured film 4 on the peripheral circuit region side exists. The peripheral circuit region is an impurity diffusion region having a conductivity type different from that of the semiconductor substrate, but the portion 15a where the impurity is not diffused remains the same conductivity type as the semiconductor substrate. Therefore, the semiconductor element formed in the impurity diffusion region 15 is electrically separated from the semiconductor substrate and the impurity diffusion layer (impurity diffusion layer having the same conductivity type and high concentration as the semiconductor substrate) formed in the memory cell region thereafter. It will not be done.

  According to the method of the present invention, a photomask including a light-shielding portion having a convex portion protruding from the boundary toward the first region side at a position facing each element region adjacent in the row direction is provided on the photomask. By using it in the lithography process, the surface on the first region side is shielded by the convex portion from the portion that is easily condensed as shown in FIG. 7, so that wavy line condensing as shown in FIG. 7 does not occur. Can be.

  Therefore, since the end portion of the resist cured film can be prevented from becoming wavy, the impurity can be diffused over the entire first region and including the lower portion of the region isolation oxide film in the second region. become able to. As a result, the semiconductor element formed in the impurity diffusion region in the vicinity of the region isolation oxide film in the second region has a semiconductor substrate and an impurity diffusion layer formed in the first region thereafter (the same conductivity type as the substrate and having a concentration). Therefore, the semiconductor element can be prevented from malfunctioning because it is electrically separated from the high impurity diffusion layer.

Hereinafter, embodiments of the present invention will be described.
FIG. 1 is a diagram illustrating a photolithography process that constitutes a semiconductor device manufacturing method corresponding to an embodiment of the present invention.
This embodiment is a method for manufacturing a DRAM in which element regions are formed in the arrangement shown in FIG. 3 described in the background art section, and conventionally known methods can be adopted except for the photolithography process.

  First, an element isolation oxide film and a region isolation oxide film are formed on a P-type silicon substrate by a LOCOS (Local Oxidation of Silicon) method or the like. In the memory cell region 1, an element isolation oxide film 11 is formed so that the element region 10 has the shape and arrangement shown in FIG. 3, and a region isolation oxide film 12 is formed at the boundary between the memory cell region 1 and the peripheral circuit region 2. Form.

Next, a negative photoresist film is formed on the entire surface of the silicon substrate, and a photomask 3 is disposed thereon as shown in FIG.
This photomask 3 has a light shielding portion in which a plurality of rectangular protrusions 31a protrude from the line 31L aligned with the boundary line L1 between the memory cell region 1 and the peripheral circuit region 2 toward the memory cell region 1 at a predetermined interval. 31. These convex portions 31a are arranged at positions facing each other between the adjacent element regions 10 in the row direction (along a line parallel to the line L1). This photomask 3 is obtained by forming a chrome pattern in the shape of the light shielding portion 31 on a transparent substrate. The line 31L of the light-shielding portion 31 of the photomask 3 is arranged in accordance with the line L1 of the silicon substrate, and light irradiation is performed.

Thereby, since wavy line condensing like FIG. 7 does not arise, the edge part of a resist cured film does not become wavy line shape. Therefore, as shown in FIG. 5, the entire memory cell region can be covered with the resist cured film 4, and the end portion of the resist cured film 4 can be made linear to match the center position in the width direction of the region isolation oxide film 12.
Next, as shown in FIG. 5, phosphorus (P), which is an N-type impurity, is ion-implanted into the P-type silicon substrate 5 through this resist cured film (resist pattern) 4 (impurity diffusion is performed). . As a result, an N well is formed in the peripheral circuit region. Here, as shown in FIG. 6, since the end 4a of the resist cured film 4 is formed as indicated by a solid line instead of a two-dot chain line, the lower portion of the region isolation oxide film 12 in the peripheral circuit region is included. Further, the N well 15 as designed can be formed by diffusing impurities throughout.

  Next, after removing the resist cured film (resist pattern) 4, a resist pattern covering the peripheral circuit region side is formed. Next, boron (B), which is a P-type impurity, is ion-implanted into the memory cell region 1 of the silicon substrate 5 through this resist pattern, thereby forming the P well 16 shown in FIG. Thereafter, the DRAM is completed by forming each semiconductor element and forming a metal wiring layer in accordance with a conventionally known method.

  In this embodiment, as shown in FIG. 2, the source / drain regions of the transistor 8 are formed in the N well 15 near the region isolation oxide film 12 in the peripheral circuit region. As described above, the N well 15 is formed as designed. As a result, the source / drain regions are electrically isolated from the P-type silicon substrate 5 and the P (P +) well 16. Therefore, it is possible to prevent malfunction of the transistor 8 which has been a conventional problem.

In this embodiment, the photomask 3 in which the convex portions 31a of the light-shielding portion 31 are rectangular is used. Instead, the photomask 3 shown in FIG. 8 may be used.
This photomask 3 has a light shielding portion in which a plurality of triangular protrusions 32a protrude from the line 31L aligned with the boundary line L1 between the memory cell region 1 and the peripheral circuit region 2 toward the memory cell region 1 at a predetermined interval. 32. These convex portions 32a are arranged at positions facing each other between the adjacent element regions 10 in the row direction (along a line parallel to the line L1).

  Even when this photomask 3 is used, a negative photoresist film is formed on the entire surface of the silicon substrate, and the line 32L of the light-shielding portion 32 is aligned with the line L1 of the silicon substrate, as shown in FIG. Then, a photomask 3 is placed and light irradiation is performed. Thereby, since the light condensing as shown in FIG. 7 does not occur, the end portion of the resist cured film does not become wavy. Therefore, as shown in FIG. 5, the entire memory cell region can be covered with the resist cured film 4, and the end portion of the resist cured film 4 can be made linear to match the center position in the width direction of the region isolation oxide film 12.

4A and 4B illustrate a photolithography process according to an embodiment of the present invention. FIG. 6 is a partial cross-sectional view showing an example of a DRAM. The top view which shows the highly integrated arrangement | sequence of the element area | region in a memory cell. The top view which shows the light irradiation process by the conventional photomask. Sectional drawing explaining an impurity diffusion process. Sectional drawing explaining the state after an impurity diffusion process, and the subject of this invention. The top view explaining the wavy line condensing in a photolithography process. The figure which shows the example using the photomask different from FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory cell area | region (1st area | region), 10 ... Element area | region, 11 ... Element isolation oxide film, 12 ... Area isolation oxide film, 15 ... N well, 16 ... P (P +) well, 2 ... Peripheral circuit area | region ( 2nd region), 3 ... Photomask, 31 ... Light-shielding part, 31a ... Projection of light-shielding part, 4 ... Resist cured film (resist pattern), 5 ... Silicon substrate, 6 ... Transistor, 71 ... Bit line, 72 ... Capacitor 73 ... Transfer gate line 8 ... Transistor 91 ... First metal wiring 92 ... Interlayer insulating film L1 ... Boundary line between memory cell region and peripheral circuit region (separating first region and second region) L2... Line indicating the row of the element region matrix, L3... Line indicating the column of the element region matrix, L4... The end of the region isolation oxide film on the peripheral circuit region (second region) side. Line, L5 ... Element Contour line of the band.

Claims (2)

A first region and a second region separated along a straight line, and elements are arranged in a matrix in the first region, the matrix being arranged along a line along the straight line and the straight line A method of manufacturing a semiconductor device comprising diagonally extending rows,
Forming an isolation oxide film corresponding to each element arrangement in each region of the semiconductor substrate, and forming an isolation oxide film at a boundary between the two regions; and
After this isolation oxide film formation step, a negative photoresist film is formed on the entire surface of the semiconductor substrate, and light is irradiated through a photomask that shields the second region, thereby allowing the first region to be exposed on the first region. A photolithography process for forming a resist pattern in which a resist cured film remains on
A step of diffusing impurities having a conductivity type different from that of the semiconductor substrate into the second region of the semiconductor substrate by performing impurity diffusion on the semiconductor substrate through the resist pattern after the photolithography step;
Have
The light-shielding portion of the photomask used in the photolithography process has a convex portion that protrudes toward the first region from the boundary at a position facing each element region adjacent in the row direction. A method for manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a DRAM having a memory cell region as a first region and a peripheral circuit region as a second region is manufactured.

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