JP2005196949A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which reading and writing of data can be accurately performed by preventing malfunction even when selection of an address delays. <P>SOLUTION: This semiconductor device has three factors of data holding unit, a pre-charge unit, and a delay unit. The data holding unit has a plurality of memory cells. The pre-charge unit has a pre-charge potential line, a pre-charge signal line, and a plurality of switches. The delay unit has a plurality of transistors. In addition to these three factors, the device has one or both of an address selecting unit having a column decoder and a row decoder, and a display unit having a plurality of pixels. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a semiconductor device having a semiconductor element. The present invention also relates to a semiconductor device (hereinafter also referred to as “ID tag”) capable of communicating data by wireless communication.

In recent years, a semiconductor device having a semiconductor element is applied not only to electronic devices such as computers and mobile terminals but also to various fields such as an IC card, and its capacity is being increased. A semiconductor device includes: a memory cell array including a plurality of memory cells including a memory element in a region where a bit line and a word line intersect with an insulator; and an arbitrary potential of the bit line in a state where the word line is not selected. And a precharge circuit for setting the potential.

As the capacity of a semiconductor device is increased, address selection may be delayed due to increased wiring resistance and increased complexity of a decoder. Then, when performing the precharge operation of the bit line, the word line may be in a selected state, and as a result, a malfunction may occur, and the data included in the memory cell may be rewritten or destroyed. there were. In other words, data could not be read and written accurately.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor device and an ID tag that can prevent malfunction and accurately read and write data even when address selection is delayed.

In order to solve the above-described problems of the prior art, the present invention provides a semiconductor device and an ID tag having the following configuration.

The semiconductor device according to the present invention includes three elements: a data holding unit, a precharge unit, and a delay unit. The data holding means has a plurality of memory cells. The precharge means has a precharge potential line, a precharge signal line, and a plurality of switches. The delay means has a plurality of transistors. In addition to the above three elements, one or both of address selection means having a column decoder and a row decoder and display means having a plurality of pixels are provided.

Each of the plurality of memory cells included in the data holding means includes a storage element in a region where the bit line and the word line intersect with each other with an insulator interposed therebetween. The memory element is one or more selected from a transistor, a capacitor element, and a resistor element.

The precharge potential line included in the precharge means is a wiring for transmitting a precharge potential, and the precharge signal line is a wiring for transmitting a precharge signal. Each of the plurality of switches is provided between the precharge potential line and the bit line. Each of the plurality of switches is an element having a switching function, and in many cases, is a transistor or an analog switch. The input nodes of the plurality of switches are connected to the precharge signal line. Note that in the case where each of the plurality of switches is a transistor, an input node of the plurality of switches corresponds to a gate electrode of the transistor. When each of the plurality of switches is an analog switch, the input nodes of the plurality of switches correspond to the gate electrode of the N-type transistor and the gate electrode of the P-type transistor constituting the analog switch.

The input node of the delay means is connected to the CK line and the WEB line. Alternatively, the input node of the delay unit is connected to the CK line, the WEB line, and the CEB line. Alternatively, the input node of the delay means is connected to the REB line and the WEB line. Alternatively, the input node of the delay means is connected to the REB line, the WEB line, and the CEB line. The output node of the delay means is connected to a precharge signal line. The delay means has a plurality of transistors, and the plurality of transistors constitute a plurality of logic circuits. Therefore, the input node of the delay means corresponds to the input node of the logic circuit arranged at one end among the plurality of logic circuits.

The ID tag of the present invention is characterized by having a storage means including three elements of a data holding means, a precharge means and a delay means, a control means, a power generation means and a transmission / reception means. The ID tag of the present invention is characterized by having storage means including four elements of data holding means, precharge means, delay means, and address selection means, control means, power generation means, and transmission / reception means.

The present invention having the data holding means, the precharge means, and the delay means can provide a semiconductor device capable of preventing malfunction and accurately reading and writing data. In addition to the data holding unit, the precharge unit, and the delay unit, the present invention including the display unit can provide a semiconductor device that realizes high functionality and high added value.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.
(Embodiment 1)

The semiconductor device according to the present invention is characterized by including three basic elements of a data holding means 11 (hereinafter referred to as a memory cell array 11), a precharge means 12 and a delay means 13 (see FIG. 1). The semiconductor device according to the present invention corresponds to a storage unit having a function of storing data, and the storage unit includes three basic elements: a data holding unit 11, a precharge unit 12, and a delay unit 13.

The memory cell array 11 has a plurality of memory cells 14 arranged in a matrix (see FIG. 1). The memory cell array 11 includes bit lines B1 to Bn (n is a natural number) from the first column to the nth column in the column direction, and word lines W1 to Wm (m from the first row to the mth row in the row direction). Has a natural number). The memory cell 14 includes a storage element in a region where the bit line Bx (1 ≦ x ≦ n) and the word line Wy (1 ≦ y ≦ m) intersect via an insulator.

The memory element is one or more selected from a transistor, a capacitor element, and a resistor element. In the case where the semiconductor device of the present invention is a DRAM (Dynamic Random Access Memory), one transistor and one capacitor are used as memory elements. In the case of SRAM (Static Random Access Memory), six transistors, five transistors, four transistors and two resistance elements, or four transistors and one resistance element are used as memory elements. When six transistors or four transistors and two resistance elements are used as memory elements, two bit lines (one bit line and one bit bar line) are arranged in each column. . Note that the present invention is not limited to DRAM and SRAM, and is based on the configuration of the storage element, and includes FeRAM (Ferroelectric Random Access Memory), Mask ROM (Read Only Memory), PROM (Programmable Read Only Memory), EPROM (Electrically Readable Memory). ), EEPROM (Electrically Erasable Read Only Memory), flash memory, and the like.

The precharge means 12 (also referred to as a precharge circuit) has a precharge potential line 15, a precharge signal line 16, and a plurality of switches SW1 to SWm (m is a natural number) (see FIG. 1). The plurality of switches SWx (1 ≦ x ≦ m) are provided between the precharge potential line 15 and the bit line Bx. The plurality of switches SWx are elements having a switching function, and are, for example, transistors or analog switches. Further, input nodes of the plurality of switches SWx are connected to the precharge signal line 16. That is, the conduction or non-conduction of the switch SWx is controlled by the precharge signal transmitted from the precharge signal line 16.

In this embodiment, an embodiment is described in which an analog switch is used as the switch SWx (see FIG. 2A). The input node of the analog switch corresponds to the gate electrode of the N-type transistor and the gate electrode of the P-type transistor that constitute the analog switch. That is, the gate electrodes of both transistors are electrically connected to the precharge signal line 16. More specifically, the gate electrode of the P-type transistor constituting the analog switch is directly connected to the precharge signal line 16, and the gate electrode of the N-type transistor is connected to the output node of the inverter 19. The input node of the inverter 19 is connected to the precharge signal line 16.

The delay means 13 (also referred to as a delay circuit) has a plurality of transistors (see FIGS. 1 and 2). Specifically, the delay means 13 has a plurality of logic circuits composed of a plurality of transistors, and the plurality of transistors constitute at least one inverter. More specifically, the delay means 13 includes a plurality of logic circuits and a plurality of inverters selected from AND, NAND, OR, NOR, EOR, ENOR, TriBUF (tristate buffer), TriINV (tristate inverter), and the like. Or it has several inverters connected in series.
2A shows a case where the delay means 13 has a logic circuit and an inverter, and FIG. 2B shows a case where the delay means 13 has only an inverter.
In the former form shown in FIG. 2A, the input node of the delay means 13 corresponds to the input node of the logic circuit 21, and the output node of the delay means 13 corresponds to the output node of the inverter 27. 2A includes an inverter 20, logic circuits 21 to 23, inverters 24 and 25, a logic circuit 26, an inverter 27, and a wiring 28. However, the configuration of the decoder is not limited to the above description, and various configurations can be applied.
In the latter form shown in FIG. 2B, the delay means 13 includes an inverter group 30 and a logic circuit 31. The input node of the delay means 13 corresponds to the input node of the logic circuit 31, and the output node of the delay means 13 corresponds to the output node of the inverter group 30.

The input node of the delay means 13 is connected to the CK line and the WEB line, or connected to the CK line, the WEB line and the CEB line, or connected to the REB line and the WEB line, or the REB line. , WEB line and CEB line, and the output node is connected to the precharge signal line 16. The connection of the input node depends on the relationship between the timing of performing the precharge operation and CK and the necessity of the CEB signal. More specifically, when the precharge operation is performed in synchronization with CK, the input node of the delay unit 13 is connected to the CK line and the WEB line, or is connected to the CK line, the WEB line, and the CEB line. On the other hand, when the precharge operation is performed asynchronously with CK, the input node of the delay means 13 is connected to the REB line and the WEB line, or connected to the REB line, the WEB line, and the CEB line.
The CEB signal is unnecessary when only one chip is provided, or when reading and writing operations are always performed in spite of the provision of a plurality of chips.
The CK line is a wiring that transmits a CK (clock) signal, the WEB (writeable) line is a wiring that transmits a WEB signal, the REB (readable) line is a wiring that transmits a REB signal, and CEB (chipable). ) Line is a wiring for transmitting a CEB signal. The WEB signal is a write control signal, the REB signal is a read control signal, and the CEB signal is a chip selection signal.

The present invention having the delay means 13 can delay the output of a precharge signal for controlling conduction or non-conduction of the switch SWx of the precharge means 12. Therefore, even if the switching from the selection of the word line Wy to the non-selection is delayed, the output of the precharge signal is also delayed, so that the precharge operation is not performed with the word line Wy selected. Therefore, the semiconductor device of the present invention having the above structure can prevent malfunction and accurately read and write data.

The present invention is characterized by including an address selection means in addition to the three basic elements of the data holding means 11, the precharge means 12 and the delay means 13 (see FIGS. 1 and 2).
The address selection means includes a column decoder 17 and a row decoder 18 and plays a role of selecting one memory cell from the plurality of memory cells 14. The column decoder 17 is connected to the bit lines B1 to Bm, and the row decoder 18 is connected to the word lines W1 to Wn. The column decoder 17 is connected to the column address selection line, and the row decoder 18 is connected to the row address selection line. The column address selection line is a wiring that transmits a column address selection signal (Ax, 1 ≦ x ≦ m), and the row address selection line is a wiring that transmits a row address selection signal (Ay, 1 ≦ y ≦ n). It is. Further, the row decoder 18 is connected to a plurality of wirings selected from the CK line, REB line, WEB line, and CEB line. Similar to the connection of the input node of the delay means 13, the wiring connected to the row decoder 18 depends on the relationship between the timing of performing the precharge operation and CK, and the necessity of the CEB signal.
In the present embodiment, row address selection line Ay is connected to the input node of inverter 20. A plurality of wirings selected from the CK line, REB line, WEB line, and CEB line are connected to the input node of the logic circuit 21. The output node of inverter 27 is connected to word line Wy.

The present invention has display means (not shown in FIGS. 1 and 2) having a plurality of pixels in addition to the three basic elements of the data holding means 11, the precharge means 12 and the delay means 13 mentioned above. It may be. By having the display means, a semiconductor device with high functionality and high added value can be provided.

Although not shown, the present invention provides a sense amplifier used for determining binary data, a read / write circuit that controls whether to perform read or write operation, and an output circuit that outputs data to the outside A necessary circuit such as the above may be included as appropriate.

The operation of the semiconductor device having the above structure will be described with reference to timing charts of FIGS.
First, the case where the precharge operation is performed in synchronization with CK will be described with reference to FIG. Here, a precharge operation is performed when CK is H level, WEB is H level, or CK is H level and WEB is L level, and a read operation is performed when CK is L level and WEB is H level. A mode in which the write operation is performed when is at the L level and WEB is at the L level will be described.
Note that a dotted line in a waveform indicating the potential of the wiring in the timing charts of FIGS. 3A and 3B indicates a floating state (also referred to as an indefinite state or a floating state). In addition, CEB does not depend on operation control, and is always at H level or L level when performing some operation. Here, CEB is always at L level.

In the period T1, CK is at the H level, WEB is at the H level, and CEB is at the L level, and the address selection signal Ab for selecting the address of the b-th row (1 ≦ b ≦ n, b is a natural number) is at the H level. When the delay period α elapses from the start of the period T1, an L level precharge signal is transmitted from the delay means 13 to the precharge signal line 16, and the precharge signal line 16 has the same potential as the L level signal. . Then, all the analog switches SW1 to SWm to which a signal of H level or L level is input via the precharge signal line 16 are turned on, and all the bit lines B1 to Bm are precharged to the precharge potential Vpc. The

In the period T2, CK is at L level, WEB is at H level, CEB is at L level, and Ab is at H level. When the delay period α elapses after the period T2 starts, the column decoder 17 selects the bit line Ba of the a-th column (1 ≦ a ≦ m, a is a natural number). At the same time, an H level signal is transmitted to the b-th word line Wb, and the word line Wb is selected. Then, H level data of the bit line Ba is read from the memory cell 14 arranged at the coordinates (a, b).

In the period T3, CK is at the H level, WEB is at the L level, CEB is at the L level, and the address selection signal Aj for selecting an address in the j-th row (1 ≦ j ≦ n, j is a natural number) is at the H level. When the delay period α elapses from the start of the period T3, the L-level precharge signal is transmitted to the precharge signal line 16, all the analog switches SW1 to SWm are all turned on, and all the bit lines B1 to Bm. Is precharged to the precharge potential Vpc.

In the period T4, CK is L level, WEB is L level, CEB is L level, and Aj is H level. When the delay period α elapses from the start of the period T4, the column decoder 17 selects the bit line Bi in the i-th column (1 ≦ i ≦ m, i is a natural number), and an H level signal is transmitted. At the same time, an H level signal is transmitted to the j-th word line Wj, and the word line Wj is selected. Then, H level data is written into the memory cell 14 arranged at the coordinates (i, j).

Next, a mode in which the precharge operation is performed asynchronously with CK will be described with reference to FIG. In this case, a precharge operation is performed when REB is H level and WEB is H level, a write operation is performed when REB is H level and WEB is L level, and when REB is L level and WEB is H level. Read operation is performed. CEB is always at L level.

In the period T1, REB is H level, WEB is H level, and Ab is H level. When the delay period α elapses from the start of the period T1, the L level precharge signal is transmitted to the precharge signal line 16, all the analog switches SW1 to SWm are turned on, and all the bit lines B1 to Bm are turned on. Precharged to precharge potential Vpc.

In the period T2, REB is at an H level, WEB is at an L level, and Ab is at an H level. When the delay period α elapses after the period T2 starts, the bit line Ba and the word line Wb are selected. Then, the H level data of the bit line Ba is written to the memory cell 14 arranged at the coordinates (a, b).

In the period T3, REB is H level, WEB is H level, and Aj is H level. When the delay period α elapses from the start of the period T3, an L-level precharge signal is transmitted to the precharge signal line 16, all the analog switches SW1 to SWm are turned on, and all the bit lines B1 to Bm are turned on. Precharged to precharge potential Vpc.

In the period T4, REB is L level, WEB is H level, and Aj is H level. When the delay period α elapses after the period T4 starts, the bit line Bi and the word line Wj are selected. Then, H level data of the bit line Bi is read from the memory cell 14 arranged at the coordinates (i, j).

As described above, in each of the precharge periods T1 and T3, the write period, and the read periods T2 and T4, the precharge operation, the write operation, and the read operation are performed as described above.

The present invention having the above configuration can delay the output of a precharge signal for controlling conduction or non-conduction of the switch SWx. Therefore, even if the switching from the selection of the word line Wy to the non-selection is delayed, the output of the precharge signal is also delayed, so that the precharge operation is not performed with the word line Wy selected. Therefore, the present invention having the above configuration can prevent malfunction and accurately read and write data.
(Embodiment 2)

A panel which is one embodiment of a semiconductor device of the present invention will be described with reference to the drawings. The panel includes a pixel portion 401 including a plurality of pixels and driver circuits 402 and 403 including a plurality of transistors over a substrate 406 (see FIG. 4A). The drive circuits 402 and 403 may be externally attached to the substrate 406 without being integrally formed, or may be mounted on the substrate 406 by a COG (Chip On Glass) method or the like. Therefore, the display means corresponds to only the pixel portion 401 or the pixel portion 401 and the drive circuits 402 and 403. Further, the panel includes a VRAM (screen display dedicated memory), a storage unit 404 corresponding to a RAM or a ROM, and a CPU (Central Processing Unit, central processing unit) 405 on a substrate 406. Further, the panel includes an input terminal 409 that supplies signals for controlling the drive circuits 402 and 403, the storage unit 404, and the CPU 405 on the substrate 406. A signal such as a video signal and a potential are supplied to the input terminal 409 through the connection film 408. In addition, the panel includes a sealant (not illustrated in FIG. 4A) surrounding the pixel portion 401 and the driver circuits 402 and 403, and the substrate 406 and the substrate 407 are attached to each other with the sealant. Note that in the illustrated panel, the counter substrate 407 is provided only over the pixel portion 401 and the driver circuits 402 and 403, but may be provided over the entire surface. However, since the CPU 405 may generate heat, a heat sink may be provided so as to be in contact with the CPU 405.

4B is a cross-sectional view taken along the line AA ′ of the panel. The pixel portion 401 includes a TFT 411 and a capacitor 412, the driver circuit 402 includes an element group 419 including TFTs, and the storage unit 404 includes a TFT. It has an element group 420 consisting of A pixel electrode 413, an alignment film 414, a liquid crystal layer 415, an alignment film 416, and a counter electrode 417 are provided between the substrate 406 and the substrate 407. A polarizing plate is attached to the substrate 406 and the counter substrate 407.

The elements forming the circuit over the substrate 406 are preferably formed of a polycrystalline semiconductor (polysilicon) having favorable characteristics such as mobility as compared with an amorphous semiconductor, so that monolithic structure is realized. As described above, a panel in which a functional circuit such as a storage unit and a CPU other than the pixel portion and the driving circuit is integrally formed is called a system-on-panel, and the system can be multi-functionalized. Since the panel having the above configuration reduces the number of external ICs to be connected, it is small, light, and thin, and is very effective when applied to a portable terminal that has been rapidly spreading recently. Note that although a panel using a liquid crystal element as a display element is shown in this embodiment mode, the present invention is not limited to this. You may apply to the panel using other display elements, such as a light emitting element, as a display element.

In the above panel, the structure of the semiconductor device described in Embodiment 1 is applied to the structure of the memory unit 404. That is, the storage unit 404 includes a data holding unit 11, a precharge unit 12, and a delay unit 13. Further, it also has an address selection means having a column decoder 17 and a row decoder 18 (see FIG. 5). Due to the above characteristics, the panel of the present invention has an effect of preventing malfunction and accurately reading and writing data.

Next, the interrelation between the display unit 421 including the pixel portion 401 and the drive circuits 402 and 403, the storage unit 404, and the CPU 405 and a series of operations thereof will be briefly described below.
The CPU 405 includes a control unit 422 and a calculation unit 423.
When reading or writing data from the storage unit 404, first, information on the address of the memory cell storing the data or the memory cell storing the data from the program counter included in the control unit 422 included in the CPU 405 is stored in the storage unit. This is supplied to the row decoder 18 and the delay means 13 which are address selection means included in 404.
Information read from the designated address is supplied from the column decoder 17 to an instruction register included in the control unit 422. Information to be written to the designated address is supplied from a register included in the calculation unit 423.
The display of an image in the pixel portion 401 included in the display unit 421 is performed according to a signal supplied from the CPU 405 to the drive circuits 402 and 403. Note that when the video signal is stored in the storage unit 404, the video signal is supplied from the storage unit 404 to the drive circuit 402 on the signal line side via the CPU 405.
This embodiment mode can be freely combined with the above embodiment modes.
(Embodiment 3)

A structure of an ID tag (also referred to as an RFID tag, an IC tag, an electronic tag, an IC chip, a wireless chip, a wireless processor, or a wireless memory) of the present invention will be described. The ID tag 306 of the present invention includes an IC chip 304 including a storage unit 301, a control unit 302, and a power generation unit 303, and an antenna 305 (also referred to as a transmission / reception unit) (see FIG. 6A).

In the above panel, the structure of the semiconductor device described in Embodiment 1 is applied to the structure of the memory unit 301. That is, the storage unit 301 includes the data holding unit 11, the precharge unit 12, and the delay unit 13. Further, it also has an address selection means having a column decoder 17 and a row decoder 18 (see FIG. 6B). Due to the above features, the ID tag of the present invention has an effect of preventing malfunction and accurately reading and writing data. Note that the storage unit 301 can be a RAM, a ROM, or the like according to the configuration of the storage element included in the data holding unit, but a ROM may be used as the storage unit 301 used for the ID tag.

The control means 302 is composed of a logic circuit. The control means 302 (also referred to as a control circuit) corresponds to a CPU (central processing circuit) or the like. In the case of the non-contact type, the power generation means 303 employs an electromagnetic induction action, a mutual induction action, or an induction action due to static electricity of the antenna 305 wound in a coil shape. Therefore, in this case, the power generation unit 303 (also referred to as a power generation circuit) operates with the antenna 305. The antenna 305 can select the height of the frequency to be received by controlling the number of turns.

A method for forming the antenna 305 over the same substrate as the IC chip 304 (see FIGS. 6C and 6E), or a method for mounting the IC chip 304 over the substrate 313 including the antenna 305 (FIG. 6D). Either method (see (F)) is adopted. In the case where the former method is employed, a TFT group 309 and an antenna 305 are provided over a substrate 308 (see FIG. 6E). On the other hand, when the latter method is employed, the substrate 310 including the TFT group 309 is mounted over the substrate 313 including the antenna 305 with the conductive layer 311 and the insulating layer 312 interposed therebetween (see FIG. 6F). Note that the TFT group 309 shown in FIGS. 6E and 6F is a component of any one of the storage unit 301, the control unit 302, and the power generation unit 303.

Next, a communication procedure using the ID tag 306 will be briefly described below (see FIG. 6A). First, the antenna 305 included in the ID tag 306 receives radio waves from the reader / writer 307. Then, an electromotive force is generated in the power generation means 303 by a resonance action. Then, the storage unit 301 and the control unit 302 included in the ID tag 306 are activated, and the control unit 302 converts the data in the storage unit 301 into a signal. Next, a signal is transmitted from the antenna 305 included in the ID tag 306. Then, the ID tag 306 receives a signal transmitted by the antenna included in the reader / writer 307. The received signal is transmitted to a data processing device (not shown in FIG. 6A) via a controller (not shown in FIG. 6A) included in the reader / writer 307, and data is transmitted using software. Processing is performed. The above communication procedure is a case where a coil-type antenna is used and an electromagnetic induction method using a magnetic flux generated by being induced between the ID tag coil and the reader / writer coil is used. However, the present invention is not limited to the above system, and a radio system using a microwave band radio wave may be used.

The ID tag 306 has a wide directivity depending on the point of non-contact communication, the point that multiple reading is possible, the point that data can be written, the point that it can be processed into various shapes, and the frequency to be selected. This has advantages such as a wide recognition range. The ID tag 306 is an IC tag that can identify individual information of a person or an object by non-contact wireless communication, a label that can be attached to a target by applying a label process, a wristband for an event or an amusement Etc. can be applied. Further, the ID tag 306 may be molded using a resin material, or may be directly fixed to a metal that hinders wireless communication. Furthermore, the ID tag 306 can be used for system operations such as an entrance / exit management system and a payment system.

Next, an embodiment when the ID tag 306 is actually used will be described. A reader / writer 320 is provided on the side surface of the portable terminal including the display portion 321, and an ID tag 322 is provided on the side surface of the article 326 (see FIG. 7A). When the reader / writer 320 is held over the ID tag 322, the display unit 321 displays information on the product such as the description of the product, such as the raw material and origin of the product, the inspection result for each production process, the history of the distribution process, and the like. Further, when the product 325 is conveyed by a belt conveyor, the product 325 can be inspected by using a reader / writer 323 and an ID tag 324 provided on the product 325 (see FIG. 7B). . In this way, by using the ID tag in the system, information can be easily acquired, and high functionality and high added value are realized.

An embodiment of the present invention will be described with reference to FIG. The semiconductor device of the present invention is roughly divided into four blocks: a data storage block, a display block, an image processing block, and a control block, and all the blocks are provided on the substrate 100.
The data storage block includes a program ROM (PROM) 101, a work area RAM (WRAM) 102, an audio data program ROM (Audio ROM) 103, line buffer RAMs 104a and 104b, an in-range RAM (INRAM) 105, a color palette RAM (CRAM). ) 106, a memory controller 107, a decoder / register 108, an audio data program ROM controller 109, an audio data DA conversion circuit / operational amplifier 110, a memory reference power generation circuit (Vref power supply) 111, and a gradation power supply 112.
The display block includes a pixel portion 113 and driving circuits 114 and 115. The image processing block has an image processing circuit 116. The control block has a CPU 117.

As described above, a semiconductor device having not only a display block but also a data storage block, an image processing block, and a control block reduces the number of ICs to be connected and realizes a small size, a thin shape, and a light weight. In addition, the semiconductor device in which the display block, the image processing block, and the control block are adjacent to each other is arranged along the data flow, and realizes an accurate operation. The present invention is applied to the configuration of each memory constituting the storage block. This embodiment can be freely combined with the above embodiment modes.

As an example of an electronic device to which the present invention is applied, a television device, a digital camera, a digital video camera, a mobile phone device (mobile phone), a PDA or other portable information terminal, a portable game machine, a monitor, a personal computer, a car audio, etc. And an image reproducing device provided with a recording medium such as a home game machine. Specific examples will be described below.

FIG. 9A illustrates a portable terminal, which includes a main body 9101, a display portion 9102, and the like. FIG. 9C illustrates a portable television receiver including a main body 9301, a display portion 9302, and the like. FIG. 9D illustrates a portable information terminal, which includes a main body 9201, a display portion 9202, and the like. FIG. 9E illustrates a digital video camera, which includes display portions 9701 and 9702 and the like.

A panel including a display portion includes a driver circuit 9104 and a functional circuit 9103 such as a CPU or a storage unit as shown in FIG. The present invention is applied to the structure of the storage means included in the functional circuit 9103. An electronic device including a panel in which not only the driver circuit 9104 but also the functional circuit 9103 is integrally formed can reduce the number of external ICs to be connected, and thus can be reduced in size, weight, and thickness. In addition, when a self-luminous light emitting element is used as a display element constituting the display portion, a backlight or the like is not necessary, so that a thin shape, a small size, and a light weight are realized as compared with the case of using a liquid crystal element.

FIG. 9F illustrates a contact IC card, which includes a main body 9601, an IC chip 9602, and a module terminal 9603. The IC chip 9602 includes a RAM 9604, a ROM 9605, a CPU 9606, a RAM 9607, and the like. The present invention is applied to the configuration of the storage means of the RAMs 9604 and 9607 and the ROM 9605 that the IC chip 9602 has. This embodiment can be freely combined with the above embodiment modes and embodiments.

FIG. 3 illustrates Embodiment 1 of the present invention. FIG. 3 illustrates Embodiment 1 of the present invention. FIG. 3 illustrates Embodiment 1 of the present invention. FIG. 6 illustrates Embodiment 2 of the present invention. FIG. 6 illustrates Embodiment 2 of the present invention. FIG. 9 illustrates Embodiment 3 of the present invention. FIG. 9 illustrates Embodiment 3 of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The figure explaining Example 1 of this invention. The figure explaining Example 2 of this invention.

Explanation of symbols

11 Data holding means (memory cell array), 12 Precharge means 13 Delay means, 14 Memory cell 15 Precharge potential line, 16 Precharge signal line 17 Column decoder, 18 Row decoder

Claims (18)

Data holding means having a plurality of memory cells;
Precharge means having a precharge potential line, a precharge signal line and a plurality of switches;
A semiconductor device comprising delay means having a plurality of transistors. Data holding means having a plurality of memory cells;
Precharge means having a precharge potential line, a precharge signal line and a plurality of switches;
Delay means having a plurality of transistors;
A semiconductor device comprising: an address selection unit having a column decoder and a row decoder. Data holding means having a plurality of memory cells;
Precharge means having a precharge potential line, a precharge signal line and a plurality of switches;
Delay means having a plurality of transistors;
And a display means having a plurality of pixels. Data holding means having a plurality of memory cells;
Precharge means having a precharge potential line, a precharge signal line and a plurality of switches;
Delay means having a plurality of transistors;
An address selection means having a column decoder and a row decoder;
And a display means having a plurality of pixels. In any one of Claims 1 thru | or 4,
Each of the plurality of memory cells includes a memory element in a region where a bit line and a word line intersect via an insulator. In any one of Claims 1 thru | or 4,
Each of the plurality of memory cells includes a storage element in a region where a bit line and a word line intersect via an insulator,
The memory device is one or more selected from a transistor, a capacitor, and a resistor. In any one of Claims 1 thru | or 4,
Each of the plurality of memory cells includes a storage element in a region where a bit line and a word line intersect via an insulator,
Each of the plurality of switches is provided between the precharge potential line and the bit line. In any one of Claims 1 thru | or 4,
Each of the plurality of switches is a transistor or an analog switch. In any one of Claims 1 thru | or 4,
An input node of the plurality of switches is connected to the precharge signal line. In any one of Claims 1 thru | or 4,
An input node of the delay means is connected to a CK line and a WEB line. In any one of Claims 1 thru | or 4,
An input node of the delay means is connected to a CK line, a WEB line, and a CEB line. In any one of Claims 1 thru | or 4,
An input node of the delay means is connected to a REB line and a WEB line. In any one of Claims 1 thru | or 4,
An input node of the delay means is connected to a REB line, a WEB line, and a CEB line. In any one of Claims 1 thru | or 4,
An output node of the delay means is connected to the precharge signal line. In any one of Claims 1 thru | or 4,
A semiconductor device comprising control means, power supply generation means, and transmission / reception means. The semiconductor device according to claim 1, wherein the semiconductor device is a DRAM, an SRAM, or an FeRAM. 5. The semiconductor device according to claim 1, wherein the semiconductor device is a mask ROM or a PROM. 5. The semiconductor device according to claim 1, wherein the semiconductor device is an EPROM, an EEPROM, or a flash memory.

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