JP2005196753A5 - - Google Patents
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- JP2005196753A5 JP2005196753A5 JP2004360133A JP2004360133A JP2005196753A5 JP 2005196753 A5 JP2005196753 A5 JP 2005196753A5 JP 2004360133 A JP2004360133 A JP 2004360133A JP 2004360133 A JP2004360133 A JP 2004360133A JP 2005196753 A5 JP2005196753 A5 JP 2005196753A5
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- conductive layers
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Claims (8)
前記複数の第１の素子は、前記複数の導電層から１つを選択するデコーダを構成し、
前記複数の第２の素子は、前記複数の導電層から伝達される信号を増幅するセンスアンプを構成し、
前記複数の第１の素子が設けられる領域の間に、前記複数の第２の素子が設けられる領域が配置されていることを特徴とする半導体装置。 On one surface of the substrate having an insulating surface, there are a region where a plurality of conductive layers are provided, a region where a plurality of first elements are provided, and a region where a plurality of second elements are provided,
Wherein the plurality of first element constitutes a decoder for selecting one of said plurality of conductive layers,
Wherein the plurality of second element constitutes a sense amplifier for amplifying a signal transmitted from said plurality of conductive layers,
The semiconductor device characterized by between a region where the plurality of first elements are provided, a region in which the plurality of second elements are provided are arranged.
前記複数の第１の素子は、前記複数の導電層から１つを選択するデコーダを構成し、
前記複数の第２の素子は、前記複数の導電層から伝達される信号を増幅するセンスアンプを構成し、
前記複数の第１の素子が設けられる領域と前記複数の第２の素子が設けられる領域は、交互に配置されていることを特徴とする半導体装置。 On one surface of the substrate having an insulating surface, there are a region where a plurality of conductive layers are provided, a region where a plurality of first elements are provided, and a region where a plurality of second elements are provided,
Wherein the plurality of first element constitutes a decoder for selecting one of said plurality of conductive layers,
Wherein the plurality of second element constitutes a sense amplifier for amplifying a signal transmitted from said plurality of conductive layers,
A region in which the plurality of first elements are provided and a region in which the plurality of second elements are provided are alternately arranged.
前記複数の第１の素子が設けられる領域は、前記複数の導電層の各々に対応した複数の素子形成領域に分割され、
前記複数の素子形成領域から選択された１つの素子形成領域の行方向のピッチと、前記複数の導電層間のピッチは異なることを特徴とする半導体装置。 In claim 1 or claim 2,
The region where the plurality of first elements are provided is divided into a plurality of element formation regions corresponding to each of the plurality of conductive layers,
A semiconductor device, wherein a pitch in a row direction of one element formation region selected from the plurality of element formation regions is different from a pitch between the plurality of conductive layers.
前記複数の第１の素子と前記複数の第２の素子は、それぞれ、トランジスタを有することを特徴とする半導体装置。The plurality of first elements and the plurality of second elements each include a transistor.
前記基板はガラス基板であることを特徴とする半導体装置。 In claim 1 or claim 2,
The semiconductor device, wherein the substrate is a glass substrate.
前記基板上に設けられた記憶素子を有することを特徴とする半導体装置。 In claim 1 or claim 2,
A semiconductor device comprising a memory element provided on the substrate .
前記基板上に設けられた発光素子または液晶素子を有することを特徴とする半導体装置。 In claim 1 or claim 2,
A semiconductor device comprising a light-emitting element or a liquid crystal element provided over the substrate .
制御手段、電源発生手段及び送受信手段を有することを特徴とする半導体装置。 In claim 1 or claim 2,
A semiconductor device comprising control means, power supply generation means, and transmission / reception means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004360133A JP4989847B2 (en) | 2003-12-12 | 2004-12-13 | Semiconductor device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003415169 | 2003-12-12 | ||
| JP2003415169 | 2003-12-12 | ||
| JP2004360133A JP4989847B2 (en) | 2003-12-12 | 2004-12-13 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011007086A Division JP5256310B2 (en) | 2003-12-12 | 2011-01-17 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2005196753A JP2005196753A (en) | 2005-07-21 |
| JP2005196753A5 true JP2005196753A5 (en) | 2007-11-29 |
| JP4989847B2 JP4989847B2 (en) | 2012-08-01 |
Family
ID=34829095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004360133A Expired - Fee Related JP4989847B2 (en) | 2003-12-12 | 2004-12-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4989847B2 (en) |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63247990A (en) * | 1987-10-21 | 1988-10-14 | Hitachi Ltd | Semiconductor memory device |
| DE3776798D1 (en) * | 1987-11-23 | 1992-03-26 | Philips Nv | FAST WORKING STATIC RAM WITH LARGE CAPACITY. |
| JP2663651B2 (en) * | 1989-06-26 | 1997-10-15 | 日本電気株式会社 | Semiconductor memory integrated circuit |
| JPH04335296A (en) * | 1991-05-10 | 1992-11-24 | Sony Corp | Semiconductor memory device |
| JPH0878538A (en) * | 1994-09-06 | 1996-03-22 | Hitachi Ltd | Semiconductor memory and information processor employing it |
| US5923605A (en) * | 1997-09-29 | 1999-07-13 | Siemens Aktiengesellschaft | Space-efficient semiconductor memory having hierarchical column select line architecture |
| JP2002093160A (en) * | 2000-09-18 | 2002-03-29 | Mitsubishi Electric Corp | Semiconductor memory |
| JP3913534B2 (en) * | 2001-11-30 | 2007-05-09 | 株式会社半導体エネルギー研究所 | Display device and display system using the same |
| KR100648543B1 (en) * | 2002-06-03 | 2006-11-27 | 후지쯔 가부시끼가이샤 | Semiconductor integrated circuit |
-
2004
- 2004-12-13 JP JP2004360133A patent/JP4989847B2/en not_active Expired - Fee Related
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