JP2005196447A - Memory control device and memory card using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control device capable of writing a large amount of data into a NAND memory at high speed by making effective use of the function of writing into a plurality of blocks at the same time, and a memory card using the memory control device. <P>SOLUTION: The memory control device has: an electrically rewritable NAND memory 11 divided into clear blocks which are cleared of a plurality of cell data at a time through clearing action, the plurality of clear blocks enabling data to be written therein at the same time; an I/O-I/F part 15 having a plurality of data terminals 14b-14e and connected to a host 20; and a controller 19 that controls the data received by the data terminals 14b-14e so that for each of the data terminals 14b-14e, the data are written into the plurality of clear blocks of the NAND memory 11 as independent bit streams at the same time. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory control device and a memory card using the same, and is particularly used for a NAND memory having a function of simultaneously writing a plurality of blocks.

  In recent years, digital devices have been developed along with the digitization of music signals and video signals. These digital devices are equipped with a recording medium such as a compact disk or a hard disk in order to record music data and video data.

  Digital devices are becoming smaller, and several centimeter-square products are also available for music players. In such a small digital device, with the miniaturization of the main body, the equipped recording medium has also been miniaturized in parallel.

  Further, so-called memory cards using semiconductor memories are used as smaller recording media. At present, a memory card called SD (Secure Digital) card corresponding to copyright protection has been commercialized.

  The SD memory card is equipped with a NAND type EEPROM (hereinafter referred to as “NAND type memory”). A NAND memory is a kind of semiconductor memory device, which can be electrically rewritten, and is characterized in that a certain area is collectively treated as an erase block in an erase operation. For this reason, it is more suitable for use such as file recording that handles a large capacity at a time than the use as a normal program area where random access occurs.

  However, the NAND type memory cannot be overwritten in principle because of the structure of the memory cell, and when data is rewritten, it is necessary to write new data after erasing the memory cell once. Become.

  Further, the number of times of rewriting of the memory cell is limited, and erasure, writing block averaging processing, and the like are required so as not to use only the same memory cell. For this reason, there is a problem that writing speed is slower than other recording media.

  In order to solve this problem, a method of simultaneously writing to a plurality of blocks in a NAND memory is described in “Patent Document 1”. A NAND type memory capable of simultaneously writing four blocks according to this method has already been commercialized.

  On the other hand, the data recorded on the SD memory card includes not only music signals but also video signals as described above. As described in “Patent Document 2”, it is necessary to consider multi-angle data when recording a video signal.

  DVDs and surveillance camera videos often handle this multi-angle video signal, and there is a strong demand for real-time performance especially for surveillance camera videos. For this reason, it is necessary to realize a function of displaying images of a plurality of angles at the same time, or a function of switching and displaying angles at an arbitrary timing.

  In the case of recording such multi-angle video signals on an SD memory card, conventionally, there has been a problem that data of each angle has to be transferred to the memory card in a time division manner.

  That is, since the host side transfers data to the memory card in a time-sharing manner, there is a drawback that data control on the host side becomes complicated. Particularly in consumer digital camcorders, cost competition is fierce, and control on the host side is complicated, resulting in high costs.

  Furthermore, the conventional memory card has an essential problem that video data of a plurality of angles cannot be simultaneously written in the NAND memory, and high-speed recording cannot be performed.

  FIG. 6 is an image diagram showing a data writing method in a conventional SD card I / F.

  In the conventional SD card I / F, stream data is transferred to the simultaneous write buffers 61a to 61d by time division using the data terminals DAT0, DAT1, DAT2, and DAT3. That is, data in units of bytes (8 bits) is divided into upper 4 bits and lower 4 bits, and as shown in FIG. 6, first, a plurality of bytes of StreamA1 are sent, and then a plurality of bytes of StreamA2 are transferred. Further, StreamB1 and StreamB2, which are streams of different angles, are transferred in the same manner as StreamA1 and StreamA2.

Therefore, in such a data transfer method, there is a problem that not only the above-described simultaneous writing function of a plurality of blocks can be effectively used but high-speed data transfer cannot be performed, but also data control on the host side becomes very complicated.
Japanese Patent Laid-Open No. 11-224492 Japanese Patent Laid-Open No. 2001-223991

  As described above, the conventional memory control device and the memory card using the memory control device have a problem that the multiple block simultaneous writing function of the NAND memory cannot be effectively used.

  The present invention has been made to solve the above problems, and a memory control device capable of writing a large amount of data to a NAND memory at a high speed by using a multiple block simultaneous writing function and a memory card using the same The purpose is to provide.

  According to one aspect of the present invention, an electrically rewritable nonvolatile memory capable of simultaneously writing data to a plurality of erase blocks divided into erase blocks from which a plurality of cell data is erased collectively in an erase operation. A memory control apparatus for controlling a memory, having a plurality of data terminals, connected to a host device, and data received by the plurality of data terminals as independent bit streams for the respective data terminals There is provided a memory control device comprising writing means for simultaneously writing to the plurality of erase blocks of the nonvolatile memory.

  According to another aspect of the present invention, a plurality of cell data is divided into erase blocks to be erased collectively in an erase operation, and data can be written to the plurality of erase blocks simultaneously. Non-volatile memory, connection means having a plurality of data terminals, connected to a host device, and data received by the plurality of data terminals as independent bit streams for each of the data terminals There is provided a memory card comprising writing means for simultaneously writing to a plurality of the erase blocks.

  According to the present invention, the multiple block simultaneous writing function of the NAND memory can be used effectively, so that a memory control device capable of writing a large amount of data at high speed and a memory card using the same can be realized.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit block diagram showing a memory control device and a memory card using the same according to Embodiment 1 of the present invention. Here, a case where the NAND memory 11 and the memory control device 13 are mounted on the memory card 12 is shown.

  The memory card 12 writes / reads data to / from the CLK terminal 14a for receiving the clock CLK necessary for data transfer, the DAT0 terminal 14b, the DAT1 terminal 14c, the DAT2 terminal 14d, the DAT3 terminal 14e, and the memory card 12 used for data transfer, It includes a CMD terminal 14f that receives a command CMD for instructing erasure, a VDD terminal 14g to which a power supply VDD is supplied, and GND terminals 14h and 14i to which a ground GND is connected.

  The CMD terminal 14 f is also used to transfer a processing request to the memory card 12 and response information to be returned from the memory card 12 to the host 20.

  The memory control device 13 according to the first embodiment of the present invention includes an I / O-I / F unit 15 that is an interface with an external device, an information register of the memory card 12, and firmware for controlling the entire memory control device 13. Are stored in a ROM 16, an SRAM 17 that is a work memory for executing firmware, a memory I / F unit 18 that is an interface with a NAND memory 11 that is a storage element, and a controller 19 that controls these by firmware. Composed.

  A NAND memory 11 for storing and storing data is mounted on the memory card 12. The NAND memory 11 is an electrically erasable nonvolatile memory. The minimum unit that can be erased is called an erase block. The erase block has a capacity of 8 KB, 16 KB, 32 KB, and the like.

  In this erase block, there is a unit called a page, and the page is composed of 528 (512 + 16) bytes. 512 bytes are for data, and 16 bytes are for error correction.

  For example, when the erase block is 8 KB, one block is composed of 16 pages, 16 KB is composed of 32 pages, and 32 KB is composed of 64 pages. When the capacity is 64 MB, it is 528 bytes * 32 pages * 4096 erase blocks.

The NAND memory 11 can simultaneously write to a plurality of erase blocks under the following conditions. That is, the same page is written in each erase block, and the number of erase blocks to be simultaneously written is 4 blocks, and the 4 blocks are combinations of Table 1.

  For example, erasure blocks 0, 1, 2, and 3 can be simultaneously written, but 0, 4, 2, and 7 cannot be simultaneously written.

  Further, the memory card 12 manages the NAND memory 11 by dividing it into a normal area and a protected area, and only the normal area can be read and written by a normal command. In order to access the protected area, a predetermined authentication process is required.

  For this authentication, CPRM (Content Protection for Recodable Media) is used. As a result, a function of suppressing access by unauthorized devices is realized.

  The controller 19 of the memory control device 13 initializes the I / O-I / F unit 15, ROM 16, SRAM 17, memory I / F unit 18, and NAND memory 11 when the memory card 12 is powered on. Subsequently, the firmware is read from the ROM 16 and stored in the SRAM 17.

  When the preparation of the controller 19 is completed and a prescribed initialization command is issued from the host 20 using the CMD terminal 14f and the DAT terminals 14b to 14e, the initialization of the memory card 12 is completed. The controller 19 executes a desired process according to a command from the host 20, for example, single write, multiple write, single read, multiple read, register information read, authentication procedure, and the like.

  The controller 19 has a function for extending the life of the rewrite life of the NAND memory 11. The controller 19 treats the address accessed from the host 20 as a logical address and treats the address of the NAND memory 11 as a physical address. Has an address translation table so that different physical addresses can be accessed even with the same logical address.

  Next, the operation of the memory control device 13 having the above-described configuration will be described.

  First, the host 20 performs initialization processing of the memory card 12 by the method described above. Subsequently, necessary internal register information is read. It is determined whether or not the memory card 12 has a multi-stream recording function based on the read register value.

  When the host 20 has the same function, the host 20 issues a command for changing to the multi-stream write mode. The host 20 develops the bit of the multi-angle bit stream on the DAT0 terminal 14b, the DAT1 terminal 14c, the DAT2 terminal 14d, and the DAT3 terminal 14e, and transfers the bit stream to the memory card 12 as a stream signal.

  FIG. 2 is an image diagram showing a write operation of the memory control device 13 according to the first embodiment of the present invention.

  The memory control device 13 that has received the stream data, as shown in FIG. 2, receives the data received by the DAT0 terminal 14b to the simultaneous write buffer 21a, the data received by the DAT1 terminal 14c to the simultaneous write buffer 21b, and the DAT2 terminal 14d. Write the data received by the DAT3 terminal 14e into the simultaneous write buffer 21c.

  Necessary areas are secured in the SRAM 17 for the simultaneous write buffers 21a to 21d.

  When all the simultaneous write buffers 21a to 21d are filled with data, the data in the simultaneous write buffers 21a to 21d is transferred to the NAND memory 11 via the memory I / F unit 18 by using the simultaneous writing function of a plurality of blocks of the NAND memory 11. Write to.

  The data written in the NAND memory 11 is shown in the physical memory map of FIG. 1 in the order of physical addresses.

  In this way, Stream-A, Stream-B, Stream-C, and Stream-D in FIG. 1 are written to the NAND memory 11 in the memory card 12 like a physical memory map.

  As shown in the physical memory map, the order of writing and reading is w1, w2, w3, w4 for writing, r1, r2, r3, r4 for reading, and four data are written at the same time. Read data.

  Up to this point, the description has been made without considering the logical-physical conversion of the address, but actually the logical address and the physical address are different.

  FIG. 3 is an image diagram showing address conversion of the memory control device 13 according to the first embodiment of the present invention.

  FIG. 3 shows a memory map in which a multi-stream write mode (parallel) and a normal write mode (serial) are mixed. Since ADDB0, ADDB1, ADDB2, and ADDB3 are data written in the multi-stream mode, a set of 4 erase blocks is formed.

  In this example, the conditions described in Table 1 are satisfied, such as EB8, EB9, EB10, and EB11. Therefore, the four erase blocks need only satisfy the above conditions, and need not be continuous. For example, EB0, EB9, EB14 (not shown), and EB19 (not shown) may be used.

  On the other hand, in the normal write mode, ADDB4, ADDB5, ADDB6, and ADDB7 correspond to one erase block for one block, such as EB1, EB4, EBy, and EBz, and the above conditions must be satisfied. There is no.

  According to the first embodiment, it is possible to handle a plurality of input streams independently by associating independent stream data with erase blocks in a plurality of block simultaneous write areas of the NAND memory 11, so that the host 20 can be easily controlled. In addition, the simultaneous writing function of a plurality of blocks of the NAND memory 11 can be used effectively, and the writing performance to the memory card 12 can be improved.

  Therefore, video signals of a plurality of angles can be simultaneously recorded on the memory card 12 in real time, thereby enabling the user to switch and display the angles at an arbitrary timing, and the degree of freedom of the video data processing method is increased. Improve dramatically.

  In the first embodiment, the simultaneous write buffer 21a is used for Stream-A, the simultaneous write buffer 21b is used for Stream-B, the simultaneous write buffer 21c is used for Stream-C, and the simultaneous write buffer 21c is used for Stream-D. Although the write buffer 21d is allocated, the present invention is not limited to this. For example, the simultaneous write buffer 21d may be allocated to Stream-A. For this switching, a dedicated command may be newly provided.

  In the first embodiment, the memory control device 13 mounted on the memory card 12 has been described. However, the present invention is not limited to this, and may be mounted in the NAND memory 11, for example. The present invention can also be applied to a control device such as a digital camera that directly controls the NAND memory 11.

  Hereinafter, Example 2 of the present invention will be described with reference to the drawings.

  The first embodiment uses the simultaneous writing function of a plurality of blocks of the NAND memory 11 to write multi-stream data such as video signals of a plurality of angles simultaneously and at high speed. In contrast, in the second embodiment, one stream data is duplicated and simultaneously written in a plurality of erase blocks.

  For example, data can be protected by copying important data to a plurality of areas.

  Since the configuration of the memory card in the second embodiment of the present invention is the same as that in the first embodiment, reference is made to FIG. Here, the control method will be described.

  FIG. 4 is a conceptual diagram showing page details of erase blocks in the memory control device 13 and the memory card 12 using the same according to the second embodiment of the present invention. FIG. 4A is a physical memory map according to the second embodiment, and FIG. 4B is an internal table 41 showing an example of erase block numbers depending on the number of copies.

  FIG. 4A shows a case where the number of copies is four as an example.

  Data input to the memory card 12 may be transferred by using a plurality of data lines, or may be transferred by bit development using a single data line as in the first embodiment. The copy number is notified to the memory card 12 in advance of the write command using a copy number setting command.

  In the case of multiple copies, the offset value of the erase block to be copied is also notified using a command.

The erase block in which the same copy data is written is calculated by the following calculation formula.
A: (4 * n) * 0 + 0 + Start
B: (4 * n) * 1 + 0 + Start
C: (4 * n) * 2 + 0 + Start
D: (4 * n) * 3 + 0 + Start
Here, Start is the erase block number of A, and is 0 in FIG. N is the offset value of the erase block.

  For example, when n is 100, A = 0, B = 401, C = 802, and D = 1203. These are managed as an internal table 41 by the controller 19 of the memory card 12.

  As shown in FIG. 4B, the internal table 41 includes a base erase block number (column 42), a copy number (column 43), a Start (column 44), an Offset value (column 45), and a related block 1 (Column 46), related block 2 (column 47), and related block 3 (column 48).

  In the case of the copy number 4 described above, the line 49 is as shown in FIG. When the number of copies is 2, the result is as shown in line 50 of FIG. When the number of copies is 2, the data received by the 4-bit data DAT terminals 14b to 14e may be handled as two multi-value (in this case, 2 bits = 4 values) bit streams.

  By adjusting the Offset value (column 45) of the internal table 41, the same data can be recorded on different logical disks at a time. Similarly, in order to manage one file in the FAT file system (ISO / IEC 9293), it is possible to write the data body, FAT, and directory entry at a time.

  According to the second embodiment, it is possible to effectively use the multiple block simultaneous writing function of the NAND memory 11 and easily have multiple copies of input data. Since the reliability of data is emphasized in an overnight operation server or the like, the reliability of data can be easily improved by writing the data on the recording medium by applying the present invention.

  Embodiment 3 of the present invention will be described below with reference to the drawings.

  Since the configuration of the memory card according to the third embodiment of the present invention is the same as that of the first embodiment, refer to FIG. Here, the control method will be described.

  FIG. 5 is a conceptual diagram showing page details of erase blocks in the memory control device 13 and the memory card 12 using the same according to the third embodiment of the present invention. FIG. 5A is a physical memory map according to the third embodiment, and FIG. 5B is an internal table 51 that manages a writing method for each erase block.

  FIG. 5A is a physical memory map of the NAND memory 11 when a plurality of blocks are simultaneously written and a normal writing area is mixed. Here, the memory map is divided into two areas, which show different areas of the same NAND memory 11, respectively.

  In the multiple block simultaneous writing area, A-0, A-1, A-2, and A-3 are written by one write operation w1. At the time of reading, these are read in the order of R1, R2, R3, and R4 so as to be A-0, A-1, A-2, and A-3.

  On the other hand, in the normal writing area, the multiple block simultaneous writing function is not used, and writing and reading processing are performed in order from the top in succession one block at a time during writing and reading. In the case of multi-stream writing, processing is performed as described in the first embodiment.

  Multiple block simultaneous writing, normal writing, and multi-stream writing are managed in the internal table 51. As shown in FIG. 5B, the internal table 51 includes parallel ( Multiple block simultaneous writing), serial (normal writing), and multi (multi-stream writing) are set as data arrays.

  The data array is set when data is written to the erase block for the first time. Whether to execute simultaneous writing (parallel) of a plurality of blocks or normal writing (serial) is determined by an access method from the host 20.

  For example, when the command from the host 20 is a single write, it is known that the input data is for one page, so the normal write (serial) is executed. If the command is multi-write, the input data is predicted to have a large capacity, and multiple blocks are simultaneously written (parallel).

  According to the third embodiment, in addition to the effects described in the first embodiment, the writing method for each erase block is managed by the internal table 51. Therefore, even when different write formats are mixed, data can be read without any problem. Become.

  In the above-described third embodiment, the data array of the internal table 51 is set when data is written to the erase block for the first time. However, the present invention is not limited to this. You may divide the area.

  In the third embodiment, the write method (parallel, serial, or multi) is determined by the access method from the host 20, but the present invention is not limited to this. For example, the host The write mode switching command may be issued before the 20 issues the write command to change the write mode of the memory card 12.

1 is a circuit block diagram showing a memory control device according to Embodiment 1 of the present invention and a memory card using the same. FIG. 3 is an image diagram illustrating a write operation of the memory control device according to the first embodiment of the invention. FIG. 3 is an image diagram illustrating address conversion of the memory control device according to the first embodiment of the invention. FIG. 5 is an image diagram showing page details of an erase block in a memory control device according to Embodiment 2 of the present invention and a memory card using the same. FIG. 9 is an image diagram showing page details of an erase block in a memory control device and a memory card using the same according to Embodiment 3 of the present invention. The image figure which shows the data writing method in the conventional SD card I / F.

Explanation of symbols

11 NAND memory 12 Memory card 13 Memory controller 14a-14i Terminal 15 I / O-I / F part 16 ROM
17 SRAM
18 Memory I / F unit 19 Controller 20 Hosts 21a to 21d Simultaneous write buffers 41 and 51 Internal table

Claims (5)

A memory control device for controlling an electrically rewritable nonvolatile memory in which a plurality of cell data is divided into erase blocks to be erased collectively by an erase operation and data can be simultaneously written to the plurality of erase blocks. And
A connection means having a plurality of data terminals and connected to a host device;
A memory control device comprising: a writing unit that simultaneously writes data received by the plurality of data terminals into the plurality of erase blocks of the nonvolatile memory as independent bit streams for the respective data terminals. A memory control device for controlling an electrically rewritable nonvolatile memory in which a plurality of cell data is divided into erase blocks to be erased collectively by an erase operation and data can be simultaneously written to the plurality of erase blocks. And
A connection means having a plurality of data terminals and connected to a host device;
It comprises write means for copying data received by one data terminal of the plurality of data terminals and simultaneously writing the data to at least two independent bit streams to the plurality of erase blocks of the nonvolatile memory. Memory control device. Other writing means for bundling data received by the plurality of data terminals and writing the data to the nonvolatile memory as a multi-value data stream;
3. The memory control apparatus according to claim 1, further comprising a selection unit that selects the writing unit or the other writing unit based on an instruction received by the connection unit.   The area management unit for managing an internal table indicating that an area of the nonvolatile memory in which data is written is written by the writing unit or the other writing unit. Memory controller. An electrically rewritable nonvolatile memory that is divided into erase blocks in which a plurality of cell data is erased collectively in an erase operation, and that can simultaneously write data to the plurality of erase blocks;
A connection means having a plurality of data terminals and connected to a host device;
A memory card comprising a writing means for simultaneously writing data received by the plurality of data terminals to the plurality of erase blocks of the nonvolatile memory as independent bit streams for the respective data terminals.

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