JP2005191858A - Oscillator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the frequency fluctuation of the output clock signal of a voltage-controlled oscillator to be caused due to every external factor. <P>SOLUTION: A correction voltage circuit for correcting a variable capacitance value is connected to a terminal opposite to a terminal to which a Vt voltage is applied from a charge pump circuit 104 or a loop filter (low pass filter) 105 of a variable capacity configuring the resonance circuit of a voltage-controlled oscillator 101. The correction voltage circuit is controlled by a detecting circuit 106 so that the frequency fluctuation is suppressed by correcting a variable capacitance value exactly for the frequency fluctuation of a clock signal caused by every external factor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an oscillator.

  Conventionally, a clock signal output from a voltage controlled oscillator (VCO) is divided by a counter circuit, phase-compared with a reference signal, and a phase comparison result between the clock signal and the reference signal is charged with binary data. The control current is output to the pump circuit, and the control current based on the binary data sent from the phase comparator in the charge pump circuit is output and converted to the control voltage via the loop filter, and the control voltage is input to the VCO.

  By repeating the above operation continuously, the reference signal and the clock signal are in phase, and the output clock signal of the VCO is locked. Even after being locked, the output clock signal of the VCO is kept locked by the above-described operation.

  One of the problems in such a VCO is that the frequency of the clock signal may fluctuate temporarily due to external influences. Due to the frequency variation of the clock signal, the rise time of the transmission / reception path of the mobile communication device is delayed, and the signal input from the antenna cannot be transmitted efficiently from the beginning. There is a concern that the first bit of the input signal cannot be detected and a bit error occurs.

  As an example, the output of the VCO is usually connected to the counter oscillation circuit and the local oscillation signal input section of the modulator / demodulator or mixer circuit. When the circuit operation is turned on / off, the impedance of the local oscillation signal input section of the mixer circuit changes, and the load used in the resonant circuit of the VCO fluctuates due to the impedance change, and as a result, the frequency of the clock signal Will fluctuate.

The frequency fluctuation due to such load fluctuation is generally achieved by inserting a buffer circuit between the VCO output and the mixer circuit to increase the impedance of the VCO output when viewed from the mixer circuit, that is, by increasing the isolation. Frequency fluctuation can be suppressed.
Special table 2003-500872 gazette

  However, the frequency fluctuation of the clock signal of the VCO is not only caused by the load fluctuation, but is caused by any factor. As described above, it is easy to take measures against frequency fluctuations caused by load fluctuations, but it is difficult to take countermeasures against frequency fluctuations caused by the accumulation of small factors such as the influence of parasitic components.

  Further, the frequency fluctuation is controlled by the PLL circuit, but the loop response time is delayed due to the characteristics of the loop filter, and the lock-up time is delayed. When the lock-up time is increased, the C / N characteristic of the clock signal of the VCO is deteriorated or the leak of the reference signal is increased. Therefore, it is difficult to take measures against frequency fluctuations.

  As described above, the present invention detects the frequency fluctuation before the frequency fluctuation is controlled by the control voltage output from the loop filter without taking measures against the frequency fluctuation of the VCO clock signal for each factor. An object of the present invention is to provide an oscillator in which the influence of the frequency fluctuation on the bit error due to the frequency fluctuation is less than that of the conventional one by having the correction circuit that detects the frequency fluctuation and corrects the frequency fluctuation.

  In order to achieve the above object, the present invention comprises a detection circuit for detecting a frequency variation after comparing a clock signal output from a VCO with a phase comparator, a pair of variable capacitors, and a pair of inductors. And a conventional VCO that is constituted by a pair of MOSFETs that output the clock signal and a terminal to which an output voltage from a pair of variable-capacity charge pump circuits that constitute the resonance circuit is applied. Includes a VCO having a correction circuit for correcting a frequency variation of the clock signal, which is configured by connecting a grounded terminal to a variable power source connected to a detection circuit via a pair of resistors. It is characterized by.

  According to the present invention, when the clock signal of the VCO locked by the PLL circuit starts to cause frequency fluctuation due to an external factor, the frequency fluctuation is detected by the detection circuit, and the VCO resonance circuit is forcibly detected by the correction circuit. Since the frequency fluctuation is corrected by applying a correction voltage from the variable power source to the variable capacitor constituting the frequency fluctuation, the frequency fluctuation can be reduced.

  According to the present invention, by configuring a circuit that applies a variable voltage controlled by the detection circuit to a terminal opposite to a terminal to which a voltage is applied in the variable capacitor of the VCO, the clock signal of the VCO that is generated by an external factor is generated. By forcibly correcting the frequency variation for the potential difference of the variable capacitor, the frequency variation of the clock signal is suppressed, so that high-quality communication with very few bit errors becomes possible.

  Embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a basic configuration of an oscillator according to an embodiment of the present invention.

  The signal input from the antenna 1 is amplified, modulated, and unnecessary signals are removed by the RF unit 2 and then input to the MPU 3.

  FIG. 2 is a block diagram showing a basic configuration of a PLL circuit which is a part of the RF unit of FIG.

  After the output clock signal is input to the counter circuit 102 and divided by the VCO 101, the oscillator performs phase comparison with the reference signal input from the outside in the phase comparator 103, and the result is expressed as binary data in the phase comparator 103. Is output from. When the binary data output from the phase comparator 103 is input to the charge pump circuit 104, the binary data output from the phase comparator 103 in the charge pump circuit 104 is converted into a current and output. The current output from the charge pump circuit 104 is converted into a voltage by the loop filter 105, and the phase difference voltage is input to the VCO 101 as the Vt voltage. Further, after the phase comparison by the phase comparator 103, the phase difference corresponding to the frequency fluctuation is input to the detection circuit 106, and the variable power supply is controlled by the detection circuit 106.

  Next, the oscillator having the configuration shown in FIG. 1 will be described.

  The antenna 1 selects a signal from the diversity antenna by controlling the MPU 3 so that the signal having the highest sensitivity among the plurality of signals can be selected. The signal input to the antenna 1 is processed into a low frequency signal by the RF unit 2. In the RF unit 2, the signal from the antenna 1 is input to the received signal processing unit via a switch, amplified by a low noise amplifier or the like, and then input to the mixer via a filter and converted to a low frequency. The signal converted to the low frequency is input to the MPU 3, and data is extracted from the input low frequency signal.

  Next, the PLL circuit having the configuration shown in FIG. 2 will be described.

  The counter circuit 102 divides the output clock signal of the VCO 101 and outputs it to the phase comparator 103.

  The phase comparator 103 compares the phase of the output signal from the counter circuit 102 and the phase of the reference signal from the outside, and outputs the result to the charge pump 104 as binary data of H (High) and L (Low). The charge pump circuit 104 converts the binary data from the phase comparator 103 into a ternary signal of H, L, and Z. For example, when the phase of the clock signal is ahead of that of the reference signal, H is output and the current is supplied to the loop filter 105. When the clock signal is behind the reference signal, L is output and the current is output. Is output from the loop filter, and in the case of the same phase, Z is output to turn off currents to and from the loop filter 104, that is, turn off MOSFETs 211 and 212 described later.

  FIG. 3 is a circuit diagram showing a basic configuration of an embodiment of the charge pump circuit 104 shown in FIG.

  The binary data output from the phase comparator 103 in FIG. 1 is input to the MOSFETs 211 and 212 from the input lines 201 and 202 in FIG. 3, respectively. Since the MOSFET 211 is a p-type MOSFET, it is turned on when “0” is input to the input line 201, and the MOSFET 212 is an n-type MOSFET and is turned on when “1” is input to the input line 202. When the MOSFET 211 is turned on, the state becomes H and current flows through the output unit 203. That is, when a current is supplied to the loop filter 105 in the subsequent stage and the MOSFET 212 is turned on, a current flows from the output line 203 to GND when the MOSFET 212 is turned on, that is, a current flows from the loop filter 105 in the subsequent stage to the GND. Flowing. Further, in the case of the same phase, the state is in the Z state, the MOSFETs 211 and 212 are in the off state, and no current flows.

  FIG. 4 is a circuit diagram showing a basic configuration of one embodiment of the loop filter 105 shown in FIG.

  In this example, a secondary lag filter was used. The current output from the charge pump circuit 104 is accumulated in the capacitors 302 and 303 in FIG. 4. By accumulating the current output from the charge pump circuit 104, a potential difference is generated in the capacitors 302 and 303. The loop filter 105 outputs a Vt voltage to the VCO 101.

  FIG. 5 is a circuit diagram showing the basic configuration of one embodiment of the VCO 101. As shown in FIG.

  By inputting the Vt voltage output from the loop filter 105 of FIG. 2 to the back gate of the variable capacitor 412 formed by the n-type MOSFETs 401 and 402, the capacitance of the variable capacitor 412 changes. A resonant circuit is configured. The VCO 101 generates an oscillation signal by a pair of MOSFETs 403 and 404, and then outputs a signal having a resonance frequency as a clock signal by this resonance circuit. The output clock signal is input to the phase comparator 103 and subjected to phase comparison. Then, the binary data is converted into a current by the charge pump 104, and the converted output current is converted into a voltage by the loop filter 105. And the variable capacitor 412 changes. By repeating this operation, the output clock signal of the VCO is always kept in the same phase as the reference signal, that is, kept in a locked state.

  The detection circuit 106 receives the binary data phase-compared by the phase comparator 103, and controls the variable power supply in accordance with the input data.

  Next, examples of the embodiment will be described.

  As described above, when the operation of the mixer is turned on / off when the clock signal of the VCO 101 is in a locked state, the impedance of the local oscillation signal input unit of the mixer changes. If the impedance of the local oscillation signal input section of the mixer is changed from Z to Z + ΔZ when the mixer is changed from the off state to the on state, and the impedance change fluctuates the load of the VCO, (Equation 1) As shown.

ここでＺ_ＶＣＯは、ＶＣＯ１０１の負荷インピーダンス、ＬはＶＣＯ１０１のインダクタ値、ＣはＶＣＯ１０１の可変容量値である。また、このときのＺ_ＶＣＯにおいてはインダクタと容量値が支配的であるためΔＺをΔＬとΔＣに置き換えると、（数２）に示すようになる。

Here, Z _VCO is a load impedance of the VCO 101, L is an inductor value of the VCO 101, and C is a variable capacitance value of the VCO 101. In addition, since the inductor and the capacitance value are dominant in the Z _{VCO at} this time, when ΔZ is replaced with ΔL and ΔC, (Formula 2) is obtained.

ＶＣＯ１０１のクロック信号の周波数ｆはＬＣ共振回路によって、（数３）に示すようになる。

The frequency f of the clock signal of the VCO 101 is represented by (Equation 3) by the LC resonance circuit.

したがって、（数４）に示すように、負荷変動によって周波数変動Δｆが生じる。

Therefore, as shown in (Equation 4), the frequency fluctuation Δf is caused by the load fluctuation.

しかし、ＰＬＬ回路はＶＣＯ１０１のクロック信号が常にロックの状態になるように保持しようとするため、負荷変動によってクロック信号の周波数変動が起こるのは通常数ｕｓｅｃ程度となるが、アプリケーションによっては、数ｕｓｅｃの周波数変動も規格外れになる場合があるため、クロック信号の周波数変動が問題になる。

However, since the PLL circuit tries to hold the clock signal of the VCO 101 so that the clock signal is always locked, the frequency fluctuation of the clock signal due to the load fluctuation usually occurs on the order of several usec. The frequency variation of the clock signal may also be out of specification, so that the frequency variation of the clock signal becomes a problem.

  Therefore, as in this embodiment, the impedance of ΔZ caused by the load fluctuation is corrected by ΔC ′ when the operation of the mixer is turned on so that the variable capacitance values (Equation 5) and (Equation 6) are satisfied. As a result, the frequency fluctuation of Δf can be suppressed.

ここで、可変容量値は（数７），（数８）で決定される。

Here, the variable capacitance value is determined by (Equation 7) and (Equation 8).

ここで、Ｖｔはループフィルタ１０５から入力される電圧、Ｖｃは補正電圧であり、周波数変動が生じないときにはＶｃは接地状態にある。仮に、クロック信号が５ＧＨｚで周波数変動が１ＭＨｚ、インダクタ値が０．５ｎＨの場合、（数３）の式より、Ｃ＋Ｃ’＝１.０１２ｐＦ，Ｃ＝２.０２６ｐＦとなり、（数９）のようになる。

Here, Vt is a voltage input from the loop filter 105, Vc is a correction voltage, and Vc is in a grounded state when frequency fluctuation does not occur. If the clock signal is 5 GHz, the frequency variation is 1 MHz, and the inductor value is 0.5 nH, C + C ′ = 1.012 pF and C = 2.026 pF from the equation (3), as shown in (Equation 9) Become.

この結果、（数７）の式により、（数１０）のようになる。

As a result, (Equation 10) is obtained from the equation (Equation 7).

また、Ｑ＝ＣＶによりΔＶ＝Ｖとなることから、｜Ｖｔ−Ｖｃ｜＝２ＶとなるようなＶｃを検出回路を介して印加すればよい。

Since Q = CV and ΔV = V, Vc such that | Vt−Vc | = 2V may be applied via the detection circuit.

  The present invention is applicable to an oscillator, and is particularly effective when applied to an oscillator that can be used in a PLL circuit having a voltage controlled oscillator such as a mobile communication device.

The block diagram which shows schematic structure in the oscillator of embodiment of this invention Block diagram of a PLL circuit included in the RF section of the oscillator in this embodiment The block diagram which shows the basic composition of the charge pump circuit contained in the oscillator in this embodiment The block diagram which shows the basic composition of the low pass filter contained in the oscillator in this embodiment The block diagram which shows the basic composition of the voltage control oscillator contained in the oscillator in this embodiment

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Voltage controlled oscillator 102 Counter circuit 103 Phase comparator 104 Charge pump circuit 105 Loop filter 106 Detection circuit 201-202 Charge pump input line 203 Charge pump output line 211 p-type MOSFET
212 n-type MOSFET
301 Loop filter input lines 302 to 303 Capacitor 304 Resistor 305 Loop filter output lines 404 to 404 n-type MOSFET
405 to 406 Resistors 407 to 408 Capacitors 409 to 510 Inductor 411 Variable power supply 412 Variable capacitance

Claims (6)

  An antenna, an RF (Radio Frequency) unit that processes a signal input to the antenna into a low-frequency signal, and a processing unit that processes data transmitted by the low-frequency signal processed in the RF unit without a bit error; An oscillator comprising:   The oscillator according to claim 1, wherein a PLL (Phase Lock Loop) circuit having a small frequency fluctuation is provided in the RF unit so that the processing unit performs processing without bit error.   The PLL circuit includes a counter circuit that divides a signal output from a voltage controlled oscillator, a phase comparator that compares phases of reference signals, and a charge pump that increases or decreases an output current based on a comparison result of the phase comparator. A circuit, a loop filter that removes a high-frequency component from the output current of the charge pump circuit, converts it into a voltage and applies it to the voltage-controlled oscillator, and a detection circuit that detects a frequency shift caused by a frequency fluctuation, When the frequency of the clock signal whose phase matches that of the reference signal suddenly fluctuates due to an external factor, the fluctuating frequency deviation is detected by the detection circuit and forcibly corrected to suppress the frequency deviation. The oscillator according to claim 1 or 2, characterized in that   The voltage controlled oscillator is provided with a resonance circuit composed of a variable capacitor and an inductor, and a voltage obtained by converting a current output from the charge pump circuit through the loop filter is applied to the variable capacitor, The configuration is such that the clock signal having a desired frequency of a voltage controlled oscillator is output, and the detection circuit detects a frequency shift that fluctuates when the frequency of the clock signal suddenly fluctuates due to an external factor, and the loop 4. The oscillator according to claim 3, further comprising a circuit that forcibly corrects the capacitance of the variable capacitor that varies according to the output voltage of the filter.   When the frequency of the clock signal output from the voltage-controlled oscillator whose phase matches that of the reference signal is abruptly fluctuated due to an external factor, the fluctuation of the fluctuating frequency is detected by the detection circuit, and the correction voltage is forcibly corrected. Is applied to a terminal opposite to the terminal to which the output voltage of the loop filter of the variable capacitor to which the output voltage of the loop filter is applied, to forcibly correct the frequency deviation of the clock signal. 5. The oscillator according to claim 3, wherein frequency fluctuation of the clock signal is prevented.   By detecting the frequency fluctuation of the clock signal by the detection circuit and applying the detection signal from the detection circuit as a correction voltage to the variable capacitor, the frequency fluctuation is forced before the output voltage from the loop filter is controlled. The oscillator according to any one of claims 3 to 5, wherein the voltage controlled oscillator is configured to suppress frequency fluctuation and reduce frequency fluctuation.

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