JP2005191226A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem in a bipolar transistor providing the collector electrode on the surface, in which the diffusing region which is to become the extraction of electrode must be extended up to a first collector embedding layer provided at the lower part of the collector region, that the collector resistance can be reduced by improving impurity concentration of the first collector embedding layer, but that the width of collector region becomes narrow, and that the dielectric strength becomes deteriorated. <P>SOLUTION: A second collector embedding layer is provided to a first collector embedding layer and a contact of a diffusing region. Moreover, the second collector embedding layer is impurity, having the diffusion coefficient larger than that of the first collector embedding layer and also having higher concentration. The first collector embedding layer adopts impurity having a small diffusion coefficient. Thus, upper diffusion of the first collector embedding layer is controlled, and the second collector embedding layer can be diffused to the upper region. Since the contact resistance with the diffusion region can be reduced, reduction in the collector resistance due to reduction of contact resistance can be realized, while the predetermined dielectric strength is acquired. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device that reduces collector resistance and a manufacturing method thereof.

  FIG. 7 is a cross-sectional view showing an example of a bipolar transistor. The figure shows an npn type bipolar transistor having a structure in which a collector electrode is taken out from the substrate surface.

  The substrate is a p-type semiconductor substrate 31, and a collector region 32 is provided on the n-type epitaxial layer, for example.

  An n + type collector buried layer 33 is provided at the interface between the p type substrate 31 and the n− type epitaxial layer 32. Further, an n + type diffusion region 38 is provided by diffusing impurities from the substrate surface. The n + -type diffusion region 38 is diffused to the depth of the collector buried layer 33 and is in contact with the collector buried layer 33. The n + type diffusion region 38 is in contact with the collector electrode 51 provided on the substrate surface, and the collector is taken out from the substrate surface.

  A LOCOS oxide film 34 is provided in the collector region 32 on the collector buried layer 33, and a base region 50 and an emitter region 46 are provided on the substrate surface between the LOCOS oxide films 34.

  The base region 50 includes an external base region 39 and an intrinsic base region 41. For example, a plurality of base regions 50 are arranged between the LOCOS oxide films 34 in a comb shape. An emitter region 46 is provided on the surface of each intrinsic base region 41. A base lead electrode 37 and an emitter lead electrode 45 made of a conductive material that also serves as an impurity diffusion source for forming the respective regions are brought into contact with the external base region 39 and the emitter region 46. A base electrode 48 and an emitter electrode 49 connected to the respective lead electrodes through through holes TH provided in the insulating film 47 and the TEOS film 36 are provided. Further, a collector electrode 51 connected to the collector region 32 is provided. (For example, refer to Patent Document 1).

  Next, a conventional bipolar transistor manufacturing method will be described with reference to FIGS.

  First, a mask 100 in which a region where a collector buried layer is to be formed is opened is provided on a p-type silicon substrate 31, and n-type impurities are ion-implanted. At this time, a thin oxide film (not shown) is formed in the opening to protect the surface (FIG. 8A). Thereafter, the oxide film is removed, and an n − type epitaxial layer is stacked to form a collector region 32. As the epitaxial growth proceeds, the n-type impurities diffuse vertically, and an n + -type collector buried layer 33 is formed at the interface between the n − -type epitaxial layer 32 and the p-type substrate 31 (FIG. 8B).

  Further, n-type impurities are ion-implanted and diffused in a region where a collector electrode is to be formed. As a result, an n + -type diffusion region 38 reaching the collector buried layer 33 is formed (FIG. 9).

  Thereafter, an element region is formed. First, the LOCOS oxide film 34 is formed at a predetermined position. A polysilicon layer in contact with the substrate surface exposed between the LOCOS oxide films 34 and a TEOS film 36 are deposited, an opening OP is formed in a region where an emitter region is to be formed, and a base extraction electrode also serving as a base diffusion source 37 is formed. An insulating film 40 for surface protection is formed in the opening OP, and p-type impurities are ion-implanted.

  Next, heat treatment is performed for a short time, and impurities are diffused to form the intrinsic base region 41. Further, p-type impurities in the base diffusion source 37 are diffused to the surface of the collector region 32 by the same heat treatment process. The base diffusion source 37 is doped with a p-type impurity, and an external base region 39 is formed by diffusion. The intrinsic base region 41 contacts near the surface of the external base region 39 (FIG. 10A).

  Thereafter, in order to secure the distance between the external base region 39 and the emitter region formed in a later process by self-alignment, a sidewall 43 is formed in the opening OP. The insulating film 40 at the bottom of the opening OP is removed to form an emitter contact portion. Polysilicon is deposited again, and an emitter extraction electrode 45 serving as an emitter diffusion source is formed in the opening OP. Thereafter, n-type impurities are diffused from the emitter diffusion source to the surface of the intrinsic base region 41 to form an emitter region 46 (FIG. 10B).

Further, an insulating film 47 is formed for planarization, and through holes TH are formed in the insulating film 47 and the TEOS film 36. A base electrode 48 that contacts the base lead electrode 37 through the through hole TH is formed, and an emitter electrode 49 that contacts the emitter lead electrode 45 is formed. Further, a collector electrode 51 in contact with the n + type diffusion region 38 is formed to obtain the final structure shown in FIG.
Japanese Patent Laid-Open No. 2001-358152 (page 3, FIG. 1)

  In the structure in which the collector electrode is provided on the back surface of the element and connected to the lead frame, a base-collector capacitance is generated between the base pad electrode connected to the base electrode and the frame (collector electrode). On the other hand, an element having a structure in which the collector electrode is extracted from the substrate surface as shown in FIG. 7 connects the lead frame to the emitter electrode. In this case, although base-emitter capacitance is generated between the base pad electrode and the lead frame (emitter electrode), it has less influence on high-frequency characteristics than the base-collector capacitance, which is preferable. In such an element, a p-type substrate 31 is provided, and the collector is taken out from the substrate surface by the collector buried layer 33 and the n + -type diffusion region 38.

In a bipolar transistor, a reduction in collector resistance is a major factor in improving high-frequency characteristics. Reduction of the collector resistance is also effective in reducing the collector-emitter saturation voltage (hereinafter referred to as _{VCE (sat)),} and a lower _{VCE (sat)} is preferable because power consumption can be reduced.

  In the conventional structure, the collector resistance is the total resistance of the low concentration collector region 32 and the collector buried layer 33 and the n + -type diffusion region 38 serving as a current path. Therefore, when the collector resistance is reduced, the implantation dose when forming the collector buried layer 33 is increased, and the contact resistance with the n + -type diffusion region 38 formed from the substrate surface is reduced. When the impurity concentration in the entire region of the collector buried layer 33 is increased, the vertical diffusion of the collector buried layer 33 is further advanced and the width of the low concentration collector region 32 is narrowed.

That is, the resistance of the contact portion between the collector buried layer 33 and the n + -type diffusion region 38 is reduced, and the width of the low-concentration collector region 32 just below the emitter region 46 is narrowed, and the region with a high impurity concentration is increased in the collector region. As a result, the collector resistance is reduced, which can contribute to the reduction of _{VCE (sat)} . For this reason, the output waveform is not distorted, for example, for use as an oscillator.

  However, when the low concentration region of the collector region 32 is narrowed, the breakdown voltage (VCEO) between the collector and the emitter is lowered. This is because when the depletion layer that has expanded the low concentration region by applying the bias reaches the collector buried layer 33 where the concentration rapidly increases, the depletion layer cannot expand any more and yields. That is, since the interface between the collector region 32 and the collector buried layer 33 approaches the base region 50, the breakdown voltage decreases and the breakdown voltage deteriorates.

  That is, a reduction in contact resistance at the contact portion from the collector buried layer and the substrate surface and a VCEO characteristic are traded off, and it is difficult to achieve both of them.

  The present invention has been made in view of such problems. First, a one-conductivity-type semiconductor substrate, a reverse-conductivity-type collector region provided on the semiconductor substrate, and a one-conductivity-type semiconductor substrate provided on the collector region surface. A base region, a reverse conductivity type emitter region provided on the surface of the base region, a reverse conductivity type first buried layer provided at an interface between the semiconductor substrate and the collector region, and the substrate surface A reverse conductivity type diffusion region provided so as to reach the vicinity of the first buried layer; and a reverse conductivity type second buried layer provided below the diffusion region and in contact with the diffusion region and the first buried layer; It solves by having.

  Further, the second buried layer has a higher impurity concentration than the first buried layer.

  Further, the second buried layer is provided with a width equal to or larger than that of the diffusion region.

  Further, the second buried layer is provided by an impurity having a diffusion coefficient larger than that of the first buried layer.

  Further, the diffusion region is connected to a collector electrode provided on the substrate surface.

  Second, a reverse conductivity type first buried layer and a reverse conductivity type second buried layer in contact with a part of the first buried layer are provided on a one conductivity type semiconductor substrate. Forming a collector region; forming a reverse conductivity type diffusion region reaching the second buried layer from the collector region surface; forming a one conductivity type base region on the collector region surface; And a step of forming a reverse conductivity type emitter region on the surface of the base region.

  Further, the second buried layer is formed by diffusing up to a position above the first buried layer.

  A step of forming an emitter electrode and a base electrode in contact with the emitter region and the base region, respectively, and forming a collector electrode in contact with the diffusion region on the surface of the substrate; .

According to the present invention, first, the contact resistance between the first collector buried layer and the n + -type diffusion region can be reduced by the second collector buried layer, so that the collector resistance can be reduced and V _{CE (sat)} is reduced. it can.

  Second, by using an impurity having a small diffusion coefficient in the first collector buried layer, it is possible to suppress the rise of impurities in the collector buried layer and to secure a predetermined width of the low concentration region of the collector region. The collector resistance can be reduced by suppressing the deterioration of the collector.

  Third, since the second collector buried layer has a larger diffusion coefficient than the first collector buried layer, the second collector buried layer rises upward, has good contact with the n + -type diffusion region, and takes out the collector. A region with a high impurity concentration can be expanded in the path.

  Therefore, the contact resistance between the first collector buried layer and the n + -type diffusion region can be reduced without degrading the VCEO characteristics, and the total collector resistance can be reduced.

  With reference to FIGS. 1 to 6, the semiconductor device of the present invention will be described by taking an npn bipolar transistor as an example.

  The bipolar transistor includes a semiconductor substrate 1, a collector region 2, a base region 20, an emitter region 16, a first buried layer 3, a diffusion region 8, and a second buried layer 5.

  The substrate is a p-type silicon semiconductor substrate 1, and a collector region 2 is provided on the n-type epitaxial layer, for example.

  At the interface between the p-type semiconductor substrate 1 and the n − -type epitaxial layer 2, for example, an n + -type first collector buried layer 3 in which arsenic (As), antimony (Sb), or the like is diffused is provided. Further, an n + type diffusion region 8 is provided by diffusing impurities such as arsenic and phosphorus (P) from the substrate surface. The n + -type diffusion region 8 is diffused to a depth near the first collector buried layer 3.

  The second collector buried layer 5 is a diffusion layer of an n + type impurity such as phosphorus, for example, and is provided below the n + type diffusion region 8 with a width equal to or greater than that of the n + type diffusion region 8. The region 8 and the first collector buried layer 3 are contacted.

The implantation dose of the first collector buried layer 3 is about 2E15 cm ⁻² , and the implantation dose of the second collector buried layer 5 is about 1E16 cm ⁻² . Impurity concentration after activation by heat treatment is first collector buried layer 3 is about 1E19 cm ^-3, the second collector buried layer 5 is about 2E21cm ^-3.

  The second collector buried layer 5 is provided so as to overlap the contact portion between the n + type diffusion region 8 and the first collector buried layer 3. In addition, at least the n + type diffusion region and the first collector buried layer 3 may be in contact with each other via the second collector buried layer 5, but in order to reduce the collector resistance, the n + type diffusion region 8 and the first collector region 8 are arranged. It is preferable to overlap with the contact portion with 1 collector buried layer 3.

  Even when the epitaxial layer is thick, the second collector buried layer 5 can make contact.

  A LOCOS oxide film 4 is provided in the collector region 2 on the first collector buried layer 3, and a base region 20 and an emitter region 16 are provided on the substrate surface between the LOCOS oxide films 4. The base region 20 includes an external base region 9 and an intrinsic base region 11. For example, a plurality of base regions 20 are arranged in a comb shape between the LOCOS oxide films 4. An emitter region 16 is provided on the surface of each intrinsic base region 11. The external base region 9 and the emitter region 16 are contacted with a base lead electrode 7 and an emitter lead electrode 15 made of a conductive material that also serves as an impurity diffusion source for forming the respective regions, and a base electrode 18 and an emitter connected to the base base electrode 7 and the emitter lead electrode 15, respectively. An electrode 19 is provided. The collector electrode 21 is in contact with the n + -type diffusion region 8 and provided on the substrate surface.

  Since the first collector buried layer 3 is an impurity diffusion layer having a small diffusion coefficient, it does not diffuse so much upward and downward with the epitaxial growth. On the other hand, the impurity of the second collector buried layer 5 has a larger diffusion coefficient and higher concentration than the impurity of the first collector buried layer 3. That is, the second collector buried layer 5 is diffused up (and below) the first collector buried layer 3 together with the epitaxial growth.

  On the other hand, the n + -type diffusion region 8 is a region formed by diffusion under conditions that reach the first collector buried layer 3. That is, the depth corresponding to the thickness of the collector region 2 has to be diffused, but there is a problem in that the tip of the n + -type diffusion region 8 has a reduced impurity concentration and the contact resistance here increases.

  However, according to the present embodiment, by using the rising of the second collector buried layer 5, the impurity concentration at the junction between the n + -type diffusion region 8 and the first collector buried layer 3 can be increased, and the contact resistance is increased. Can be reduced. Even if the contact between the n + -type diffusion region 8 and the first collector buried layer 3 is insufficient, the second collector buried layer 5 can reliably connect the both.

  In the bipolar transistor, it is desired to reduce the collector resistance, and the collector resistance can be reduced by improving the impurity concentration of the first collector buried layer 3. However, when the impurity concentration of the first collector buried layer 3 is improved, upward diffusion also proceeds. As a result, the collector resistance is reduced, but there is a problem that the collector region 2 becomes thin and the breakdown voltage deteriorates.

  However, in the present embodiment, the first collector buried layer 3 is arsenic or antimony. Therefore, since upward (downward) diffusion does not progress so much, a predetermined thickness of the collector region 2 can be secured and a breakdown voltage can be secured.

  The second collector buried layer 5 is phosphorus having a large diffusion coefficient and a high impurity concentration. As a result, the high-concentration region extends above the first collector buried layer 3 and the contact resistance can be reduced, which can contribute to the reduction of the collector resistance.

  That is, it is possible to provide a semiconductor device having both a predetermined breakdown voltage and a reduction in collector resistance due to a reduction in contact resistance.

  Next, an example of a method for manufacturing the bipolar transistor of this embodiment will be described with reference to FIGS. 2 to 6 and FIG.

  In the bipolar transistor manufacturing method, a reverse conductivity type first buried layer and a reverse conductivity type second buried layer in contact with a part of the first buried layer are provided on a one conductivity type semiconductor substrate. Forming a collector region of the mold, forming a reverse conductivity type diffusion region reaching the second buried layer from the collector region surface, forming a one conductivity type base region on the collector region surface, Forming a reverse conductivity type emitter region on the surface of the base region.

  First step (see FIGS. 2 and 3): a reverse conductivity type first buried layer and a reverse conductivity type second buried layer in contact with a part of the first buried layer on a one conductivity type semiconductor substrate. Forming a reverse conductivity type collector region provided with

First, in FIG. 2, a mask 100 having an opening to form a first collector buried layer is provided on a p-type silicon substrate 1, and an n-type impurity such as arsenic is applied at a dose of 2E15 cm ⁻² and an acceleration energy of about 100 KeV. Ion implantation is performed under conditions. At this time, a thin oxide film (not shown) is formed in the opening to protect the surface (FIG. 2A). Further, a mask 100 having an opening in the second collector buried layer formation planned region is formed, and an n-type impurity (for example, phosphorus) having a diffusion coefficient larger than that of the first collector buried layer is set at a dose of 1E16 cm ⁻² and an acceleration energy of about 20 KeV. Ion implantation.

  Note that the region where the second collector buried layer is to be formed is a region which partially overlaps the region where the first collector buried layer is to be formed and is located below the region where the collector electrode is to be formed (FIG. 2B).

  Thereafter, as shown in FIG. 3, the oxide film is removed, and an n − type epitaxial layer having a specific resistance of 0.6 Ωcm and a thickness of about 1.5 μm is laminated to form the collector region 2. Along with the epitaxial growth, the first collector buried layer 3 and the second collector buried layer 5 diffuse up and down, and the n + -type first collector buried layer 3 is formed at the interface between the n − -type epitaxial layer 2 and the p-type substrate 1. A two-collector buried layer 5 is formed.

  At this time, phosphorus in the second collector buried layer 5 has a higher diffusion coefficient and higher concentration than arsenic in the first collector buried layer 3, so that diffusion proceeds upward (and downward) from the first collector buried layer 3.

  Second step (see FIG. 4): a step of forming a reverse conductivity type diffusion region reaching the second buried layer from the collector region surface.

Thereafter, an insulating film in a region where a collector electrode is to be formed is opened, and n-type impurities such as phosphorus are ion-implanted. The ion implantation conditions are a dose of 5E15 cm ⁻² and an acceleration energy of about 100 KeV (FIG. 4A).

  After that, the n + -type diffusion region 8 that reaches at least the second collector buried layer 5 is formed by diffusion by heat treatment. The n + -type diffusion region 8 is diffused under conditions that reach the first collector buried layer 3, and the second collector buried layer 5 is formed so as to overlap the contact portions of both. Thereby, the resistance of the contact portion can be reduced (FIG. 4B).

  The second collector buried layer 5 has a higher impurity concentration than the first collector buried layer 3 and is diffused upward. Therefore, even if the contact between the tip of the n + -type diffusion region 8 and the first collector buried layer 3 is insufficient, the second collector buried layer 5 can reliably connect the two.

  Third step (see FIGS. 5 and 6): a step of forming a base region of one conductivity type on the surface of the collector region and forming an emitter region of reverse conductivity type on the surface of the base region.

  Thereafter, an element region is formed. First, in FIG. 5, the LOCOS oxide film 4 is formed at a predetermined position. A polysilicon layer in contact with the substrate surface exposed between the LOCOS oxide films 4 is deposited, and a TEOS film 6 is formed thereon. An opening OP is formed by opening the polysilicon layer and the region where the emitter region of the TEOS film 6 is to be formed. As a result, a base take-out electrode 7 which also serves as a base diffusion source is formed. After forming the insulating film 10 for protecting the substrate surface in the opening OP, p-type impurities are ion-implanted (FIG. 5A).

  Thereafter, the intrinsic base region 11 is formed by performing a short heat treatment. Further, the p-type impurity in the base diffusion source 7 is diffused on the surface of the collector region 2 by the same heat treatment process. The base diffusion source 7 is doped with p-type impurities, and an external base region 9 is formed by diffusion. Intrinsic base region 11 contacts near the surface of external base region 9 (FIG. 5B).

  Next, in FIG. 6, the sidewall 13 is formed in the opening OP in order to secure the distance between the external base region 9 and the emitter region formed in a later process by self-alignment. Further, in order to form the emitter region, the insulating film 10 at the bottom of the opening OP is removed to form the emitter contact portion EC (FIG. 6A).

  Polysilicon is deposited again, and an emitter lead electrode 15 serving as an emitter diffusion source is formed in the opening OP. Thereafter, n-type impurities are diffused from the emitter diffusion source 15 to the surface of the intrinsic base region 11 to form the emitter region 16 (FIG. 6B).

  Further, an insulating film 17 is formed for planarization, and a through hole TH is formed in the insulating film 17 and the TEOS film 6. A base electrode 18 in contact with the base lead electrode 7 is formed through the through hole TH, and an emitter electrode 19 in contact with the emitter lead electrode 15 is formed.

Further, a collector electrode 21 in contact with the n + -type diffusion region 8 is formed to obtain the final structure shown in FIG. The collector electrode 21 is formed on the substrate surface in the same manner as the base electrode 18 and the emitter electrode 19.

It is sectional drawing explaining the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the conventional semiconductor device. It is sectional drawing explaining the manufacturing method of the conventional semiconductor device. It is sectional drawing explaining the manufacturing method of the conventional semiconductor device. It is sectional drawing explaining the manufacturing method of the conventional semiconductor device.

Explanation of symbols

1 p-type silicon substrate 2 collector region 3 first collector buried layer 4 LOCOS oxide film 5 second collector buried layer 6 TEOS film 7 base extraction electrode 8 n + type diffusion region 9 external base region 10 insulating film 11 intrinsic base region 13 sidewall 15 Emitter extraction electrode
16 emitter region 17 insulating film 18 base electrode 19 emitter electrode 20 base region 21 collector electrode 31 p-type silicon substrate 32 collector region 33 collector buried layer 34 LOCOS oxide film 36 TEOS film 37 base lead electrode 38 n + type diffusion region 39 external base region 40 Insulating film 41 Intrinsic base region 43 Side wall
45 Emitter extraction electrode
46 Emitter region 47 Insulating film 48 Base electrode 49 Emitter electrode 50 Base region 51 Collector electrode 100 Insulating film TH Through hole EC Emitter contact part OP Opening part

Claims (8)

A semiconductor substrate of one conductivity type;
A reverse conductivity type collector region provided on the semiconductor substrate;
A base region of one conductivity type provided on the collector region surface;
A reverse conductivity type emitter region provided on the surface of the base region;
A reverse conductivity type first buried layer provided at an interface between the semiconductor substrate and the collector region;
A reverse conductivity type diffusion region provided from the substrate surface to the vicinity of the first buried layer;
A semiconductor device comprising: a second buried layer of a reverse conductivity type provided under the diffusion region and in contact with the diffusion region and the first buried layer. The semiconductor device according to claim 1, wherein the second buried layer has an impurity concentration higher than that of the first buried layer. The semiconductor device according to claim 1, wherein the second buried layer is provided with a width equal to or greater than that of the diffusion region. The semiconductor device according to claim 1, wherein the second buried layer is provided with an impurity having a diffusion coefficient larger than that of the first buried layer. 2. The semiconductor device according to claim 1, wherein the diffusion region is connected to a collector electrode provided on the substrate surface. On the one conductivity type semiconductor substrate, a reverse conductivity type collector region is provided in which a reverse conductivity type first buried layer and a reverse conductivity type second buried layer in contact with a part of the first buried layer are provided. And a process of
Forming a reverse conductivity type diffusion region reaching the second buried layer from the collector region surface;
Forming a base region of one conductivity type on the surface of the collector region and forming an emitter region of reverse conductivity type on the surface of the base region. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the second buried layer is formed by diffusing up to a position above the first buried layer. The method includes: forming an emitter electrode and a base electrode in contact with the emitter region and a base region, respectively, and forming a collector electrode in contact with the diffusion region on the surface of the substrate. Semiconductor device manufacturing method.

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