JP2005190665A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an EEPROM which improves the speed of a read-out operation, with almost no increase in a chip area. <P>SOLUTION: This EEPROM comprises a memory cell array which is located so that a plurality of NAND cells consisting of nonvolatile memory devices share a source line to constitute a block, and which is located so that a plurality of the blocks share a bit line on one end side and the source line on the other end side; a column decoder which selects the bit line of the memory cell array; and a row decoder which selects a word line of memory cells and gate lines of selector transistors. The gate lines SG2 of the selector transistors on the source line side which adjoins each other between respective blocks are connected in common, and connected with the same contact to a wiring driven by the row decoder. The row decoder selects the gate lines SG2 of the selector transistors on the source line side in a set, which adjoin each other between blocks. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM).

  As one type of EEPROM, a NAND cell type EEPROM capable of high integration is known. In this method, a plurality of memory cells are connected in series in such a manner that their adjacent sources and drains are shared with each other and connected to a bit line as a unit. A memory cell usually has an FET-MOS structure in which a floating gate (charge storage layer) and a control gate are stacked. The memory cell array is integrated in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to the bit line via the selection gate, and the source side is also connected to the source line via the selection gate. The control gates of the memory cells are continuously arranged in the row direction to become word lines.

  The operation of this NAND cell type EEPROM is as follows.

  The data write operation is performed in order from the memory cell farthest from the bit line. A high voltage Vpp (= about 20V) is applied to the control gate of the selected memory cell, and an intermediate potential VppM (= about 10V) is applied to the control gate and the selection gate of the memory cell on the bit line side. The bit line is given 0 V or an intermediate potential according to the data.

  When 0 V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. As a result, the threshold value of the selected memory cell is shifted in the positive direction. This state is, for example, “1”. When an intermediate potential is applied to the bit line, electron injection does not occur, so the threshold value does not change and remains negative. This state is “0”.

  In data erasure, the control gate connected to the memory cell to be erased is set to 0 V, the bit line and the source line are in a floating state, the control gate connected to the memory cell not to be erased, all the selection gates, and the p-type well. A high voltage of 20 V is applied to the n-type substrate. As a result, electrons in the floating gate are released to the p-type well in the memory cell to be erased, and the threshold value is shifted in the negative direction.

  In the data read operation, the control gate of the selected memory cell is set to 0 V, and the control gates and select gates of the other memory cells are set to the power supply potential Vcc (= 5 V) to detect whether a current flows in the selected memory cell. Is done.

  The bit line contact side selection gate and the source line side selection gate of such a NAND cell type EERROM are both composed of two wirings having different resistances formed in parallel with an interlayer insulating film interposed therebetween. Are connected at several locations (or several tens) in the memory cell array. In this selection gate connection region, the distance between the two selection gates sandwiching the bit line contact is relatively long. Therefore, the two selection gates sandwiching the bit line contact are connected to two wirings separately. Yes.

  On the other hand, since the distance between the two selection gates sandwiching the source line is short, wiring connection cannot be performed separately at the two selection gates sandwiching the source line. The two select gates are short-circuited, and the wiring connection is made as the same node. Therefore, in the NAND cell type EEPROM, the two selection gates sandwiching the source line are at the same potential.

  In such a row decoder in the NAND cell type EEPROM, only a decode signal in units of blocks exists as a decode signal. For this reason, the SG2 node, which requires a special decoding method in which the selected block and the adjacent block on the source line side of the selected block are decoded as a set, is not decoded, and a method of setting the same potential in all blocks has been used.

  During the write / read operation, the bit line contact side select gate SG1 is in the “L” state in the non-selected block, and in the non-selected block, the bit line and the memory cell are turned off by the bit line contact side select gate. Therefore, no malfunction occurs in the unselected block regardless of the voltage of the source side select gate SG2. That is, since a highly reliable write / read operation can be realized, there is no problem in operation reliability even if all the source side select gate SG2 potentials in the non-selected block are the same as the SG2 potential in the selected block. In view of the above, a method in which the source line side selection gate is set to the same potential in all blocks has been conventionally used.

  As is apparent from the above description of the operation, in the NAND cell type EEPROM, at the time of read operation, a control gate other than one selected control gate in the selected block, and one bit line contact side select gate in the selected block. , And the source line side select gates in all blocks are charged to the power supply voltage. Further, before the read operation is completed, the node charged to Vcc is discharged to 0V. In this case, the number of source line side selection gates to be charged to the Vcc potential and discharged to 0 V is several hundred to several thousand, and the capacity becomes a huge value. There is a problem that the time required for charging and discharging becomes longer and the time required for reading operation becomes longer.

  In addition, in order to shorten the time required for charging / discharging the source line side selection gate, the wiring width of the wirings other than those in the memory cell array among the wirings when performing the charging / discharging operation of the source line side selection gate is increased. However, when a method such as increasing the size of an element related to the charge / discharge operation is used, there is a problem that the chip area is greatly increased.

  As described above, in the conventional NAND cell type EEPROM, since the source line side selection gates in all blocks are set to the same potential, the time required for the charge / discharge operation of the source line side selection gates becomes longer and the read operation becomes longer. There was a problem of becoming. In order to solve this problem, when the wiring width is increased or the element size is increased, there is a problem that the chip area increases due to an increase in the control circuit area and the wiring area.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an EEPROM capable of speeding up a read operation without substantially increasing the chip area.

  In order to solve the above problems, the present invention adopts the following configuration.

  That is, a semiconductor memory device according to one embodiment of the present invention includes one or a plurality of nonvolatile memory cells connected to each other, a first selection transistor connected to one end of the memory cell, and the memory cell. A second select transistor connected to the other end of the memory cell, a memory cell unit including the memory cell and the first and second select transistors, and a memory cell array in which the memory cell units are arranged in an array. A word line provided by connecting a plurality of gates of the memory cell and a first selection provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor. A second selection gate provided in a direction parallel to the word line is formed by connecting a plurality of gate lines and the gates of the second selection transistors. A block composed of one or more word lines and the first and second select gate lines, and at least one of the memory cell arrays includes first, second, and third lines. There are a plurality of blocks including the first block, the first block, the second block, and the third block are different from each other, and the first selection gate line and the second block in the first block The first selection gate line is connected directly or via another wiring layer, and during the first operation, the first block in the first block is selected when the first block or the second block is selected. Both the one selection gate line and the first selection gate line in the second block are at the first voltage, and the first selection gate line in the third block is in a non-selected state. Features.

  According to the present invention, the gate charge / discharge time of the selection transistor during the read operation can be shortened without increasing the chip area, and the read operation can be speeded up.

  The details of the present invention will be described below with reference to the illustrated embodiments.

  FIG. 1 is a block diagram showing a NAND cell type EEPROM system configuration according to an embodiment of the present invention. In order to perform data write, read, rewrite, write verify read, and erase verify read for the memory cell array 1, a bit line control circuit 2 is provided. Bit line control circuit 2 is connected to data input / output buffer 6 and receives as an input the output of column decoder 3 that receives an address signal from address buffer 4. Further, a row decoder 5 is provided for controlling the control gate and the selection gate for the memory cell array 1, and a substrate potential control for controlling the potential of the p substrate (or p-type well) on which the memory cell array 1 is formed. A circuit 7 is provided.

  2A and 2B are a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array, and FIGS. 3A and 3B are A-A ′ and B in FIG. 2A, respectively. It is -B 'sectional drawing. A memory cell array including a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well) 11 surrounded by the element isolation oxide film 12. If explanation is made by paying attention to one NAND cell, in this embodiment, eight memory cells M1 to M8 are connected in series to constitute one NAND cell.

  In each memory cell, floating gates 14 (141, 142,..., 148) are formed on the substrate 11 via a gate insulating film 13, and control gates 16 (161, 162,...) Are formed thereon via an interlayer insulating film 15. 168)). The n-type diffusion layers 19 that are the source and drain of these memory cells are connected so that adjacent ones are shared, and thereby the memory cells are connected in series.

  Select gates 149 and 169 and 1410 and 1610 formed simultaneously with the floating gate and the control gate of the memory cell are provided on the drain side and the source side of the NAND cell, respectively. The substrate on which the element is formed is covered with a CVD oxide film 17, and a bit line 18 is disposed thereon. The bit line 18 is in contact with the drain side diffusion layer 19 at one end of the NAND cell. The control gates 16 of the NAND cells arranged in the row direction are commonly arranged as control gate lines CG (1), CG (2),... CG (8). These control gate lines become word lines. The selection gates 149, 169 and 1410, 1610 are also arranged as selection gate lines SG1, SG2 continuously in the row direction, respectively.

  Note that the gate insulating film 13 between the select gates 149 and 1410 and the substrate 11 may be formed thicker than the gate insulating film of the memory cell portion to increase its reliability.

  FIG. 4 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix.

  FIG. 5 is a plan view of a plurality of NAND cell arrays in the memory cell array, FIGS. 6A and 6B are plan views of portions (I) and (II) in FIG. 5, and FIG. These are CC 'sectional drawing of Fig.6 (a) (b). Also, the reference numerals indicating the nodes in FIG. 6 are the same as the symbols in FIG.

  In the NAND cell type EEPROM, as can be seen from FIGS. 2 and 3, the node 14 wiring is used as the gate electrode of the selection gate transistor, and the node 16 wiring is formed in parallel with the node 14 wiring with the interlayer insulating film 15 interposed therebetween. Yes. Since the node 14 wiring normally has high resistance, when only the node 14 wiring is used as the selection gate line, the time required for charging and discharging the selection gate line becomes long. In this case, the operation time of each chip is long. Invite time.

  In order to shorten the charging / discharging time of the selection gate line, the node 16 wiring and the node 14 wiring, whose resistance is set several times lower than that of the normal node 14 wiring, are connected at several places (or several tens of places) in the memory cell array. The method is used. In this case, an area for connecting the node 16 wiring and the node 14 wiring is provided in the memory cell array, and an area having a width L3 (hereinafter referred to as a selection gate) provided between the NAND cell arrays in FIG. This is called the connection area. In this selection gate connection region, as shown in FIGS. 6A and 6B, the node 16 wiring and the node 14 wiring are connected in both the bit line contact side selection gate SG1 and the source line side selection gate SG2. ing.

  In the bit line contact side select gate SG1, the distance L1 between the SG1 wirings sandwiching the bit line contact is long, so that the connection between the node 16 and the node 14 can be performed separately in SG1 sandwiching the bit line contact. However, since the source line side select gate SG2 has a short distance L2 between the SG2 lines sandwiching the source line, the connection between the nodes 16 and 14 cannot be performed separately in SG2 across the source line. As shown in FIG. 6B, in the selection gate connection region, the connection between the node 16 and the node 14 is performed while the two SG2 nodes sandwiching the source line are connected.

  The source line side select gate SG2 is at the same potential between adjacent blocks across the source line. In the selection gate connection region, the node 16 and the node 14 are connected by a low resistance wiring material. FIG. 6C shows a case where the node 16 and the node 14 are connected using the same wiring material as that of the bit line. It is also possible to connect the node 16 and the node 14 using a different wiring material from the bit line, the node 16 and the node 14. It is also possible to form a wiring material different from the node 16 in parallel with the node 14 and connect the wiring material different from the node 16 and the node 14 in the selection gate connection region.

  FIG. 7 shows an arrangement of NAND cell blocks and an arrangement of selection / control gates. Each NAND cell block is composed of a plurality of NAND cells sharing a source line. A plurality of NAND cell blocks are arranged so as to share a bit line on one end side and share a source line on the other end side. As described with reference to FIG. 6, it can be seen that SG2 has the same potential between the blocks across the source line side. Therefore, when one NAND cell block is selected, the SG2 potential of the adjacent block on the source line side of the selected block (hereinafter simply referred to as the adjacent block) is the same as the SG2 potential in the selected block. It becomes.

  FIG. 8 shows a timing chart of the read operation of the NAND cell type EEPROM in which the SG2 node is wired as shown in FIGS. However, the source line side adjacent block SG2 in FIG. 8 indicates the source line side adjacent block SG2 of the selected block.

  In the operation shown in FIG. 8, the allowable range of the threshold voltage of the memory cell for “1” data (a range that is higher than 0 V and lower than the voltage applied to the non-selected control gate in the selected block during the read operation). Increase the current flowing through the NAND cell (NAND cell including the selected memory cell with “0” data) that flows current during the read operation (the higher the voltage applied to the non-selected control gate in the selected block) (The current flowing through the NAND cell increases.) For the purpose of shortening the required read time, etc., the read in the case where the unselected control gate potential in the selected block is set to a voltage higher than the power supply voltage Vcc during the read operation. The operation is shown. However, it is assumed that a voltage higher than Vcc is generated by a reading high voltage generating circuit in the chip. The operation timing of FIG. 8 will be briefly described below.

  Before the read operation starts, the bit line is at a potential of 0 V or more and Vcc or less. At the start of the read operation, one of the eight control gates in the selected block is selected by the row address. When the read operation starts, all the bit lines are first charged to Vcc. Subsequently, the unselected control gates in the selected block (seven), the SG1 in the selected block, the SG2 in the selected block, and the SG2 in the adjacent block (on the source line side of the selected block) are charged from 0 V to Vcc. In this case, the time required for charging to the Vcc potential is determined by the resistance and capacitance of each wiring of the control gate and selection gate in the memory cell.

  The non-selection control gate in the selected block, SG1 in the selected block, SG2 in the selected block, and SG2 in the adjacent block (on the source line side of the selected block) are all the same as the wiring material of the node 16 in FIG. (However, SG1 and SG2 are the same wiring material as that of the node 16 when the resistance is lower among the wirings), and the wiring capacitance is similar, so that the non-selection control gate in the selected block, the SG1 in the selected block, The required charging time (corresponding to (A) in FIG. 8) is approximately the same in SG2 in the selected block and SG2 in the adjacent block (on the source line side of the selected block).

  Next, each node of the non-selection control gate in the selected block, SG1 in the selected block, SG2 in the selected block, and SG2 in the adjacent block (on the source line side of the selected block) becomes the output node VCGH of the read high voltage generation circuit. Connected. Subsequently, the read high voltage generation circuit starts generating a voltage higher than Vcc, and a voltage higher than Vcc is supplied to the output node VCGH of the read high voltage generation circuit. The nodes in the selected block SG1, the selected block SG2, and the SG2 in the adjacent block (on the source line side of the selected block) are also charged to a voltage higher than Vcc.

  At this time, the high-voltage load capacitance for reading includes seven control gates, three selection gates, and a high-voltage node in the row decoder (a VPPRW node in FIG. 9 (formed by a p-channel transistor in the HV broken line). The n-well capacitances are also included) and one of the nodes N1 and N2. When the read high voltage reaches the desired potential level VH, the node connected to the VCGH node or the VCGH node is kept at the VH potential for a while, and data is read from the selected memory cell to the bit line.

  Subsequently, each node of the non-selected control gate in the selected block, SG1 in the selected block, SG2 in the selected block, and SG2 in the adjacent block (on the source line side of the selected block) is discharged from VH to 0V. In this case, the time required for the discharge to 0 V potential is determined by the resistance and capacitance of each wiring of the control gate and selection gate in the memory cell. The non-selection control gate in the selected block, SG1 in the selected block, SG2 in the selected block, and SG2 in the adjacent block (on the source line side of the selected block) are all the same as the wiring material of the node 16 in FIG. (However, SG1 and SG2 are the same wiring material as that of the node 16 when the resistance is lower among the wirings), and the wiring capacitance is similar, so that the non-selection control gate in the selected block, the SG1 in the selected block, The required charging time (corresponding to (c) in FIG. 8) is approximately the same in SG2 in the selected block and SG2 in the adjacent block (on the source line side of the selected block).

  Subsequently, the read high voltage generation circuit finishes generating a voltage higher than Vcc, and the VCGH node is set to the Vcc potential. Further, the operation of reading out the voltage of the bit line by the sense amplifier and outputting it to the outside of the chip is performed, and then the reading operation is finished.

  As apparent from the operation timing of FIG. 8, only SG2 in the selected block and SG2 in the adjacent block (on the source line side of the selected block) among SG2 in all the blocks are removed from Vcc during the read operation. It becomes VH potential, and SG2 other than two are all kept at 0V.

  In this way, when a block is selected, SG2 in the adjacent block is selected together with SG2 in the selected block (on the source line side of the selected block), and the same potential as SG2 in the selected block is selected (in the selected block). SG2 in the adjacent block is set (for example, 0V → Vcc → VH → 0V during the read operation), and SG2 in other blocks is set to the set voltage (for example, in the non-selected block) It is a feature of the present invention that the voltage is set to 0 V during the read operation.

  However, the present invention is not limited to the read operation. When the present invention is used, the SG2 potential in the selected block is different from the SG2 potential in the non-selected block (except for the adjacent block on the source line side of the selected block). When the potential is set, SG2 in the adjacent block (on the source line side of the selected block) is kept at the same potential as the SG2 potential in the selected block even during a read operation.

  FIG. 9 shows a configuration example of the row decoder 5 for realizing the above-described present invention. The n-well potential in which the p-channel transistor in the HV broken line in FIG. 9 is formed is set to the VPPRW node potential. The signal RDENB is a signal for starting the NAND cell block selection operation, and the block corresponding to the row address is selected while the signal RDENB is “H”. The block decode signal is a signal having a different input signal type in each block. In the block corresponding to the row address, all the block decode signals are “H” and the signal RDENB is “H”. It becomes.

  The signals ERASE and ERASEB are “H” and “L” during the erasing operation, and are “L” and “H” except during the erasing operation. Signals SGD, CG1 to 8, SGS, and Vuss are signals having the same operation timing in any block regardless of selected / adjacent / non-selected blocks. The VPPRW node is at the same potential as the VCGH node during a read operation, and is charged to a high voltage for write / erase during a write / erase operation.

  When this row decoder is used, when one of the UP and DOWN blocks is selected, the other becomes the adjacent block on the source line side of the selected block. If neither the UP or DOWN block is selected, both become just unselected blocks, and neither UP nor DOWN becomes the adjacent block on the source line side of the selected block.

  Further, except during the erase operation, the nodes N1 and N2 have the same potential and 0 V as VPPRW in the selected block, respectively, and the same as 0 V and VPPRW in the adjacent block on the source line side of the selected block and in other unselected blocks, respectively. It becomes a potential. Therefore, in this row decoder, during operations other than the erase operation, the potentials SGD, CG1 to CG8 are sent to SG1, CG (1) to CG (8) in the selected block, respectively.

  In the adjacent block on the source line side of the selected block and in other non-selected blocks, CG1 to CG8 are 0 V, SG1 is a Vuss (or (Vuss-Vthn) potential; Vthn is an E type, and n-channel MOS transistors Qn2 to Qn15 threshold voltage) potential.

  In addition to the erase operation, both the transistors Qn7 and Qp4, or both the transistors Qn10 and Qp5 are turned on in the selected block and in the adjacent block on the source line side of the selected block, and the transistors Qn8 and Qn9 are turned on. Since either one is in the off state, SG2 is set to the SGS potential. In the other blocks, the four transistors Qn7, Qp4, Qn10, and Qp5 are in the off state, both Qn8 and Qn9 are in the on state, and SG2 is at the Vuss (or (Vuss−Vthn)) potential.

  In the erase operation, the nodes N1 and N2 have the same potential as 0V and VPPRW in the selected block, respectively, and the same potential as VPPRW and 0V in the adjacent block on the source line side of the selected block and in other non-selected blocks, respectively. Therefore, during the erase operation, CG1 to CG8 are set to 0V and SG1 is set to the Vuss (or (Vuss−Vthn) potential) potential in the selected block. In the adjacent block on the source line side of the selected block and other unselected blocks, the potentials SGD, CG1 to CG8 are sent to SG1, CG (1) to CG (8), respectively.

  In the erase operation, when only one of the blocks sandwiching the source line is selected, both of the transistors Qn7 and Qp4 or the transistors Qn10 and Qp5 in the selected block and in the adjacent block on the source line side of the selected block. Since both transistors are turned on and one of the transistors Qn8 and Qn9 is off, SG2 is set to the SGS potential. In the other non-selected blocks, the four transistors Qn8, Qp4, Qn10, and Qp5 are all in the on state, and the two transistors Qn8 and Qn9 are in the off state, so SG2 is set to the SGS potential.

  Even during the erasing operation, even when a plurality of blocks such as chip erasing are selected at the same time, and only in the row decoder corresponding to both selected blocks when both the blocks sandwiching the source line are selected, the transistor Since all of Qn7, Qp4, Qn10, and Qp5 are turned off and the transistors Qn8 and Qn9 are both turned on, SG2 in both the selected blocks has a Vuss (or (Vuss-Vthn)) potential. The row decoder of FIG. 9 which is an example of the configuration of the present invention is characterized by the configuration of the portion (☆) compared to the conventional configuration of the row decoder, and this configuration realizes the operation timing of FIG.

  FIG. 10 shows the operation timing at the time of the read operation of the row decoder related signals for realizing the read operation shown in FIG. However, the adjacent block in FIG. 10 indicates the source line side adjacent block of the selected block, and the non-selected block in FIG. 10 indicates the selected block and the source line side adjacent block of the selected block among all the blocks. It shows the removed block.

  FIG. 11 shows operation timings of the nodes in the memory cell array and the nodes in the row decoder in the data erasing operation. However, the adjacent block in FIG. 11 indicates the source line side adjacent block of the selected block, and the non-selected block in FIG. 11 indicates the selected block and the source line side adjacent block of the selected block among all the blocks. It shows the removed block. Further, the operation timing of the SG2 node in FIG. 11 is the case where only one of the blocks sandwiching the source line is selected in the erase operation.

  FIG. 12 shows the operation timing of the SG2 node in both selected blocks when a plurality of blocks such as chip erasure are simultaneously selected during the erase operation and both of the blocks sandwiching the source line are selected. Shown in

  Next, the effect of the present invention will be described.

  FIG. 15 shows a conventional NAND cell block arrangement and selection / control gate arrangement. As can be seen from FIG. 15, conventionally, all SG2 nodes in all blocks are connected and set to the same potential. FIG. 16 shows a circuit configuration of the row decoder 5 in the conventional system. In FIG. 16, the SGS voltage input from the outside to the row decoder is directly input to the SG2 node without being decoded, and since the SGS voltage is the same potential in all blocks, the SG2 node has the same potential in all blocks. . The reason why the SG2 node potential has been set in this way will be described next.

  As shown in FIG. 6, since the selection gate on the source line side has a short distance between the selection gates sandwiching the source line in the connection region between the node 16 and the node 14, the source line is sandwiched in the selection gate connection region. However, the node 16 and the node 14 in both blocks are connected, and the node 16 and the node 14 are connected. The SG2 node potential is the same in both blocks across the source line.

  In the row decoder shown in FIG. 16, there is only a decode signal in block units as a decode signal. Therefore, the same circuit as SG1, CG (1) to CG (8) to be decoded in block units should be used. The SG2 node to be decoded cannot be decoded by setting the selected block and the adjacent block on the source line side of the selected block as a set. Therefore, the decoding method using the selected block and the adjacent block on the source line side of the selected block as a set is not used. It was.

  During the write / read operation, the bit line contact side select gate SG1 is in the “L” state in the non-selected block, and in the non-selected block, the bit line and the memory cell are turned off by the bit line contact side select gate. Therefore, no malfunction occurs in the unselected block regardless of the voltage of the source side select gate SG2. That is, since a highly reliable write / read operation can be realized, there is no problem in operation reliability even if all the source side select gate SG2 potentials in the non-selected block are set to the same potential as the SG2 potential in the selected block. It was. Further, during the erase operation, all SG2 nodes in all blocks are charged to about the high voltage for erasure, so that it is not necessary to decode the SG2 node. Therefore, a method is used in which all SG2 nodes in all blocks are connected to have the same potential.

  However, in the conventional method in which all SG2 nodes in all blocks are connected, the capacity of the SG2 node becomes enormous, and therefore the charge / discharge time of the SG2 node is prolonged, and the charge / discharge operation of the SG2 node is performed. There was a problem that the time required for the operation to include became long. FIG. 17 shows the operation timing during the read operation when the conventional method is used.

  8 differs from the operation timing in FIG. 8 in the time required for charging the SG2 node from 0 V to Vcc in FIG. 17 (corresponding to (ki) in FIG. 17), the time required for discharging from the VH potential to 0 V (in FIG. 17). (Corresponding to (c)) is longer than the charge / discharge required time of FIG. 8 (corresponding to (a) and (c) in FIG. 8, respectively), and Vcc to VH potential of each node by the read high voltage generation circuit The time required for charging (corresponding to (c) and (b) in FIGS. 17 and 8 respectively) is longer in FIG. 17 than in FIG. This is because the SG2 node capacity is much larger in the conventional method than in the method of the present invention. This will be described in detail below.

  First, the difference in the time required for charging the SG2 node from 0 V to Vcc and the time required for discharging from the VH potential to 0 V will be described. As described above, in FIG. 8, charging from 0V to Vcc of each node in the selected block non-selected control gate, selected block SG1, selected block SG2, and (selected source line side) adjacent block SG2 is performed. The required time and the required time for discharging from the VH potential to 0 V are both times determined by the resistance and capacitance of each wiring in the memory cell.

  The non-selection control gate in the selected block, SG1 in the selected block, SG2 in the selected block, and SG2 in the adjacent block (on the source line side of the selected block) are all the same as the wiring material of the node 16 in FIG. (However, SG1 and SG2 are the same wiring material as that of the node 16 when the resistance is lower among the wirings), and the wiring capacitance is similar, so that the non-selection control gate in the selected block, the SG1 in the selected block, The required charging time (corresponding to (A) in FIG. 8) is approximately the same in SG2 in the selected block and SG2 in the adjacent block (on the source line side of the selected block).

  In this case, the charge operation of SG2 from 0V to Vcc and the discharge operation from the VH potential to 0V are performed by the SG2 signal → transistors Qn7, Qp4, Qn10, Qp5 → SGS node → SGS potential control circuit in the row decoder. Done. Further, since the SGS potential control circuit for performing the charge / discharge is located away from the row decoder, there is a wiring resistance between the SGS node in the row decoder and the SGS potential control circuit, and the SGS potential control circuit. A resistance also exists in the transistor for performing the charge / discharge operation.

  In the operation in FIG. 8, since the capacity in the memory cell of the SG2 node is as small as about two SG2, the wiring resistance and the charge resistance in SG2 charging operation from 0V to Vcc and discharging operation from VH potential to 0V are as follows. Since the transistor resistance was not a problem, the time required for the charge / discharge operation of the SG2 node was approximately the same as that of the non-selection control gate in the selection block and SG1 in the selection block.

  However, in the method of connecting all SG2 nodes in all blocks as in the operation of FIG. 17, the capacity of SG2 node = (one capacity of SG2) × (the number of SG2, that is, the total number of blocks). Further, since the total number of blocks is usually several hundred to several thousand, the capacity of the SG2 node is a huge value.

  In this case, during the charge / discharge operation of the SG2 node, the wiring resistance of the SGS node and the resistance of the transistor in the SGS potential control circuit become problems, and the time required for the charge / discharge operation of the SG2 node is within the memory cell. This is much longer than the time determined by the resistance and capacitance of the wiring of SG2, and is much longer than the non-selected control gate in the selected block and SG1 in the selected block, and the charge / discharge required time of SG2 when using the present invention Will be much longer.

  Also in FIG. 17, (ki) and (ko) are significantly longer than (f) and (ke), and (ki) and (ko) in FIG. ), It is much longer than (c). As described above, the conventional method has a problem that the time required for charging / discharging SG2 is prolonged, and as a result, the operation speed is lowered. In the conventional method, in order to shorten the charge / discharge time of the SG2 node, the wiring width of the SGS node is increased and the size of the transistor in the SGS potential control circuit is increased to reduce the wiring / transistor resistance. Although there is a method, in order to shorten the SGS charge / discharge required time to the extent of using this method, it is necessary to increase the SGS wiring width and transistor size by several tens of times, and the chip size is greatly increased.

  Next, a comparison between the conventional method and the present invention in the time required for charging the Vcc to VH potential at each node by the high voltage generation circuit for reading will be described. The VH potential is a potential generated / supplied by the reading high voltage generation circuit in the chip, and the current supply capability of the generation circuit is much lower than the current supply capability of the power supply voltage and the ground voltage. For this reason, the time required for charging the VCC to VH potential at each node is governed by the current supply capability of the generating circuit and the load capacity of the high voltage for reading rather than the wiring resistance and transistor resistance of each node.

  When the current supply capability of the generation circuit is the same, the present invention is compared with the conventional method. In the present invention, the read high voltage load capacitance includes seven control gates, three selection gates, and a high voltage node in the row decoder (VPPRW node in FIG. 9 (p-channel transistor in the HV broken line). In addition, the load capacity of the high voltage for reading in the conventional method is seven control gates, hundreds to thousands of selection gates, and the high voltage in the row decoder. 9 (VPPRW node in FIG. 9 (including the N-well capacitance in which the p-channel transistor in the HV broken line is formed) and one of nodes N1 and N2).

  The difference in load capacity is the number of selection gates, and the capacity of the conventional system is larger for hundreds to thousands of selection gates. Since the capacity of several hundred to several thousand select gates is larger than [capacity of seven control gates + high voltage node capacity in the row decoder], the conventional method is more suitable as a load capacity of the high voltage for reading. More than several times larger. Therefore, the time required for charging the Vcc to VH potentials of each node by the high voltage generation circuit for reading is several times longer in the conventional method than in the present invention (FIG. 17 (c) is longer than FIG. 8 (a)). Equivalent to long).

  On the other hand, when the conventional method is used, the current supply capability of the read high voltage generation circuit is increased several times or more in order to shorten the time required for charging from the Vcc to the VH potential when using the present invention. That is, it is necessary to increase the pattern area of the read high voltage generation circuit by several times or more, which causes a significant increase in the chip area. On the other hand, when the present invention is used, the time required for charging from Vcc to VH potential can be shortened, and the reading operation can be speeded up.

  As described above, the present invention has been described mainly using the read operation in the case where the unselected control gate potential in the selected block, etc., is set to a voltage higher than the power supply voltage Vcc during the read operation. The present invention is not limited to the examples. For example, the present invention is also effective in a read operation when the non-selected control gate potential in the selected block is charged only to the power supply voltage Vcc during the read operation. FIGS. 14 and 18 show the read operation timing when the present invention / conventional method is used when a high voltage for reading is not used during such a read operation. In the case of using the present invention, the time required to charge Vcc potential to SG2 and the time required to discharge to 0V can be shortened as compared with the conventional method ((D), (E) in FIG. 14). Is equivalent to being shorter than (S) and (C) in FIG. 17), and it can be seen that the reading operation can be speeded up.

  Also, the circuit configuration of the row decoder 5 shown in FIG. 9 can be variously modified without departing from the gist of the present invention. For example, instead of the portion indicated by (☆) in FIG. The present invention is also effective when (e) is used. When (a), (c), and (d) in FIG. 13 are used in place of the (☆) portion in FIG. 9, in the non-selected block at the time of read / write operation (adjacent to the selected block on the source line side) The SG2 potential (except the block) cannot be set to 0V, and the SG2 potential can only be lowered to Vthp (where Vthp is the threshold voltage of the transistors Qp17, Qp18, Qp19, Qp20) during the write / read operation. In the non-selected block, the bit line contact side select gate SG1 is in the “L” state, and in the non-selected block, the bit line and the memory cell are made non-conductive by the bit line contact side select gate. Regardless of the voltage of the inner source side selection gate SG2, no malfunction occurs, that is, there is no problem in reliability.

  In addition, when (e) in FIG. 13 is used instead of the (☆) portion in FIG. 9, in the non-selected block during the write / read operation (excluding the adjacent block on the source line side of the selected block) Although the SG2 node in the floating state is in a floating state, there is no problem in reliability for the same reason as in the case of using (a), (c), and (d) in FIG.

  When (e) in FIG. 13 is used in place of the (☆) portion in FIG. 9, both selected blocks are used only when both blocks sandwiching the source line are selected during the erase operation. In this case, all the nodes other than the control gate are charged up to the erasing high voltage in both selected blocks in the memory cell array, so that the SG2 node in the floating state is the surrounding node. It is considered that the voltage is charged to close to a high voltage for erasing by capacitive coupling with the capacitor, and it is considered that there is no problem in reliability. However, when (e) in FIG. Detailed examination of the rise is necessary.

  Further, in the case of using (e) in FIG. 13, a leakage current of a level that does not cause a problem except in the floating state, that is, a case where charges are supplied through a transistor (FIGS. 9 and 13A to 13A). (When (d) is used) Even if a negligible leakage current exists in the SG2 node, if the SG2 node is floating, the SG2 node (nodes 1410 and 1610 in FIG. 3) and the p-type well (or p-type substrate) forming the memory cell array (corresponding to the node 11 in FIG. 3) is at the high voltage for erasing, so that the SG2 node and the p-type well (or p-type well) There is a risk that the potential difference of the mold substrate) will increase, leading to destruction and failure.

  However, the case where (e) in FIG. 13 is used is the case where the number of elements in the portion (☆) is minimized, and the pattern area of the row decoder is slightly smaller than in the case where the other is used, so that FIG. As to which of FIGS. 13A to 13E is used, it cannot be said which is the best.

  Further, as an example of the configuration of the row decoder 5, the SG2 nodes in both blocks sandwiching the source line are connected in the row decoder as shown in FIG. 9, but the present invention is limited to the above embodiment. Is not to be done. For example, as in the row decoder shown in FIG. 19, in the row decoder, the SG2 node in both blocks sandwiching the source line is not connected, and the circuit of the portion (☆) in FIG. 9 is also in the row decoder. Then, the present invention is effective even when connected to any of the SG2 nodes in both blocks sandwiching the source line.

  In addition, in the row decoder used in the present invention, the number of transistors is increased by 3 to 4 per block as compared with the row decoder in the conventional method, but the row decoder includes about 50 transistors per block. Therefore, when the circuit configuration of the row decoder to be used is changed from the conventional one to that of the present invention, the increase in the pattern area of the row decoder is about 10% at maximum. However, as an influence on the entire chip area, the increase in the chip area when the reading operation speed is increased using the conventional method to the same extent as the reading operation speed when using the present invention is due to the change of the row decoder. Much larger than the chip area increase. Therefore, it is much more effective to use the present invention to speed up the reading operation.

  As mentioned above, although this invention was demonstrated using the Example, this invention is not limited to the said Example, A various change is possible in the range which does not deviate from the summary. In the above embodiment, when adjacent source line side select gates are connected to each other and set to the same potential, the adjacent source line side select gate is set as a set, and the bit line contact side select gate is decoded for each block. However, instead of the source line side select gate, the adjacent bit line contact side select gates are connected to each other and set to the same potential, and the adjacent bit line contact side select gate is set as a set and decoded. The present invention is also effective when the line-side selection gate is decoded for each block.

  In such an embodiment, a NAND cell block arrangement diagram is shown in FIG. 20, and a configuration example of a row decoder is shown in FIG. The embodiments shown in FIGS. 20 and 21 are particularly effective when the distance between the bit line contact side select gates is shortened and it becomes difficult to separate adjacent select gates on the bit line contact side. Similar to the embodiment described above, high-speed operation can be realized even when two adjacent select gates on the bit line contact side have the same potential.

  FIG. 22 shows a NAND cell block arrangement diagram in another embodiment. Features of the embodiment of FIG. 22 will be described below. As the design rule becomes smaller, both the bit line contact side select gate distance and the source line side select gate distance are reduced. Therefore, the processing for separating adjacent select gate lines in the select gate connection region is performed on the bit line contact side / source line. Both sides become difficult. When the embodiment of FIG. 22 is used, since the adjacent selection gate is at the same potential on both the bit line contact side and the source line side, there is a feature that it is not necessary to separate the selection gate lines, and the processing is easy. High-speed operation can be realized.

  In the embodiment of FIG. 22, for example, the source line side selection gate potential setting circuit portion (Qn7, Qn8, Qn9, Qn10, Qp4, Qp5 portion in FIG. 9) of FIG. 9 and the bit line contact side selection of FIG. This can be easily realized by combining the gate potential setting circuit portions (Qn1, Qn2, Qn15, Qn16, Qp1, and Qp8 portions in FIG. 21). Further, in the NAND cell type, when either the bit line contact side selection gate or the source line side selection gate is not provided, the present invention is also effective when the present invention is applied to the remaining selection gate.

  So far, in the NAND cell type EEPROM, the case where the number of bit line contact side selection gates and source line side selection gates in the single NAND cell is one by one has been described as an example. It is not restricted to an Example. For example, it is also effective when the number of one or both of the bit line contact side selection gate and the source line side selection gate in the single NAND cell is two or more. 23 to 30 show an embodiment in which there are a plurality of both the bit line contact side selection gate and the source line side selection gate.

  23 and 24 show an embodiment in which only the selection gate (one per block) adjacent to the source line is set to the same potential, and FIGS. 25 and 26 show the selection on the source line side between adjacent blocks sandwiching the source line. This is an embodiment in which all k gates corresponding to each other have the same potential. In FIGS. 27, 28, 29, and 30, the selection gate to which the present invention is applied in FIGS. 23, 24, 25, and 26 is changed from the source line side to the bit line contact side. This is an example. However, in FIG. 24, FIG. 26, FIG. 28, and FIG. 30, a circuit in which a part of the row decoder circuit shown in FIG. 9 is omitted is shown, but the block selection signal has the same meaning.

  So far, the embodiment in the case where the present invention is applied to a NAND cell type EEPROM has been shown, but the present invention is also effective in other memory cell units. For example, the present invention can be applied to a DINOR cell type EEPROM and an AND cell type EEPROM.

  FIG. 31 shows an equivalent circuit diagram of a memory cell array in the DINOR cell type EEPROM. For details of the DINOR cell type EEPROM, see “H. Onoda et al., IEDM Tech. Digest, 1992, pp. 599-602”. FIG. 32 shows an equivalent circuit diagram of the memory cell array in the AND cell type EEPROM. For details of the AND cell type EEPROM, see "H. Kume et al, IEDM Tech. Degest, 1992, pp. 991-993".

  An example in which the present invention is applied to a DINOR cell type EEPROM is shown in FIGS. However, DSL1 (UP), DSL2 (UP), DSL1 (DOWN), and DSL2 (DOWN) in FIG. 34 are block selection signals, and N1 (UP), N2 (UP), and N1 (DOWN) in FIG. , N2 (DOWN).

  Examples of the case where the present invention is applied to an AND cell type EEPROM are shown in FIG. 35, FIG. 36, FIG. 37, and FIG. However, signals ASL1 (UP), ASL2 (UP), ASL1 (DOWN), and ASL2 (DOWN) in FIGS. 36 and 38 are block selection signals, and signals N1 (UP) and N2 (UP) in FIG. , N1 (DOWN), N2 (DOWN).

  In the above embodiment, an example in which the number of memory cells between the bit line and the source line is plural is shown. However, the present invention is not limited to the above embodiment, and for example, FIG. This is also effective when the number of memory cells between the bit line and the source line is one as shown in FIG.

  Although the present invention has been described using the embodiments, the present invention can be variously modified without departing from the spirit of the present invention.

1 is a block diagram showing a system configuration of a NAND cell type EEPROM according to an embodiment of the present invention. The top view and equivalent circuit schematic of one NAND cell part of a memory cell array. AA 'and BB' sectional drawing of FIG. 2 is an equivalent circuit diagram of a memory cell array in which NAND cells are arranged in a matrix. FIG. The top view of the some NAND cell arrangement | sequence in a memory cell array. The top view and sectional drawing of the selection gate in a memory cell array. The figure which shows the arrangement | sequence of a NAND cell block, and the arrangement | sequence of a selection / control gate. FIG. 6 is a timing chart of a read operation of the NAND cell type EEPROM. The circuit block diagram of the row decoder concerning one Example of this invention. FIG. 10 is an operation timing chart during a read operation of signals related to the row decoder of FIG. 9. FIG. 5 is an operation timing chart of nodes in a memory cell array and nodes in a row decoder in a data erasing operation. The operation | movement timing diagram of SG2 node in both the selection blocks in case the quantity block which pinched | interposed the source line is selected during erase operation. The figure which shows the modification of the part of (*) in FIG. The data read-out operation | movement timing diagram concerning another Example of this invention. The figure which shows the arrangement | sequence of the NAND cell block and the arrangement | sequence of a selection / control gate in a conventional system. The circuit block diagram of the row decoder in a conventional system. The operation | movement timing diagram at the time of read-out operation | movement at the time of using a conventional system. The data read-out operation | movement timing diagram concerning another prior art example. The figure which shows the example of a change of the circuit structure of the row decoder shown in FIG. The figure which shows the arrangement | sequence of the NAND cell block concerning the further another Example of this invention, and the arrangement | sequence of a selection / control gate. The circuit block diagram of the row decoder concerning another Example of this invention. The figure which shows the arrangement | sequence of the NAND cell block and the arrangement | sequence of the selection / control gate in another Example of this invention. The figure which shows the NAND cell block arrangement | sequence in the case of making the selection gate (one per block) adjacent to a source line into the same electric potential. The figure which shows a row decoder structure in the case of making the selection gate (one per block) adjacent to a source line into the same electric potential. The figure which shows the NAND cell block arrangement | sequence in the case of making it correspond between the adjacent blocks which pinch | interpose all the k source line side selection gates. FIG. 6 is a diagram showing a row decoder configuration in the case where the corresponding ones between adjacent blocks sandwiching all k source line side selection gates have the same potential. The figure which shows the NAND cell block arrangement at the time of changing the selection gate to which this invention is applied from the source line side to the bit line contact side. The figure which shows the row decoder structure when the selection gate to which the present invention is applied is changed from the source line side to the bit line contact side. The figure which shows the NAND cell block arrangement at the time of changing the selection gate to which this invention is applied from the source line side to the bit line contact side. The figure which shows the row decoder structure when the selection gate to which the present invention is applied is changed from the source line side to the bit line contact side. The equivalent circuit diagram of the memory cell array in a DINOR cell type EEPROM. The equivalent circuit diagram of the memory cell array in AND cell type EEPROM. The figure which shows the block arrangement at the time of applying this invention to a DINOR cell type EEPROM. The figure which shows the row decoder structure in FIG. The figure which shows the block arrangement at the time of applying this invention to AND cell type | mold EEPROM. The figure which shows the row decoder structure in FIG. The figure which shows the block arrangement at the time of applying this invention to AND cell type | mold EEPROM. The figure which shows the row decoder structure in FIG. The equivalent circuit diagram of the memory cell array in a parallel connection type EEPROM. The equivalent circuit diagram of the memory cell array in another parallel connection type EEPROM.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Bit line control circuit 3 ... Column decoder 4 ... Address buffer 5 ... Row decoder 6 ... Data input / output buffer 7 ... Substrate potential control circuit 11 ... p-type silicon substrate 12 ... Element isolation oxide film 14 ... Floating gate (Charge storage layer)
DESCRIPTION OF SYMBOLS 16 ... Control gate 17 ... Interlayer insulation film 18 ... Bit line 19 ... N-type diffused layer SG ... Selection gate line CG ... Control gate line

Claims (38)

One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A second select transistor connected to the other end of the memory cell;
A memory cell unit including the memory cell and the first and second selection transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
A block composed of one or more word lines and the first and second selection gate lines;
With
There are a plurality of blocks including first, second, and third blocks in at least one of the memory cell arrays, and the first, second, and third blocks are different from each other. The first selection gate line in one block and the first selection gate line in the second block are connected directly or through another wiring layer, and during the first operation, the first block Alternatively, when the second block is selected, the first selection gate line in the first block and the first selection gate line in the second block both have the first voltage, and the third block A nonvolatile semiconductor memory device, wherein a first selection gate line in a block is in a non-selected state.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the first block and the second block are adjacent blocks.   In the block, the first selection gate line is on one end side, the second selection gate line is on the other end side, and all word lines in the block are between the first and second selection gate lines. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is disposed in a non-volatile semiconductor memory device.   The first block and the second block are arranged so that the first selection gate line in the first block and the first selection gate line in the second block are adjacent to each other. The nonvolatile semiconductor memory device according to claim 1.   The first selection gate line in all the blocks other than the first and second blocks among the plurality of blocks is in a non-selected state during the first operation. Item 5. The nonvolatile semiconductor memory device according to any one of Items 1 to 4.   6. The first selection gate line in the first block and the first selection gate line in the third block have different voltages during the first operation. The nonvolatile semiconductor memory device according to any one of the above.   During the first operation, when only one of the first block and the second block is selected or when both are selected, the first selection gate line in the first block The nonvolatile semiconductor memory device according to claim 1, wherein the voltages are set to be the same.   The row decoder circuit for performing selection control / non-selection control and voltage setting of the word line and the first and second selection gate lines. Nonvolatile semiconductor memory device.   9. The nonvolatile semiconductor memory device according to claim 1, wherein the row decoder circuit has a function of simultaneously selecting the first selection gate line and the second selection gate line in the same block. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A second select transistor connected to the other end of the memory cell;
A memory cell unit including the memory cell and the first and second selection transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
With
During the first operation, among the plurality of first selection gate lines in the memory cell array, two adjacent first selection gate lines become the first voltage, and other first selection gates A nonvolatile semiconductor memory device, wherein a line is in a non-selected state. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A second select transistor connected to the other end of the memory cell;
A memory cell unit including the memory cell and the first and second selection transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
With
During the first operation, among the plurality of first selection gate lines in the memory cell array, two adjacent first selection gate lines become the first voltage, and at least one other first selection gate line. A non-volatile semiconductor memory device, wherein one select gate line has a second voltage different from the first voltage. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A second select transistor connected to the other end of the memory cell;
A memory cell unit including the memory cell and the first and second selection transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
With
During the first operation, two adjacent first selection gate lines among the plurality of first selection gate lines in the memory cell array are set to the first voltage, and all other first selection gate lines are set. The non-volatile semiconductor memory device, wherein the selection gate line has a second voltage different from the first voltage.   The nonvolatile semiconductor memory according to claim 10, wherein the first selection gate line is connected to the adjacent first selection gate line directly or through another wiring layer. apparatus. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A second select transistor connected to the other end of the memory cell;
A memory cell unit including the memory cell and the first and second selection transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
A row decoder circuit for controlling selection / non-selection and voltage setting of the word line of the memory cell, and for selecting / deselecting control and voltage setting of the first and second selection gate lines;
With
The non-volatile semiconductor memory device, wherein the first selection gate line is connected to an adjacent first selection gate line directly or through another wiring layer. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A second select transistor connected to the other end of the memory cell;
A memory cell unit including the memory cell and the first and second selection transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
A row decoder circuit for controlling selection / non-selection and voltage setting of the word line of the memory cell, and for selecting / deselecting control and voltage setting of the first and second selection gate lines;
With
The non-volatile semiconductor memory device, wherein the first selection gate line always has the same set voltage as the adjacent first selection gate line. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A second select transistor connected to the other end of the memory cell;
A memory cell unit including the memory cell and the first and second selection transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
A row decoder circuit for controlling selection / non-selection and voltage setting of the word line of the memory cell, and for selecting / deselecting control and voltage setting of the first and second selection gate lines;
First and second transistors provided in the row decoder circuit and connected in series;
With
The first selection gate line is connected to an adjacent first selection gate line directly or via another wiring layer and to one end of the series-connected first and second transistors. A non-volatile semiconductor memory device.   The nonvolatile semiconductor memory device according to claim 16, wherein the first transistor and the second transistor have the same polarity. A block comprising one or more word lines and the first and second selection gate lines;
17. The first selection gate line in all blocks except for the selected block and a block adjacent to the selected block during the erasing operation is charged through the first and second transistors. Alternatively, the nonvolatile semiconductor memory device according to 17.   The first selection gate line is connected to a third transistor different from the first and second transistors, and the third transistor has the same polarity as the first and second transistors. The nonvolatile semiconductor memory device according to claim 16, wherein the nonvolatile semiconductor memory device is a non-volatile semiconductor memory device. A block comprising one or more word lines and the first and second selection gate lines;
The first selection gate line in the first block and the first selection gate line in the second block are connected, and the selection / non-selection of the first block is connected to the gate of the first transistor. The first signal, which is a control signal, is input, and the second signal, which is a selection / non-selection control signal for the second block, is input to the gate of the second transistor. The nonvolatile semiconductor memory device according to any one of 16 to 19.   A third signal is input to the gate of the third transistor, and the logic level of the third signal is in an inverted state of the logic level of the first signal or the second signal. The nonvolatile semiconductor memory device according to claim 16. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A second select transistor connected to the other end of the memory cell;
A memory cell unit including the memory cell and the first and second selection transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
A row decoder circuit for controlling selection / non-selection and voltage setting of the word line of the memory cell, and for selecting / deselecting control and voltage setting of the first and second selection gate lines;
With
The first select gate line is connected to the adjacent first select gate line directly or via another wiring layer, and the second select gate line is directly connected to the adjacent second select gate line or A nonvolatile semiconductor memory device, wherein the nonvolatile semiconductor memory device is connected via another wiring layer. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A second select transistor connected to the other end of the memory cell;
A memory cell unit including the memory cell and the first and second selection transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
A row decoder circuit for controlling selection / non-selection and voltage setting of the word line of the memory cell, and for selecting / deselecting control and voltage setting of the first and second selection gate lines;
With
The first selection gate line always has the same setting voltage as the adjacent first selection gate line, and the second selection gate line always has the same setting voltage as the adjacent second selection gate line. There is a non-volatile semiconductor memory device. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A second select transistor connected to the other end of the memory cell;
A memory cell unit including the memory cell and the first and second selection transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
A row decoder circuit for controlling selection / non-selection and voltage setting of the word line of the memory cell, and for selecting / deselecting control and voltage setting of the first and second selection gate lines;
With
The first selection gate line always has the same setting voltage as the adjacent first selection gate line, and the second selection gate line is adjacent to the adjacent second selection gate line during the first operation. A non-volatile semiconductor memory device, characterized by being set to a different voltage. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A second select transistor connected to the other end of the memory cell;
A memory cell unit including the memory cell and the first and second selection transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
A row decoder circuit for controlling selection / non-selection and voltage setting of the word line of the memory cell, and for selecting / deselecting control and voltage setting of the first and second selection gate lines;
A block composed of one or more word lines and the first and second selection gate lines;
With
The first selection gate line in the first block is connected to the first selection gate line in the second block directly or through another wiring layer and corresponds to the first block. A nonvolatile semiconductor memory device, wherein one row decoder circuit and a second row decoder circuit corresponding to the second block are arranged on the same side of the cell array. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A second select transistor connected to the other end of the memory cell;
A memory cell unit including the memory cell and the first and second selection transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
A row decoder circuit for controlling selection / non-selection and voltage setting of the word line of the memory cell, and for selecting / deselecting control and voltage setting of the first and second selection gate lines;
A block composed of one or more word lines and the first and second selection gate lines;
With
The first selection gate line in the first block is always set to the same voltage as the first selection gate line in the second block, and the first row decoder circuit corresponding to the first block And a second row decoder circuit corresponding to the second block is disposed on the same side of the cell array. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor;
A second select transistor connected between one end of the memory cell and the first select transistor;
A third select transistor;
A fourth select transistor connected between the other end of the memory cell and a third select transistor;
A memory cell unit including the memory cell and the first, second, third and fourth select transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
A third selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the third selection transistor;
A fourth selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the fourth selection transistor;
A row for controlling selection / non-selection and voltage setting of the word line of the memory cell, and for selecting / deselecting control and voltage setting of the first, second, third and fourth selection gate lines. A decoder circuit;
A block composed of one or more word lines and the first and second selection gate lines;
With
In the block, the order of the first selection gate line, the second selection gate line, one or more word lines, the fourth selection gate line, and the third selection gate line from one end side to the other end side. The nonvolatile semiconductor memory device is characterized in that the first selection gate lines in the first block are always set to the same voltage as the first selection gate lines in the second block. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor;
A second select transistor connected between one end of the memory cell and the first select transistor;
A third select transistor;
A fourth select transistor connected between the other end of the memory cell and a third select transistor;
A memory cell unit including the memory cell and the first, second, third and fourth select transistors;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A second selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the second selection transistor;
A third selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the third selection transistor;
A fourth selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the fourth selection transistor;
A row for controlling selection / non-selection and voltage setting of the word line of the memory cell, and for selecting / deselecting control and voltage setting of the first, second, third and fourth selection gate lines. A decoder circuit;
A block composed of one or more word lines and the first and second selection gate lines;
With
In the block, the order of the first selection gate line, the second selection gate line, one or more word lines, the fourth selection gate line, and the third selection gate line from one end side to the other end side. The first select gate lines in the first block are connected to the first select gate lines in the second block directly or through another wiring layer. Storage device.   29. The nonvolatile semiconductor memory device according to claim 27, wherein the first block is adjacent to the second block.   30. The nonvolatile semiconductor memory device according to claim 27, wherein the first selection gate line and the second selection gate line are always set to the same voltage.   31. The second selection gate line in the first block and the second selection gate line in the second block are always set to the same voltage. Nonvolatile semiconductor memory device. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A memory cell unit including the memory cell and the first select transistor;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
With
During the first operation, among the plurality of first selection gate lines in the memory cell array, two adjacent first selection gate lines become the first voltage, and other first selection gates A nonvolatile semiconductor memory device, wherein a line is in a non-selected state. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A memory cell unit including the memory cell and the first select transistor;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
With
During the first operation, among the plurality of first selection gate lines in the memory cell array, two adjacent first selection gate lines become the first voltage, and at least one other first selection gate line. A non-volatile semiconductor memory device, wherein one select gate line has a second voltage different from the first voltage. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A memory cell unit including the memory cell and the first select transistor;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
With
During the first operation, two adjacent first selection gate lines among the plurality of first selection gate lines in the memory cell array are set to the first voltage, and all other first selection gate lines are set. The non-volatile semiconductor memory device, wherein the selection gate line has a second voltage different from the first voltage. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A memory cell unit including the memory cell and the first select transistor;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A row decoder circuit for controlling selection / non-selection of the word line of the memory cell and voltage setting, control of selection / non-selection of the first selection gate line, and voltage setting;
With
The non-volatile semiconductor memory device, wherein the first selection gate line is connected to an adjacent first selection gate line directly or through another wiring layer. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A memory cell unit including the memory cell and the first select transistor;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A row decoder circuit for controlling selection / non-selection of the word line of the memory cell and voltage setting, control of selection / non-selection of the first selection gate line, and voltage setting;
With
The non-volatile semiconductor memory device, wherein the first selection gate line always has the same set voltage as the adjacent first selection gate line. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A memory cell unit including the memory cell and the first select transistor;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A row decoder circuit for controlling selection / non-selection of the word line of the memory cell and voltage setting, control of selection / non-selection of the first selection gate line, and voltage setting;
A block composed of one or more word lines and the first selection gate line;
With
The first selection gate line in the first block is connected to the first selection gate line in the second block directly or through another wiring layer and corresponds to the first block. A nonvolatile semiconductor memory device, wherein one row decoder circuit and a second row decoder circuit corresponding to the second block are arranged on the same side of the cell array. One or a plurality of non-volatile memory cells connected to each other;
A first select transistor connected to one end of the memory cell;
A memory cell unit including the memory cell and the first select transistor;
A memory cell array in which the memory cell units are arranged in an array;
A word line provided by connecting a plurality of gates of the memory cells;
A first selection gate line provided in a direction parallel to the word line by connecting a plurality of gates of the first selection transistor;
A row decoder circuit for controlling selection / non-selection of the word line of the memory cell and voltage setting, control of selection / non-selection of the first selection gate line, and voltage setting;
A block composed of one or more word lines and the first selection gate line;
With
The first selection gate line in the first block is always set to the same voltage as the first selection gate line in the second block, and the first row decoder circuit corresponding to the first block And a second row decoder circuit corresponding to the second block is disposed on the same side of the cell array.

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