JP2005184265A - Image processor, image processing method, and program for executing that method on computer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor capable of high speed processing while reducing the amount of memory. <P>SOLUTION: An 8-line memory 11 stores image data from a scanner 9 in units of 8-line subblock of a master block. An encoding section 12 reads out the data in units of 8 lines and performs variable length encoding in units of macroblock. A macroblock head address storage section 123 stores the head address on the same horizontal line where macroblocks are arranged. A macroblock code intermediate data storage section 1234 stores the intermediate data of macroblock being subjected to variable length encoding of horizontal line. An I/O code memory area 41 stores variable length code data in units of macroblock. A macroblock code address recognition section 144 recognizes the head address of each stored block. An editing section 13 reads the variable length code data by the head address of each stored block according to the content of edition and edits the data while decoding. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus, an image processing method, and a program for executing the method on a computer, and in particular, image processing for compressing acquired image data and performing rotation processing and image composition processing on the compressed image data. The present invention relates to an apparatus, an image processing method, and a program for executing the method on a computer.

  Conventionally, the image data compression technique is generally used in the field of image processing for the purpose of reducing the amount of memory for holding image data or shortening the transmission time of image data. When printing image data, fixed-length compression is often used when printing image data because it is necessary to perform high-speed processing such as rotating image data on a limited amount of memory. Has been. GBTC (Generalized BTC) is known as a typical fixed length compression method.

  65 to 67 are diagrams showing an algorithm for GBTC fixed length compression.

  In Japanese Patent Laid-Open No. 2004-260260, GBTC having a high image quality such as 4/8 GBTC is arranged at an edge portion having a large LD value according to the LD value of GBTC, and the image quality such as 2/8 GBTC is somewhat applied to a portion having a small LD value. Although there is a problem, a technique of arranging GBTC having a high compression rate and keeping the code length fixed for each line, that is, a technique of fixed length coding is disclosed.

  As another compression method, there is known a Wavelet transform in which image data is divided into a plurality of blocks in the horizontal frequency direction and the vertical frequency direction, and the lower frequency block is made finer. This Wavelet transform has recently been developed as a natural gradation image. And it is excellent for compressing images such as photographs with continuous gradation.

  In Patent Document 2 and Patent Document 3, the quantization is loosened for a block having a high edge component of a variable length code, the quantization is strengthened for a block having a small edge component, and fixed in units of several lines. An encoding method is disclosed that can be stored in the specified code length and that can be rotated.

  As a compression method, a method of transforming image data into frequency components by orthogonal transform such as DCT (DisciteCosineTransform) and quantizing the transform coefficient is known. In particular, as a method of encoding a multi-value image using DCT, A standardized JPEG method is known by ITU-T and ISO. Expression (1-1) is an arithmetic expression for obtaining JPEG DCT, and Expression (1-2) is an arithmetic expression for obtaining IDCT.

  Further, Patent Document 4 has a band buffer when encoding image data in JPEG format, temporarily stores image data transferred serially from the scanner, and is a square macro equal to the number of lines in the band buffer. By issuing an RST (ReStart) marker for each block, a DC component is initialized for each macroblock, and a pointer table for recognizing the position of each macroblock is generated by recognizing the RST marker of the code. A technique is disclosed in which decoding is performed for each macroblock at the time of outputting an image, a rotation process in units of 90 degrees is performed, the image processing is performed, and then transferred to the printer engine 17. In Patent Document 4, encoding is performed in units of macroblocks, code length calculation is managed for each macroblock, and rotation processing is enabled.

  Patent Document 5 is composed of a line memory having a height greater than or equal to the height of the macroblock in the vertical direction when the image data is encoded in units of m * n subblocks and the macroblocks are composed of a plurality of subblocks. A first storage means that does not have a band buffer but has at least one block block line, and temporarily stores image data transferred serially from the scanner, and a plurality of macros sequentially from the first storage means By encoding while switching the encoding process of blocks, encoding is performed in units of macroblocks with a small memory capacity, and also in the decoding process, by switching the codes in units of horizontal macroblocks for each sub-block, To store the decoded image data for decoding the macroblocks in parallel. As storage means, it discloses a method which enables decoding a small memory only memory n lines of the sub-blocks.

JP 2001-218061 A JP 2001-197496 A JP 2001-224027 A JP-A-10-75345 JP 2002-125116 A

  As described above, in a system for printing processing, the GBTC method or the like has been used by using a fixed length compression method. However, this GBTC assigns 8 types of color of 3 bits to 1 block 4 * 4 dots and 1 dot in 4/8 compression, and 2/8 colors of 2 bits to 1 dot in 3/8 compression. In compression, two colors of 1 BIT were assigned. For this reason, the technique disclosed in Patent Document 1 has a problem in that dust such as a notch is generated in the outline of a character or the like in one block where the gradation difference between pixels is particularly severe, thereby degrading the image quality. there were.

  Further, in the techniques described in Patent Documents 2 and 3, since coding can be performed for each block line, the memory to be used is small, but in order to read the code from the reverse direction in the 270 degree rotation process. In addition, since the processing is complicated and the quantized value is different for each block line, there is a problem that the deterioration of the image is conspicuous at the worst.

  Further, in the technique described in Patent Document 4, if the number of pixels in the horizontal direction is 8192, when configured with 16 lines in order to reduce the band memory, 8129/16 = 512 macroblocks per band. Occurs, and address management and overall control are complicated. In the case of having 256 lines, 8129/256 = 32, which is a range that can be barely controlled, but requires a large band buffer. In addition, after the decryption and rotation processes are performed, they are serially sent and sequentially sent to the image processing unit and the printer engine 17. However, since the normal printer engine 17 must transfer data within a certain time, It is necessary to estimate the worst speed when performing complex control and complicated code memory access by the rotation processing of the memory, and there is a problem that high speed memory is necessary for the memory considering the worst memory access. It was.

  In addition, when the rotation process is performed, when the encoded code of one page is rotated, a memory area for storing the code of one page after the rotation is further required, and basically a memory area twice as large as the code is required. I need it. In addition, when code data is written to the HDD device, a buffer memory for HDD transfer is required to reduce the difference between the transfer speed of the HDD device and the processing speed of the scanner device and the printer device.

  Furthermore, in the technique described in Patent Document 4, when various editing processes are performed, in order to read a plurality of images to be synthesized such as an original image and characters, a processing time to be allocated is determined depending on circumstances, and overspec Sometimes it became a system. In addition, since the editing process is performed in synchronization with the printer engine, there is a problem that it is difficult to finish the process of reading the original image data and the character image of the synthesis process within a certain time. . However, it is basically difficult to perform a synthesis process on a variable-length code and is not specified in Patent Document 4.

  Further, it becomes difficult to simultaneously perform an operation of reading another page from the encoding scanner during a decoding process (during printing) often performed in a digital copying machine. In addition, since one band memory is shared by encoding and decoding, there is a problem that encoding cannot be performed during the decoding. Further, since the decoding process must be performed in synchronization with the engine speed, a lot of processes are required during a certain period of time, the hardware is enlarged, and a process with a high frequency is required.

  Further, the technique described in Patent Document 4 has a problem in that a large amount of memory is required because it is necessary to provide a band memory that stores data in units of macroblocks.

  In the technique described in Patent Document 5, data of one block line in units of sub-blocks is used and encoding processing is switched in units of macroblocks in the horizontal direction. For example, a fixed value such as GBTC described above is used. If the coding method is long, it is possible to switch every block line by holding the head address of the coded code in units of a plurality of macroblocks when switching the coding process. In this case, since a variable-length code is collected into a fixed-length word (for example, 32 BIT, 64 BIT, etc.) and stored as a code in a memory, a method that only manages the head address of the code as in this technique is used. , Could not be realized. Also, the variable length code switching process was not specified in detail.

  The present invention has been made in view of the above, and is capable of performing editing processing on variable length input image data, suppressing increase in memory, and processing high-quality images at high speed. An object is to provide an image processing apparatus, an image processing method, and a program for executing the method on a computer.

  In order to solve the above-described problems and achieve the object, the invention according to claim 1 is directed to subjecting input image data to variable-length encoding, editing, decoding, image processing, and image processing. An image processing apparatus for outputting data, an edit designating unit for accepting designation of editing processing contents for the input image data, and the input image data as a multi-value sub-block constituting a macro block Multi-value block line data storage means for storing as unit line data, and macro-block variable-length coding for reading out the multi-value block line data from the multi-value block line data storage means and variable-length coding for each macro block And the macroblocks arranged in the image at the time of variable length coding by the macroblock variable length coding means. Macroblock start address storage means for storing the start address of the macroblock on the horizontal line of the horizontal line, and variable length coding on the same horizontal line at the time of variable length coding by the macroblock variable length coding means Macroblock code intermediate data storage means for storing intermediate data for variable length coding processing of macroblocks, and macroblock for sequentially storing variable length code data generated by the macroblock variable length coding means in units of macroblocks A macroblock code address for recognizing the head address of each block stored in the macroblock head address storage means corresponding to the variable length code data in units of macroblocks stored in the macroblock code storage means; By the recognition means and the editing designation means Editing means for reading, decoding, and editing variable-length code data stored in the macroblock code storage means in accordance with the start address of each block recognized by the macroblock code address recognition means in accordance with the set editing processing content; , Provided.

  According to the first aspect of the present invention, the editing designation means accepts designation of editing processing content for the input image data. The multi-value block line data storage means stores input image data as line data in units of multi-value sub-blocks constituting the macro block. The macroblock variable length encoding means reads the multilevel block line data from the multilevel block line data storage means and performs variable length encoding on a macroblock basis. The macroblock head address storage means stores the head address of the macroblock on the same horizontal line in which the macroblocks are arranged in the image at the time of variable length coding by the macroblock variable length coding means. The macroblock code intermediate data storage means stores intermediate data of macroblock variable length encoding processing for variable length encoding on the same horizontal line during variable length encoding by the macroblock variable length encoding means. The macroblock code storage means sequentially stores the variable length code data generated by the macroblock variable length encoding means in units of macroblocks. The macroblock code address recognition means recognizes the head address of each block stored in the macroblock head address storage means corresponding to the variable length code data in units of macroblocks stored in the macroblock code storage means. The editing means reads and decodes the variable length code data stored in the macroblock code storage means according to the start address of each block recognized by the macroblock code address recognition means in accordance with the editing processing contents designated by the editing designation means. Edit.

  That is, when the macroblock variable length encoding means encodes, the macroblock head address storage means for storing the head address of the code for each macroblock on the same horizontal line, and the macroblock head address storage means for each macroblock on the same horizontal line. Macroblock code intermediate data storage means for storing the intermediate code data, stored in the multi-value block line data storage means for the input image data, and then encoded in parallel for each macroblock on the same horizontal line, By storing in the macroblock code storage means, a band memory having a height in the vertical direction of the macroblock is not required, and the code data of the macroblock unit is decoded by the editing means in units of macroblocks and edited. Image processing without the need for a band memory having a height in the vertical direction of the macroblock. It can be subjected. Therefore, since the multi-value block line data having the number of pixels based on the height of the sub-block smaller than that is stored without using the memory based on the number of pixels in the sub-scanning direction of the macro block, the memory can be reduced. Further, when the encoding means generates the code data, the macroblock head address storage means stores the head address of the code intermediate data of the macroblock, and the macroblock code intermediate data storage means is provided for each macroblock. Thus, the end of one line can be detected, so that it can be transmitted to the editing means and decoded for each macroblock for editing processing. With this configuration, it is possible to provide an image processing apparatus capable of performing variable-length coding on input image data to perform editing processing, suppressing an increase in memory, and processing high-quality images at high speed. With this configuration, it is possible to provide an image processing apparatus capable of performing variable-length encoding on input data to perform editing processing, suppressing an increase in memory, and processing high-quality images at high speed.

  According to a second aspect of the present invention, there is provided an image processing apparatus for inputting image data that has been subjected to variable length coding in units of macroblocks composed of sub-blocks, editing, decoding, performing image processing, and outputting the processed image data. An edit designating unit that accepts designation of edit processing contents for the input image data, a macroblock code storage unit that stores the variable-length code data in units of macroblocks, and an edit designated by the edit designating unit Editing means for reading, decoding, editing, and variable-length-coding the variable-length code data stored in the macroblock code storage means according to the processing content, and transmitting the variable-length code data to the macroblock code storage means; and the macro Macro for recognizing the address of each macro block corresponding to variable length code data stored in block code storage means Lock code address recognition means and the macroblock code address storage means receive the start address of the macroblock, read the macroblock variable length code data edited by the editing means from the macroblock code storage means, and sequentially decode And a macroblock head address storage means for storing the head address of the macroblock on the same horizontal line stored in the macroblock code storage means upon decoding by the macroblock decoding means And a macroblock decoding intermediate data storage means for storing data in the middle of decoding the macroblock processed on the same horizontal line upon decoding by the macroblock decoding means, and the macroblock decoding intermediate data storage means Receives at least the stored image data in units of sub-blocks and performs image processing, and sequentially transfers image data generated by the image processing means to the printer engine in the main scanning direction of the image. And an image output means.

  According to the second aspect of the present invention, the edit designating unit accepts the designation of the editing process content for the input image data. The macroblock code storage means stores variable length code data in units of macroblocks. The editing means reads the variable-length code data stored in the macroblock code storage means according to the editing processing content designated by the editing designation means, decodes and edits it, and performs variable-length coding again to store the macroblock code. Send to means. The macroblock code address recognition means recognizes the address of each macroblock corresponding to the variable length code data stored in the macroblock code storage means. The macroblock decoding means receives the start address of the macroblock from the macroblock code address storage means, reads the variable length code data of the macroblock edited by the editing means from the macroblock code storage means, and sequentially decodes it. The macroblock head address storage means stores the head address of the macroblock of the same horizontal line stored in the macroblock code storage means at the time of decoding by the macroblock decoding means. The macroblock decoding intermediate data storage unit stores data in the middle of decoding the macroblock to be processed on the same horizontal line when the macroblock decoding unit performs decoding. The image processing means receives at least sub-block unit image data stored in the macroblock decoded intermediate data storage means, and performs image processing. The image output means sequentially transfers the image data after the image processing generated by the image processing means to the printer engine in the main scanning direction of the image.

  With this configuration, when the macroblock decoding means decodes, the macroblock head address storage means for storing the head address of the code for each macroblock on the same horizontal line, and the macroblock head address storage means for each macroblock on the same horizontal line. Macroblock decoding intermediate data storage means for storing intermediate code data is provided, and the macroblock unit code on the same horizontal line is decoded in parallel, so that at least the subblock unit is transferred to the image processing unit. Image processing is possible without the need for band memory in the vertical direction of the block, and the input data is variable-length encoded and edited, and the increase in memory is suppressed and high-quality images are processed at high speed. It is possible to provide an image processing apparatus that can

  According to a third aspect of the present invention, in the image processing apparatus according to the first aspect, the macroblock code address recognizing means calculates a total code length generated in a macroblock consisting of a plurality of sub-blocks. It has a calculation means, It is characterized by the above-mentioned.

  According to the third aspect of the present invention, in the image processing apparatus according to the first aspect, the macroblock code address recognizing means calculates the total code length generated in a macroblock composed of a plurality of sub-blocks. It has a calculation means. With this configuration, the code length of the macroblock can be calculated by a simple method, the input data can be subjected to variable length coding and editing processing, the increase in memory can be suppressed, and high-quality images can be processed at high speed. A possible image processing apparatus can be provided.

  According to a fourth aspect of the present invention, in the image processing apparatus according to the third aspect, the macroblock code address recognizing means uses the macroblock code storage means based on the code length generated by the code length total calculating means. It is characterized by having an address calculation means for calculating the address.

  According to the invention of claim 4, in the image processing apparatus according to claim 3, the macroblock code address recognizing means uses the code length generated by the code length total calculating means to determine the address of the macroblock code storage means. Address calculating means for calculating. With this configuration, the address of the macroblock code data can be calculated by a simple method, so the input data can be variable-length encoded and edited, and the increase in memory can be suppressed, and high-quality images can be processed at high speed. An image processing apparatus can be provided.

  According to a fifth aspect of the present invention, in the image processing apparatus according to the first or second aspect, the editing unit includes a macroblock expansion storage unit that decodes and expands the image data of the macroblock. It is characterized by that.

  According to the fifth aspect of the present invention, in the image processing apparatus according to the first or second aspect, the editing means has macroblock expansion storage means for decoding and expanding macroblock image data. With this configuration, image data received with a code length can be expanded and edited by a simple method, so that input data can be variable-length encoded and edited, and an increase in memory is suppressed, resulting in high image quality. It is possible to provide an image processing apparatus capable of processing a high-speed image.

  According to a sixth aspect of the present invention, in the image processing apparatus according to the fifth aspect, the editing means includes image composition processing means for performing composition processing on an image stored in the macroblock development storage means. It is characterized by being.

  According to the sixth aspect of the present invention, in the image processing apparatus according to the fifth aspect, the editing means includes image composition processing means for performing composition processing on the image stored in the macroblock development storage means. With this configuration, image data received with a code length can be developed and combined by a simple method, so that input data can be subjected to variable-length encoding and editing processing, while suppressing an increase in memory and high image quality. It is possible to provide an image processing apparatus capable of processing a high-speed image.

  According to a seventh aspect of the present invention, in the image processing apparatus according to the fifth or sixth aspect, the editing unit stores the macroblock expansion storage unit in accordance with the editing content designated by the editing designation unit. The image processing apparatus includes a rotation processing unit that rotates the image data in units of 90 degrees for each sub-block.

  According to the seventh aspect of the present invention, in the image processing apparatus according to the fifth or sixth aspect, the editing means is stored in the macroblock development storage means according to the editing content designated by the editing designation means. Rotation processing means for rotating the image data in units of 90 degrees for each sub-block. With this configuration, image data received with a code length can be developed and rotated by a simple method, so that input data can be subjected to variable length encoding and editing processing, while suppressing an increase in memory and high image quality. It is possible to provide an image processing apparatus capable of processing a high-speed image.

  According to an eighth aspect of the present invention, in the image processing apparatus according to the first aspect, the macroblock variable length encoding means detects the end of one block line in the horizontal direction of the image data in units of macroblocks. An image block line end detection means is provided.

  According to the eighth aspect of the present invention, in the image processing apparatus according to the first aspect, the macroblock variable length encoding means detects an end of one block line in the horizontal direction of the image data in units of macroblocks. It has block line end detection means. This configuration simplifies the detection of the end of the horizontal line for each macroblock, so that the input data can be variable-length encoded and edited, and the increase in memory is suppressed and high-quality images are processed at high speed. It is possible to provide an image processing apparatus that can

  The invention according to claim 9 is the image processing apparatus according to claim 8, wherein the image block line end detection means is a restart marker at the end of one block line in the horizontal direction of the image data in units of macroblocks. It has a restart marker insertion means for inserting.

  According to the ninth aspect of the present invention, in the image processing apparatus according to the eighth aspect, the image block line end detection means sets the restart marker at the end of one block line in the horizontal direction of the image data in units of macroblocks. There is a restart marker insertion means for insertion. This configuration simplifies the detection of the end of the horizontal line for each macroblock by the restart marker at the end of the horizontal line, so that the input data can be variable-length encoded and subjected to editing processing, while suppressing an increase in memory. It is possible to provide an image processing apparatus capable of high-speed processing of high-quality images.

  According to a tenth aspect of the present invention, in the image processing apparatus according to the second aspect, the macroblock decoding means includes one block line in the horizontal direction of the variable length code data stored by the macroblock code storage means. Code block line end detecting means for detecting the end of the code block line, and using the end detected by the code block line end detecting means, the variable length code data stored in the macro block code storing means is read. It is what decodes.

  According to the tenth aspect of the present invention, in the image processing apparatus according to the second aspect, the macroblock decoding means is configured to generate one block line in the horizontal direction of the variable length code data stored by the macroblock code storage means. Code block line end detection means for detecting the end is provided, and variable length code data stored in the macroblock code storage means is read and decoded using the end detected by the code block line end detection means. With this configuration, the detection of the end of the horizontal line for each macroblock is simplified and decoded, so the input data is variable-length encoded and edited, and the increase in memory is suppressed, resulting in high-quality images. An image processing apparatus capable of high-speed processing can be provided.

  According to an eleventh aspect of the present invention, in the image processing apparatus according to the tenth aspect, the code block line end detection means reads one code of one block line in the horizontal direction for reading the code stored by the macroblock code storage means. It has a restart marker detection means for detecting a restart marker at the end.

  According to the eleventh aspect of the present invention, in the image processing apparatus according to the tenth aspect, the code block line end detection means reads the code stored in the macroblock code storage means in the horizontal direction and ends one block line in the horizontal direction. Restart marker detecting means for detecting the restart marker. With this configuration, since the detection of the end of the horizontal line for each macroblock is simplified and decoded by the restart marker at the end of the horizontal line, the input data is variable-length encoded and subjected to editing processing, and the memory It is possible to provide an image processing apparatus that can suppress an increase in image quality and can process high-quality images at high speed.

  According to a twelfth aspect of the present invention, there is provided an image processing apparatus for performing variable length coding, editing and decoding input image data, performing image processing, and outputting the image data after image processing. Edit designation means for accepting designation of processing contents, multi-value block line data storage means for storing one line of data in units of multi-value sub blocks, and codes in units of macro blocks from the multi-value block line data storage means First macroblock variable length encoding means for generating a plurality of macroblock unit variable length code data sequentially generated by the first macroblock variable length encoding means Each macroblock is stored with respect to the variable length code data stored in the storage means and the first macroblock code storage means. First macroblock code address recognizing means for recognizing a dress, and variable length code data stored in the first macroblock code storage means in accordance with the editing processing content designated by the edit designating means, An editing unit that reads, decodes and edits using the address recognized by the first macroblock code address recognition unit, and a second variable-length code for the image data edited by the editing unit in units of macroblocks Macroblock variable length coding means, second macroblock code storage means for sequentially storing variable length code data generated by the second macroblock variable length coding means in units of macroblocks, and the second Each macroblock was stored for variable length code data stored in the macroblock code storage means A second macroblock code address recognizing unit for recognizing a dress; a head address of the macroblock is received from the second macroblock code address storing unit; and a variable length of the macroblock is received from the second macroblock code storing unit. Macroblock decoding means for reading code data and sequentially decoding; output multi-value block line data storage means for storing multi-value block line data decoded by the macroblock decoding means; and for output The image processing unit that receives the image data in units of sub-blocks stored in the multi-value block line data storage unit, performs image processing, and the image data after the image processing generated by the image processing unit is subjected to image main scanning. Image output means for sequentially transferring to the printer engine in the direction It is characterized by.

  According to the twelfth aspect of the present invention, the editing designation means accepts designation of editing processing content. The multi-value block line data storage means stores one line of data in units of multi-value sub-blocks. The first macroblock variable length encoding unit generates a plurality of macroblock unit codes from the multilevel block line data storage unit. The first macroblock code storage means sequentially stores variable length code data in units of a plurality of macroblocks generated by the first macroblock variable length encoding means. The first macroblock code address recognition means recognizes the address at which each macroblock is stored for the variable length code data stored in the first macroblock code storage means. The editing means selects an address at which the first macroblock code address recognizing means recognizes the variable length code data stored in the first macroblock code storage means in accordance with the editing processing content designated by the editing designation means. Use to read, decrypt and edit. The second macroblock variable length coding means performs variable length coding on the image data edited by the editing means in units of macroblocks. The second macroblock code storage unit sequentially stores the variable length code data generated by the second macroblock variable length encoding unit in units of macroblocks. The second macroblock code address recognizing means recognizes the address where each macroblock is stored with respect to the variable length code data stored in the second macroblock code storage means. The macroblock decoding means receives the start address of the macroblock from the second macroblock code address storage means, reads the variable length code data of the macroblock from the second macroblock code storage means, and sequentially decodes them. The output multi-value block line data storage means stores the multi-value block line data decoded by the macroblock decoding means. The image processing means receives the image data in units of sub-blocks stored in the output multi-value block line data storage means, and performs image processing. The image output means sequentially transfers the image data after the image processing generated by the image processing means to the printer engine in the main scanning direction of the image.

  With this configuration, the multi-value macroblock unit code is temporarily stored in the first macroblock code storage means, and then the editing means performs synthesis with a stamp image or the like or rotation processing in macroblock units. By storing the macroblock code storage means in page 2 in units of pages, it is possible to suppress an increase in memory due to editing processing such as rotation. It is possible to provide an image processing apparatus that can suppress and process high-quality images at high speed.

  According to a thirteenth aspect of the present invention, there is provided an image processing method in which input image data is subjected to variable length encoding, editing and decoding, image processing is performed, and image data after image processing is output. An edit designation step for accepting designation of edit processing contents for the image data to be processed, and multi-value block line data for storing the input image data as line data in units of multi-value sub-blocks constituting a macro block A macroblock variable length encoding step for reading out the multilevel block line data stored in the multilevel block line data storage step and performing variable length encoding in units of the macroblock; and the macroblock variable length code. In the variable length encoding in the conversion step, the macroblocks are arranged on the same horizontal line in the image. A macroblock head address storing step for storing a head address of a black block; a macroblock code storing step for sequentially storing the variable length code data generated in the macroblock variable length coding step in units of the macroblock; and the editing The variable length code data stored in the macroblock code storage step is read in accordance with the editing processing content specified in the specification step, the editing step for decoding and editing, and the macroblock head code address storage step stored in the macroblock head code address storage step A macroblock decoding step of reading a macroblock start address, reading code data of the macroblock stored in the macroblock code storage step, and sequentially decoding the data; and data decoded in the macroblock decoding step The An output multi-value block line data storage step, an image processing step for receiving image data in units of sub-blocks stored in the output multi-value block line data storage step, and performing image processing; and And an image output step of sequentially transferring the generated image data after image processing to the printer engine in the main scanning direction of the image.

  According to the thirteenth aspect of the present invention, the editing designation step accepts designation of editing processing content for the input image data. In the multi-value block line data storage step, input image data is stored as line data in units of multi-value sub-blocks constituting the macro block. The macroblock variable length encoding step reads the multilevel block line data stored in the multilevel block line data storage step and performs variable length encoding on a macroblock basis. The macroblock head address storage step stores the head address of the macroblock on the same horizontal line in which the macroblocks are arranged in the image at the time of variable length coding in the macroblock variable length coding step. The macroblock code storage step sequentially stores the variable length code data generated in the macroblock variable length encoding step in units of macroblocks. In the editing step, the variable length code data stored in the macroblock code storage step is read, decoded and edited in accordance with the editing processing content specified in the editing specification step. The macroblock decoding step reads the macroblock head address stored in the macroblock head code address storage step, reads the macroblock code data stored in the macroblock code storage step, and sequentially decodes the data. The output multi-value block line data storage step stores the data decoded in the macroblock decoding step. The image processing step receives the image data in units of sub-blocks stored in the output multi-value block line data storage step, and performs image processing. In the image output process, the image data after the image processing generated in the image processing process is sequentially transferred to the printer engine in the main scanning direction of the image. With this configuration, it is possible to provide an image processing method capable of performing variable-length encoding on input data to perform editing processing, suppressing increase in memory, and processing high-quality images at high speed.

  The invention according to claim 14 is a program, and the image processing method according to claim 13 is executed by a computer.

  According to the invention of claim 14, the image processing method of claim 13 can be executed by a computer.

  The image processing apparatus according to the present invention (Claim 1) produces an effect that input image data is subjected to variable length coding to perform editing processing, an increase in memory can be suppressed, and high-quality images can be processed at high speed. .

  The image processing apparatus according to the present invention (claim 2) is a macroblock head address storage means for storing a code head address for each macroblock on the same horizontal line when the macroblock decoding means decodes. And macroblock decoding intermediate data storage means for storing intermediate code data for each macroblock on the same horizontal line, and by decoding in parallel the macroblock unit code on the same horizontal line, Since it is transferred to the image processing unit in units of blocks, image processing is possible without the need for a band memory with a vertical height of macroblocks, and input data is subjected to variable-length coding and editing processing, and memory is increased. This is advantageous in that high-quality images can be processed at high speed.

  In addition, the image processing apparatus according to the present invention (Claim 3) can calculate the code length of the macroblock by a simple method, performs variable length coding on the input data, performs editing processing, and increases the memory. This is advantageous in that high-quality images can be processed at high speed.

  In addition, since the image processing apparatus according to the present invention (Claim 4) can calculate the address of the macroblock code data by a simple method, the input data is subjected to variable length coding to perform editing processing, and the increase in memory is suppressed. The high-quality image can be processed at high speed.

  Further, the image processing apparatus according to the present invention (claim 5) can edit the image data received with the code length by expanding the image data by a simple method. In addition, it is possible to suppress an increase in memory and to process a high-quality image at high speed.

  Further, the image processing apparatus according to the present invention (claim 6) can develop the image data received with the code length by a simple method and perform the synthesis process. In addition, it is possible to suppress an increase in memory and to process a high-quality image at high speed.

  The image processing apparatus according to the present invention (Claim 7) can perform rotation processing by expanding image data received with a code length by a simple method, so that input data is variable-length encoded and edited. In addition, it is possible to suppress an increase in memory and to process a high-quality image at high speed.

  The image processing apparatus according to the present invention (claim 8) simplifies the detection of the end of the horizontal line for each macroblock, so that the input data is subjected to variable length coding to perform editing processing, and the memory is increased. This is advantageous in that high-quality images can be processed at high speed.

  In the image processing apparatus according to the present invention (claim 9), since the detection of the end of the horizontal line for each macroblock is simplified by the restart marker at the end of the horizontal line, the input data is variable-length encoded. As a result, it is possible to perform editing processing, suppress an increase in memory, and perform high-speed processing of high-quality images.

  In the image processing apparatus according to the present invention (claim 10), since the detection of the end of the horizontal line for each macroblock is simplified and decoded, the input data is variable-length encoded and subjected to editing processing. Thus, it is possible to suppress an increase in memory and to process a high-quality image at high speed.

  In the image processing apparatus according to the present invention (claim 11), the detection of the end of the horizontal line for each macroblock is simplified and decoded by the restart marker at the end of the horizontal line. It is possible to perform variable length coding and edit processing, suppress an increase in memory, and perform high-speed processing of high-quality images.

  The image processing apparatus according to the present invention (Claim 12) temporarily stores a multi-level macroblock unit code in the first macroblock code storage means, and then synthesizes it with a stamp image or the like by the editing means. Alternatively, by performing rotation processing in units of macroblocks and storing them in the second macroblock code storage means in units of pages, it is possible to suppress an increase in memory due to editing processing such as rotation. The editing process is performed and the increase in the memory is suppressed, and the high-quality image can be processed at high speed.

  In addition, the image processing method according to the present invention (claim 13) is advantageous in that input data is subjected to variable length coding to perform editing processing, an increase in memory is suppressed, and high-quality images can be processed at high speed. Play.

  In addition, the program according to the present invention (Claim 14) exhibits the effect that the image processing method according to Claim 13 can be executed by a computer.

  Exemplary embodiments of an image processing apparatus, an image processing method, and a program for executing the method by a computer will be described below in detail with reference to the accompanying drawings.

(1. Embodiment 1)
(1.1. Schematic Configuration of Image Processing Device According to Embodiment 1)
FIG. 1 is a functional block diagram of an image processing unit according to Embodiment 1 of the present invention. The image processing apparatus according to the first embodiment includes a scanner 9, an operation panel 30, an 8-line memory 11, an encoding unit 12, an input / output code memory area 41, an editing unit 13, a page decoding unit 14, an image processing unit 15, And a printer engine 17. The encoding unit 12 includes a macroblock head address storage unit 123 and a macroblock decoding intermediate data storage unit 1234. The editing unit 13 includes a macroblock code address recognition unit 13032. The page decoding unit 14 includes a macroblock head address storage unit 145, a macroblock code address recognition unit 144, and a macroblock decoding shift value storage unit 143172.

  Here, the input / output code memory area 41 constitutes a macroblock code storage means in the present invention. The operation panel 30 constitutes edit designation means. The 8-line memory 11 constitutes multi-value block line data storage means. The encoding unit 12 constitutes a macroblock variable length encoding unit. The input / output code memory area 41 constitutes a macroblock code storage means. The editing unit 13 constitutes editing means. The page decoding unit 14 constitutes a macroblock decoding unit. The printer engine 17 constitutes image processing means.

  The macroblock head address storage unit 123 constitutes a macroblock head address storage unit. The macroblock decoded intermediate data storage unit 1234 constitutes macroblock code intermediate data storage means (claim 1). The macroblock code address recognition unit 13032 constitutes a macroblock code address recognition unit.

  The macroblock head address storage unit 145 and the macroblock code address recognition unit 144 constitute macroblock code address recognition means (claim 2). The macroblock head address storage unit 145 constitutes a macroblock head address storage unit. The macroblock decoding shift value storage unit 143172 constitutes a macroblock decoding intermediate data storage unit. The parts shown in FIG. 1 will be described in detail below.

  FIG. 2 is a hardware configuration diagram of the image processing apparatus according to the first embodiment. The image processing apparatus includes a CPU 1, a CPU I / F 2, a memory controller 3, a memory 4, a local bus I / F 5, a ROM 6, a panel controller 7, an operation panel 8, a scanner 9, a smoothing filter processing unit 10, an 8-line memory 11, and an encoding. A section 12, an editing section 13, a page decoding section 14, an image processing section 15, an engine controller 16, a printer engine 17, an HDD control section 18, and an HDD (hard disk) section 19.

  The CPU 1 controls the entire copy device. The CPU I / F 2 is connected to the memory controller 3 and processes an interface between the CPU 1 and the memory controller 3.

  The memory controller 3 controls the memory 4. The CPU 1, the local bus I / F 5, the editing processing unit 13, the page decoding unit 14, the image processing unit 15, the encoding unit 12, and the bus I / F 11, Control the transfer of

  The memory 4 stores an image from the scanner 9, a program of the CPU 1, and various data. The local bus I / F 5 processes an interface between the ROM (Read Only Memory) 6, the panel controller 7, the CPU 1, the memory 4, and the like. The ROM 6 stores font information such as characters and the program of the CPU 1.

  The panel controller 7 controls the operation panel 8. The operation panel 8 receives an operation from the user. The scanner 9 reads an image with a CCD.

  The smoothing filter processing unit 10 performs image processing such as shading correction and MTFγ correction on the image data read from the scanner 9.

  The 8-line memory 11 stores the image data of the size in the sub-operation direction of one sub-block necessary for the encoding unit 12 to encode the data subjected to the image processing by the smoothing filter processing unit 10. Store.

  In addition, a toggle memory configuration is used for pipeline processing, and image data input from the scanner 9 and output to the encoding unit 12 can be executed simultaneously.

  The encoding unit 12 encodes the data subjected to the image processing in the 8-line memory 11 and transfers the data to the memory 4.

  The editing unit 13 synthesizes another character image or the like on the code data obtained by encoding the scanner image stored in the memory 4, performs a rotation process in units of 90 degrees, and transfers the data to the memory 4 again.

  The page decoding unit 14 receives the image data encoded by the editing unit 13, decodes it, and transfers it to the image processing unit 15 in subblock units.

  The image processing unit 15 subjects the image data decoded by the page decoding unit to color conversion processing and gradation processing in units of sub-blocks, and transfers the binary data to the engine controller 16.

  The engine controller 16 receives the data generated by the image processing unit 15 and controls the printer engine 17.

  The HDD control unit 18 controls the HDD 19 to transfer data in the memory 4 to the HDD 19 and transfer data in the HDD 19 to the memory 4. An HDD (hard disk) unit 19 stores image data of the scanner 9 and the like and encoded image data.

  FIG. 3 is a flowchart for explaining the overall flow of image formation by the image processing apparatus. The image processing apparatus first reads multi-value RGB image data from the scanner 9 (step S101). The smoothing filter processing unit 10 performs image processing such as shading correction and MTFγ correction on the image data read from the scanner 9 (step S102).

  The encoding unit 12 encodes the RGB image data that has been subjected to image processing by the smoothing filter processing unit 10 (step S103). The encoded RGB code data is stored in the memory 4 (step S104).

  The decoding unit 14 decodes the RGB code data stored in the memory 4 (step S105). The image processing unit 15 performs color correction processing and converts RGB image data into CMYK image data (step S106). The image processing unit 15 performs gradation processing on the converted image data, and converts the CMYK image data into binary CMYK data (step S108). The engine controller 16 prints binary CMYK data.

(1.2. Memory configuration)
FIG. 4 is a diagram for explaining the relationship between the overall flow of the image forming process according to the first embodiment and the memory. A supplementary description will be given except for those described with reference to FIGS. The 8-line memory 11 temporarily stores data read by the scanner 9 and subjected to image processing by the smoothing filter 10.

  The memory 4 includes an input / output code memory area 41, a page code memory area 42, a page macroblock head address storage area 43, and a main memory 47.

  The encoding unit 12 (page encoding unit) sequentially switches the encoding of the image data from the 8-line memory 11 according to the size of the main operation direction of the macroblock, and transfers it to the input / output code memory area 41 of the memory 4. A plurality of macroblock codes divided into are written.

  The memory 4 stores, in the input / output code memory area 41, codes of a plurality of macroblocks that are generated in the main operation direction and generated by the encoding unit 12.

  The code of the macro block that is generated by the encoding unit 12 and is continuous in a plurality of main operation directions in units of pages is stored in the page code memory area 42, and the start address of the macro block is stored in the page macro block start address storage area 43. To do. The code for each macroblock subjected to the synthesizing process by the page encoding unit 12 is stored in the page code memory area 42 in units of pages, and the start address is stored in the page macroblock start address storage area 43.

  Reference numeral 411 is an input / output code memory format example, reference numeral 412 is an example of a macroblock, reference numeral 414 is a page code memory format example, and reference numeral 420 is a page macroblock head address format example.

  The editing unit 13 includes a decoding unit 136, an editing processing unit 137, a synthesis memory 138, and a page encoding unit 139.

  The page encoding unit 139 sequentially reads and decodes the code for each macroblock from the input / output code memory area 41 and transfers the code to the editing processing unit 137. The edit processing unit 137 develops the decoded image data received from the decoding unit 136 into the synthesis memory 136, reads the character image to be synthesized from the main memory 47, performs the synthesis process, and performs the synthesis process. After that, it is read in the rotation direction and transferred to the page encoding unit 139.

  Here, the page encoding unit 139 constitutes the second macroblock variable length encoding means in the present invention.

  The synthesis memory 138 stores the decoded macroblock image.

  The page encoding unit 139 encodes the image in units of macroblocks subjected to the editing process from the editing processing unit 137 and writes the encoded image in the page code memory area 42. In addition, the head address of the encoded image data to be written is written in the page macroblock head address storage area 43.

  At this time, the head address of each macro block is obtained by measuring the code length of the code of each macro block and written into the page macro block head address storage area 43 of the memory 4.

  The page decoding unit 14 accesses the macroblock head address stored in the page macroblock head address storage area 43, reads the code of the macroblock stored in the page code memory area 42, decodes it, and outputs the subblock Image data to be output to the image processing unit 15 is generated in units.

  The image processing unit 15 receives the image data output from the page decoding unit 14, performs image processing, and transfers the image data to the printer engine 17 via the line memory 20.

  FIG. 5 is a schematic diagram illustrating an example of a format of the main memory 4. The input / output code memory area 41 is an area for storing code data obtained by encoding image data from the scanner 9 in units of macroblocks, and is also a memory area for temporarily storing code data when stored in the HDD 20.

  The page code memory area 42 is an area for storing code data in units of macroblocks of a plurality of pages after performing rotation processing and synthesis processing on code data in macroblock units in the input / output code memory area 41. .

  The page macroblock head address storage area 43 is an area for storing the head address of the code of the encoded macroblock of a plurality of pages in the page code memory area 42.

  The program area 44 is an area for storing various programs of the CPU 1.

  FIG. 6 is a schematic diagram showing an example of the format of the input / output code memory. The input / output code memory 411 includes a plurality of m * m pixel macroblocks 412. The macro block 412 includes a plurality of sub blocks 413 including n * n pixels.

  FIG. 7 is a schematic diagram showing an example of a macroblock in the page code memory area. The macrocode 414 in the page code memory area is composed of a plurality of sub-blocks 413 composed of n * n pixels, and a restart marker 452 is inserted at the end in the horizontal direction.

(1.3. Relationship between each processing flow and memory)
FIG. 8 is a diagram for explaining the flow of scanner input, input data encoding, editing processing, and page encoding processing. The data read from the scanner 9 is transferred to the smoothing filter processing unit (a). Image processing is performed by the smoothing filter processing unit 10 (b) and written to the 8-line memory 11. The image data in the 8-line memory 11 is read and encoded (c). The encoded code data is written into the memory 4 (d). The memory controller 3 reads the code data from the memory 4 and transfers it to the editing unit 13 (e). The editing unit 13 decodes the code data, edits the image, encodes it again, and stores the code data in the memory 4 (f).

  FIG. 9 is a diagram for explaining the flow of the decoding process and the printing process. The memory controller 3 reads the code data from the memory 4 and transfers it to the page decoding unit 14 (g) (h). The page decoding unit 14 performs a decoding process on the code data and transfers it to the image processing unit 15 (i). The image processing unit 15 receives the decoded image data from the page decoding unit 14 and performs image processing (j). The engine controller 16 transfers the data after image processing to the printer engine 17 (k).

  FIG. 10 is a diagram for explaining the flow of encoding processing and storage in the HDD. Since (a) to (d) from when the data read from the scanner 9 is processed and written to the memory 4 are the same as those described with reference to FIG. The HDD control unit 18 reads code data from the memory 4 (e). The HDD control unit 18 writes the received code data to the HDD (f).

  FIG. 11 is a diagram for explaining the flow of reading code data from the HDD, editing processing, and page encoding processing. The HDD control unit 18 reads the code data from the HDD 19 (g). The HDD control unit 18 writes the read code data into the memory 4 (h). The memory controller 3 reads the written code data from the memory 4 and transfers it to the editing unit 13 (i). The editing unit 13 decodes the code data, re-encodes the image after editing, and stores the re-encoded code data in the memory 4 (j).

  FIG. 12 is a diagram for explaining the flow of the scanner 9 input and the encoding process. The data read from the scanner 9 is transferred to the smoothing filter processing unit (a). Image processing is performed by the smoothing filter processing unit 10 and written to the 8-line memory 11 (b). The encoding unit 12 reads and encodes the image data in the 8-line memory 11, and writes the encoded code in the input / output code memory area 41 of the memory 4 (d).

  FIG. 13 is a diagram for explaining the flow of the editing process and the page encoding process. The decoding unit 136 in the editing unit 13 reads and decodes the code data from the input / output code memory area 41 of the memory 4 (e). The decoding unit 136 of the editing unit 13 transfers the decoded image data to the editing processing unit 137 (f). The editing processing unit 137 of the editing unit 13 writes the received image into the synthesis memory 138 (g). The editing processing unit 137 of the editing unit 13 reads the image data written in the synthesis memory 138 in the rotation direction (h), and transfers the read image data to the page encoding unit 139 (i). The page encoding unit 139 of the editing unit 13 encodes the image data in units of macroblocks, and sequentially writes the macroblock head address to the page macroblock head address storage area 43 of the main memory 4 (j). The page encoding unit 137 of the editing unit 13 encodes image data in units of macroblocks and sequentially writes them in the page code memory area 42 of the main memory 4.

  FIG. 14 is a diagram for explaining the flow of page decoding processing and print output. The page decoding unit 14 reads the macroblock head address from the page macroblock head address storage area 43 of the main memory 4 (l). The page decoding unit 14 reads code data in units of macroblocks from the page code memory area 42 of the main memory 4 based on the read start address of the macroblock (m). The page decoding unit 14 decodes the code of the read macroblock and transfers it to the image processing unit 15 (o). The image processing unit 15 reads the image data from the page decoding unit 14, performs image processing, and the image data subjected to the image processing is transmitted to the line memory 20 (p). The engine controller 16 (FIG. 2) transfers the data after image processing to the printer engine 17 (q).

  FIG. 15 is a diagram illustrating the flow of the encoding process, storage in the HDD, editing process, and page encoding process. Since reading (a) by the scanner 9 to writing (d) to the input / output code memory area 41 of the memory 4 is the same as described with reference to FIG. The HDD control unit 18 reads the code from the memory 4 (e), and the HDD control unit 18 writes the received code to the HDD (f).

  Conversely, the HDD control unit 18 reads code data in units of macroblocks from the HDD 19 (g), and the HDD control unit 18 writes the read code data in units of macroblocks to the input / output code memory area 41 of the main memory 4 ( h). The decoding unit 136 of the editing unit 13 reads the code data from the input / output code memory area 41 of the memory 4 and decodes the code (i) until the print output is the same as described with reference to FIGS. Therefore, explanation is omitted.

(1.4. Encoding unit)
FIG. 16 is a functional block diagram of the encoding unit of the image processing apparatus according to the first embodiment. The encoding unit 12 of the image processing apparatus includes an encoding processing unit 122, a macroblock head address storage unit 123, a memory address generation unit 124, a memory controller I / F 125, and a controller 126.

  Here, the macroblock head address storage unit 123 constitutes macroblock head address storage means of the present invention.

  The 8-line memory 11 is a memory for storing an image after image processing of one block line in the case of JPEG encoding in units of 8 * 8 pixels.

  The encoding processing unit 122 sequentially reads 8 * 8 pixels in the horizontal direction from the 8-line memory 11, encodes them by an encoding method such as JPEG, and transfers the encoded data to the memory controller I / F 125. At this time, as shown in FIG. 19, the encoding processing unit 122 determines the boundaries of macroblocks in the horizontal direction in order to perform encoding in units of a plurality of macroblocks in the horizontal direction, interrupts encoding, and The start address of the code of the macroblock written in the current memory 4 and the encoded data in the middle of encoding (in the case of JPEG, the code data in the middle of Huffman encoding and a shift value for managing the start address of the code) Temporary storage is performed, and macroblock encoding is sequentially performed to generate codes for a plurality of macroblocks. And when processing the data of 8 lines of the next block line, read the encoded data in the middle of the same macroblock and the head address of the code of the macroblock, and process the continuation of the encoding of the macroblock, It is possible to perform encoding of n * n pixels in units of macroblocks using only one line memory such as the 8-line memory 11.

  The macroblock head address storage unit 123 receives the number of the macroblock currently being processed and the macroblock switching signal from the encoding processing unit 122, receives the code memory address from the memory address generation unit 124, When the macroblock being processed by the encoding processing unit 122 is switched, the memory address of the code at the end of the macroblock before the switching is stored in the 8-line memory 11 for each of the plurality of macroblocks continuous in the horizontal direction. When each macroblock is processed at the block line, the memory address of the code at the end of the macroblock is sent to the memory address generation unit 124, so that the encoding of each macroblock can be continued.

  The memory address generation unit 124 receives and stores the code start address of the currently processed macroblock from the macroblock start address storage unit 123, receives the code data enable signal from the encoding processing unit 122, and stores the code data. It recognizes writing, counts up to the writing address of the next code, and makes it possible to generate memory addresses of a plurality of codes connected to the horizontal line.

  The memory controller I / F 125 receives the code data from the encoding processing unit 122, receives the code data address from the memory address generation unit 124, and transfers the code data to be written to the memory controller 3 and its address. The controller 126 controls the entire encoding unit 12.

  FIGS. 17A and 17B are flowcharts for explaining the encoding processing procedure. FIG. 18A is a schematic diagram illustrating an example of an 8-line memory format. FIG. 18-2 is a diagram for explaining the direction of processing of sub-blocks in a macro block. FIG. 19 is a diagram for explaining an example of an encoding format of image data.

  In the macroblock head address storage unit 123, a head address for storing a plurality of macroblocks continuous in the horizontal direction in the input / output code memory area 41 of the memory 4 is set (step S201). Here, in order to create a plurality of codes in parallel, the code size of each macroblock is first ensured to be large.

  A sub-block counter “J” in the vertical macroblock is initialized (step S202). The image data after the smoothing filter processing of one block line is stored in the 8-line memory 11, and the toggle 8-line memory 11 is switched (step S203).

  A horizontal macroblock counter “I” is initialized (step S204). A head address for storing the code of the I-th macroblock is received from the macroblock head address storage unit 123 (step S205). Data in the middle of encoding the I-th macroblock is set in the code format generation unit 1233 (described later in FIG. 20) from the macroblock code intermediate data storage unit 1234 (described later in FIG. 20) (step S206).

  Image data of the J block line of the I-th macroblock is read from the 8-line memory 11 in the horizontal direction (step S207).

  In accordance with each sub-block of the J-th block line of the I-th macroblock, encoding is performed from 0 to M as shown in FIG. 18A (step S208).

  The code of the I-th macroblock is sequentially stored in the macroblock head address storage unit 123 at the address indicated by the I-th macroblock head address in the input / output code memory area 41 of the main memory 4 (step S209).

  The memory address generation unit 124 receives the code length from the encoding processing unit 122 and receives the start address of the macroblock from the macroblock start address storage unit 123, and obtains the start address of the macroblock (step S210).

  The code format generation unit 1233 transfers and stores the data in the middle of encoding the I-th macroblock to the macroblock code intermediate data storage unit 1234 (step S211).

  The macroblock head address storage unit 123 receives and stores the I-th macroblock head address from the memory address generation unit 124 (step S212).

  The counter “I” of the macroblock in the horizontal direction is counted up (step S213).

  It is determined whether all the macroblocks in the horizontal direction have been processed (step S214). If it is determined that they have not been processed (No in step S214), the process returns to B, that is, step S205. If it is determined that all have been processed (Yes in step S214), the counter “J” of the sub-block in the vertical macroblock is counted up (step S215).

  It is determined whether all the sub-blocks in the vertical macroblock have been processed (step S216). If it is determined that it is not yet (No in step S216), C returns to step S203. When it is determined that all processing has been performed (Yes in step S216), it is determined whether or not the encoding of one page has been completed (step S217). If it is determined that it has not been completed (No in step S217), the process returns to D, that is, (step S) 201. If it is determined that the process has ended, the process ends as it is (Yes in step S217).

(1.4.1. Encoding processing unit)
FIG. 20 is a block diagram of an encoding processing unit in the encoding unit according to Embodiment 1. The encoding processing unit 122 includes an 8 * 8 buffer 1221, an 8-line memory address generation unit 1222, an RGB-> YUV conversion unit 1223, a YDCT processing unit 1224, a Y quantization processing unit 1225, a Y entropy encoding unit 1226, and a UDCT process. Unit 1227, U quantization processing unit 1228, U entropy coding unit 1229, VDCT processing unit 1240, V quantization processing unit 1241, V entropy coding unit 1242, code format generation unit 1233, and macroblock code intermediate data storage unit 1234.

  Here, the macroblock code intermediate data storage unit 1234 constitutes macroblock code intermediate data storage means in the present invention.

  The 8 * 8 buffer 1221 stores the 8 * 8 image of the sub-block. The 8-line memory address generation unit 1222 generates the start address of the 8 * 8 sub-block image from the 8-line memory 11 (a detailed block diagram is shown in FIG. 21).

  The RGB-> YUV conversion unit 1223 converts RGB of 8 * 8 pixels to YUV based on the JPEG standard, converts the Y component to the YDCT processing unit 1224, the U component to the UDCT processing unit 1227, and the V component to the VDCT processing unit. 1246.

  The YDCT processing unit 1224 performs DCT (Discrete Cosine Transform) on the Y component and transfers it to the quantization processing unit 1225. The Y quantization processing unit 1225 receives and quantizes the data after the DCT processing of the Y component from the YDCT processing unit 1224, and transfers the data to the Y entropy encoding unit 1226. The Y entropy encoding unit 1226 receives the quantized data of the Y component from the quantization processing unit 1225, encodes the data using the Huffman encoding method, and transfers the encoded data to the code format generation unit 1233. Hereinafter, U and V in the figure are also subjected to the same process as the process for Y (FIG. 23 shows a detailed block diagram).

  The UDCT processing unit 1227 performs DCT (discrete cosine transform) on the U component and transfers the U component to the quantization processing unit 1228. The U quantization processing unit 1228 receives and quantizes the data after the DCT processing of the U component from the UDCT processing unit 1227, and transfers the data to the U entropy coding unit 1229. The U entropy encoding unit 1229 receives the quantized data of the U component from the quantization processing unit 1228, encodes the data using the Huffman encoding method, and transfers the encoded data to the code format generation unit 1233.

  The VDCT processing unit 1240 performs DCT (Discrete Cosine Transform) on the V component and transfers it to the quantization processing unit 1241. The V quantization processing unit 1241 receives and quantizes the data after the DCT processing of the V component from the VDCT processing unit 1240 and transfers the data to the V entropy coding unit 1242. The V entropy encoding unit 1242 receives the quantized data of the V component from the quantization processing unit 1240, encodes the data using the Huffman encoding method, and transfers the encoded data to the code format generation unit 1233.

  The code format generation unit 1233 receives code data from the entropy encoding units 1226, 1229, and 1242, and forms a code (a detailed block diagram is shown in FIG. 28).

  The macroblock code intermediate data storage unit 1234 receives the data being encoded and the macroblock number from the code format generation unit 1233, and stores the data being encoded in the designated macroblock region (detailed in FIG. 29). Block diagram).

(1.4.2.8 line memory address generator)
FIG. 21 is a detailed block diagram of the 8-line memory address generation unit. The adder 12221 of the 8-line memory address generation unit 1222 calculates the number of processed sub-blocks in the horizontal direction.

  The register 12222 stores the number of sub-blocks processed in the horizontal direction obtained by the adder 12221. Further, after all the data of one block line is processed, the process returns to the initial value.

  The multiplier 12223 multiplies the register value acquired by the register 12222 by the number of words in one block to obtain the address of the 8-line memory 11.

  The comparison unit 12224 compares the number of subblocks with the number of subblocks in the macroblock, and generates a switching signal to the next macroblock.

  The adder 12225 calculates the number of processed horizontal macroblocks. The register 12226 stores the number of macroblocks processed in the horizontal direction acquired by the adder 12225. Further, after all the data of one block line is processed, the process returns to the initial value.

  The comparison unit 12227 compares the number of macroblocks with the number of macroblocks stored in the 8-line memory 11, and generates a switching signal for the 8-line memory 11.

  The controller 12228 controls the 8-line memory address generation unit.

  FIG. 22 is a schematic diagram illustrating an example of an MCU. First, a Y code is created, then U is encoded, and then V is encoded.

(1.2.3. Entropy coding unit)
FIG. 23 is a detailed block diagram of the entropy encoding unit in the encoding processing unit. FIG. 24A is a diagram illustrating an AC encoding procedure. FIG. 24-2 is a diagram for explaining a DC encoding procedure. FIG. 25 is a diagram for explaining DC / AC value cut-out processing. FIG. 26 is a diagram illustrating the DC value encoding unit. FIG. 27 is a diagram illustrating the AC value encoding unit. The entropy encoding unit 1226 in the encoding processing unit 122 will be described with reference to FIGS.

  The 8 * 8 DCT coefficient storage unit 12261 stores the 8 * 8 DCT coefficients after the DCT processing.

  As shown in FIGS. 24-1 and 24-2, the DC / AC value cutout unit 12262 obtains a DC value and an AC value from the 8 * 8 DCT coefficient storage unit 12261, one DC value as shown in FIG. 63 values are cut out, the DC value is transferred to the DC value encoding unit 12263, and the AC value is transferred to the AC value encoding unit 12264.

  The DC value encoding unit 12263 obtains the DC code and the code length of the DC value received from the DC / AC value cutout unit 12262 from the DC value Huffman table as shown in FIG.

  The AC value encoding unit 12264 obtains the AC code and the code length of the AC value received from the DC / AC value cutout unit 12262 from the AC value Huffman tables 2801 to 2804 as shown in FIG.

  The code format processing unit 12265 combines the DC and AC codes from the DC and AC value encoding units 12263 and 12264, and the code length thereof into one code and code length.

(1.4.4. Code format generator)
FIG. 28 is a detailed block diagram of the code format generation unit in the encoding processing unit of the encoding unit. The MUX 12331 of the code format generation unit 1233 selects the Y, U, and V codes from the entropy encoding units 1226, 1229, and 1242 in FIG. In this example, similarly to the MCU order shown in FIG. 22, a Y code is first created, then U coding is performed, and then V coding is performed.

  The shifter 12332 generates shifted data based on the leading address (generated by the adder 12337) in the connected code word in order to connect the generated code to data of one word length sequentially. .

  The register 12333 temporarily stores the code data after being shifted by the shifter 12332.

  The MUX 12334 selects the Y, U, and V codes from the entropy encoding units 1226, 1229, and 1242 in FIG.

  The MUX 12335 normally sends the processing result of the adder 12337 to the register 12336 in order to obtain the head address in the connected code word in order to connect to the data of one word length of the adder 12337. When transferring and setting the stored shift value as the intermediate data of the code of the I-th macroblock from the macroblock code intermediate data storage unit 1234 of FIG. 20 as shown in step S206 of FIG. The shift value is transferred from the macroblock code intermediate data storage unit 1234 to the register 12336.

  The register 12336 stores a value to which the shifter 12332 shifts in order to sequentially obtain the head address in the connected code word in order to connect to data of one word length. In step S211 of FIG. As shown, when the stored shift value is set as the intermediate data of the code of the I-th macroblock in the macroblock code intermediate data storage unit 1234 of FIG. 20, the shift to the macroblock code intermediate data storage unit 1234 is performed. Transfer the value.

  The adder 12337 adds the code length selected by the MUX 12334 and the accumulated shift value in one word, obtains the shift value at the head of the next code, and transfers it to the MUX 12335.

  The OR unit 12338 performs OR processing on the shifted code data 12333 and the accumulated intermediate code data in one word, connects the code data for each subblock in units of one word, and transfers the data to the MUX 12339.

  The MUX 12339 normally transfers the processing result of the OR unit 12338 to the register 12340 in order to obtain the connected code word in order to connect to the data 12338 having one word length, and step S206 in FIG. As shown in FIG. 20, when the stored intermediate code data is set as the intermediate data of the code of the I-th macroblock from the macroblock code intermediate data storage unit 1234, the macroblock code intermediate data storage unit 1234 The intermediate code data is transferred to the register 12340.

  The register 12340 stores the value ORed by the OR unit 12338 in order to obtain the connected code word to connect to one word length data, as shown in step S211 of FIG. 17-2. When the stored intermediate code data is set as the intermediate data of the code of the I-th macroblock to the macroblock code intermediate data storage unit 1234 of FIG. 20, the intermediate code data is transferred to the macroblock code intermediate data storage unit 1234 To do.

  The register 12341 for storing the code data stores the code data of one word when the codes for each sub-block are sequentially connected and grown into a code of one word.

  The controller 12342 controls the code format generation unit 1233, generates code data enable when the code data 12341 is generated, and notifies the memory address generation unit 124 of FIG. 16 that code data has been generated by one word. .

  In the first embodiment, at the time of encoding, there is an intermediate code data storage unit, and a code that has not reached the fixed length word in the process of combining variable length codes into fixed length words as in the code format generation unit 1233 of FIG. When the shift value for managing the head address in one word of the code is temporarily stored in the intermediate code data storage unit for each macroblock and is continuously encoded for each macroblock, the fixed length word temporarily saved is reached. By switching the value that is not used and the shift value for managing the leading address in one word of the code back to the code format generation unit 1233 in FIG. 28, the encoding switching with the variable length code is realized. .

  FIG. 29 is a detailed functional block diagram of the macroblock code intermediate storage unit in the encoding processing unit of the encoding unit. The address conversion unit 12341 of the macroblock code intermediate storage unit 1234 receives the number of the macroblock currently being processed from the 8-line memory address generation unit 1222 and converts it into the address of the macroblock number in the memory 4.

  The write signal generator 12342 receives the macroblock switching signal from the 8-line memory address generator 1222 and generates a write signal for the memory 4.

  The memory 4 stores data in the middle of encoding and shift data in the middle of encoding from the code format generation unit 1233 for each macroblock continuous in the horizontal direction.

  FIG. 30 is a detailed block diagram of the macroblock head address storage unit of the encoding unit. The address conversion unit 1231 of the macroblock head address storage unit 123 of the encoding unit 12 receives the number of the currently processed macroblock from the encoding processing unit 122 and converts it into the address of the macroblock number in the memory 4. .

  The write signal generation unit 1232 receives the macroblock switching signal from the encoding processing unit 122 and generates a write signal for the memory 4.

  The memory 4 stores the macroblock head address of each macroblock in the input / output code memory area 41 from the memory address generation unit 124 for each macroblock continuous in the horizontal direction.

(1.5. Editorial Department)
FIG. 31 is a functional block diagram of the editing unit of the image processing apparatus according to the first embodiment. FIG. 32 is a schematic diagram illustrating an example of a format of a composite memory in the editing unit.

  The memory controller I / F 1301 of the editing unit 13 reads the code of the macroblock from the input / output code memory area 41 of the main memory 4 and transfers the code to the buffer 1302 of the decoding unit 1303, and also the buffer 1305 of the JPEG encoding unit. The code data is sequentially transferred to the page code memory area 42 of the main memory 4, and the start address of the macroblock from the macroblock start address calculation unit 1312 is transferred to the page macroblock start address storage area 43.

  A buffer 1302 is a buffer for transferring code data to the decoding unit 1303.

  The decoding unit 1303 reads and decodes the code from the input / output code memory area 41 of the main memory 4 and transfers the code to the memory I / F of the synthesis memory 138. In this example, it is composed of JPEG (FIG. 39 shows a detailed block diagram of the decoding unit 1303 in the editing unit).

  As shown in FIGS. 37 and 38, the 8 * 8 rotation processing unit 1304 rotates the image data in the synthesis memory 138 in units of 8 * 8 pixels (sub-block units) in accordance with the designated rotation angle of 90 degrees. Apply processing.

  A buffer 1305 is a buffer for transferring the code data from the page encoding unit 1306 to the memory controller I / F 1301.

  The page encoding unit 1306 reads and decodes the code from the code page memory area of the synthesis memory 138 and transfers the code to the synthesis memory I / F 1309 of the synthesis memory 138. In this example, the page encoding unit 1306 is configured by JPEG (a detailed block diagram is shown in FIG. 43).

  A buffer 1307 is a buffer for transferring image data such as characters to be combined to the image combining unit 1308.

  The image composition unit 1308 subjects the macroblock image developed in the composition memory 138 to image data such as characters stored in the buffer 1307 and transfers the image data to the composition memory 138 again.

  The synthesis memory I / F 1309 performs an interface for accessing the synthesis memory 138.

  The synthesizing memory 138 temporarily stores the image data of the macroblock developed by the decoding unit 1303 in the variable claim invention numerical value 13. FIG. 33 shows an example of the format of the synthesis memory 138.

  The code length counting unit 1311 counts the total code length for each macroblock of the code encoded by the page encoding unit 1306 and transfers the counted code length to the macroblock head address calculating unit 1312.

  The macroblock head address calculation unit 1312 receives the total code length for each macroblock from the code length count unit 1311, calculates the head address of each macroblock code, and transfers it to the memory controller I / F 1301.

  The memory address generation unit 1313 receives the start address of each macroblock from the macroblock start address calculation unit 1312 and generates an address in the memory 4 that transfers the code data of the page encoding unit 1306 via the memory controller I / F 1301. To do.

  The memory address generation unit 1313 generates an address of the synthesis memory 138. When re-encoding a macroblock after image synthesis in the synthesis memory 138, by changing the order in which the macroblocks are read out in units of sub-blocks according to the specified rotation angle in units of 90 degrees, rotation processing in units of 90 degrees is performed. (See FIG. 36).

  The controller 1316 controls the entire editing processing unit 13.

  FIGS. 33-1 and 33-2 are flowcharts illustrating an editing process procedure in the image processing apparatus according to the first embodiment. FIG. 34 is a diagram for explaining the order of reading data from the macroblock. FIG. 35 is a diagram for explaining a page level rotation process. FIG. 36 is a diagram for explaining the rotation processing at the macroblock level. 37 and 38 are diagrams for explaining sub-block level rotation processing. The editing processing procedure will be described with reference to FIGS.

  The head address of the macro record is set to 0 (step S301). As shown in FIG. 36, one macroblock code corresponding to the rotation angle is read from the main memory. At this time, the head address is read from the macro block head address area of the main memory of the corresponding macro block, and the head address of the code of the corresponding macro block is obtained by adding the head address of the code of this page (step S302).

  The code length counter is set to 0 (step S303). As shown in FIG. 34, one subblock code is decoded from the macroblock (step S304). It is determined whether all sub-blocks in the macro block have been processed (step S305). If not yet (No in step S305), the process returns to step S304.

  If all the processing has been completed (Yes in step S305), the image composition unit inserts a character image or the like into the macroblock image, and updates the value of the composition memory (step S306).

  As shown in FIG. 37, the sub-block image is cut out from the synthesis memory 138 according to the rotation angle based on the image rotation process, and transmitted to the 8 * 8 rotation processing unit 1304 (step S307). The 8 * 8 rotation processing unit 1304 rotates each pixel according to the rotation angle at the sub-block level (step S308).

  The page encoding unit 1306 encodes the pixels of the sub block of the 8 * 8 rotation processing unit 1304, and sets it as a code length counter (step S309). The code of the macro block after the editing process is stored in the code page area indicated by the start address of the macro block in the main memory + the start address of the code (step S310). The value of the start address of the macro block is stored in the macro block address storage area of the main memory (step S311).

  The head address of the macro block is replaced with the counter + the head address of the macro block (step S312). It is determined whether all macroblocks in the page have been processed (step S313). If it is determined that it has not been processed (No in step S313), the process returns to step S302. If it is determined that the processing has been performed (Yes in step S313), the processing ends.

(1.5.1 Decoding unit in editing unit)
FIG. 39 is a functional block diagram of the decoding unit in the editing unit. The decoding processing unit 13031 of the decoding unit 1303 in the editing unit 13 reads a code from the input / output code memory area 41 of the main memory 4, decodes it, and transfers it to the synthesis memory 138. (FIG. 41 shows a detailed functional block diagram of the decryption processing unit 13031).

  The read memory address generation unit 13032 generates a memory address to be read from the input / output memory area of the main memory 4, and receives a code word request signal for requesting the next code word from the decoding processing unit 13031 and one macroblock. A macroblock end signal indicating that decoding has been completed is received, and the start address of the input / output memory area of the main memory 4 for each macroblock is received from the macroblock start address storage unit 13033, thereby generating a memory address to be read. To do.

  Here, the read memory address generation unit 13032 and the macroblock head address storage unit 13033 constitute macroblock code address recognition means (claim 1) in the present invention.

  The macroblock head address storage unit 13033 stores the head address of each macroblock in the input / output memory area of the main memory 4.

  FIG. 40 is a flowchart illustrating a processing procedure performed by the decoding processing unit in the editing unit. FIG. 41 is a schematic diagram showing the read order of the data encoded for each macroblock and the macroblock composed of sub-blocks.

  The start address of the memory 4 is set to 0 for a plurality of macroblocks continuous in the horizontal direction (step S401). Next, the sub-block counter “J” in the vertical macroblock is initialized to 0 (step S402). The head address of the I-th macroblock is read in the main scanning direction of the column of the J-th macroblock in the sub-scanning direction from the macroblock head address storage unit 13033 (step S403). The code is read from the buffer 1302 in FIG. 31 (step S404).

  Decoding is sequentially performed for each sub-block from 0 to M on the J block line of the I-th macroblock (step S405). I is set to I + 1 (step S406). It is determined whether I is greater than β (step S407). If not, the process returns to step S403. If it is determined that it is larger (Yes in step S407), it is determined whether or not all codes in the input / output code memory have been decoded (step S408). If it is determined that it is not yet (No in step S408), J is replaced with J + 1 (step S409), and the process returns to step S402. If it is determined that the process has ended (Yes in step S408), the process ends.

  FIG. 42 is a functional block diagram of the decoding processing unit in the decoding unit of the editing unit. The entropy decoding unit 13041 of the decoding processing unit 13031 of the decoding unit 1303 of the editing unit 13 sequentially reads the code data of the main memory 4, performs the entropy decoding processing of the Y component, and sends it to the Y inverse quantization processing unit 13042. Transfers 8 * 8 pixel data of Y component after quantization, performs entropy decoding processing of U component, and transfers 8 * 8 pixel data of U component after quantization to U inverse quantization processing unit 13044 Then, the V component entropy decoding process is performed, and the quantized V component 8 * 8 pixel data is transferred to the V inverse quantization processing unit 13046.

  The Y inverse quantization processing unit 13042 receives the quantized Y component 8 * 8 pixel data from the Y entropy decoding unit 13041, performs inverse quantization, obtains the Y component 8 * 8 pixel DCT coefficient, Transfer to the processing unit 13043.

  The YIDCT processing unit 13043 receives Y * 8 * 8 pixel DCT coefficients from the inverse quantization processing unit, performs IDCT (Inverse Discrete Cosine Transform), and performs horizontal 8-pixel data of the Y component of the currently processed line. Is transferred to the YUV-> RGB conversion unit 13048.

  The U inverse quantization processing unit 13044 receives the quantized U component 8 * 8 pixel data from the U entropy decoding unit 13041, inversely quantizes the U component 8 * 8 pixel DCT coefficient, and obtains the UIDCT. Transfer to the processing unit 13045.

  The UIDCT processing unit 13045 receives the DCT coefficient of 8 * 8 pixels of the U component from the inverse quantization processing unit 13044, performs IDCT (Inverse Discrete Cosine Transform), and performs horizontal 8 pixels of the U component of the currently processed line. Data is obtained and transferred to the YUV-> RGB conversion unit 13048.

  The V inverse quantization processing unit 13046 receives the quantized 8 * 8 pixel data of the V component from the V entropy decoding unit 13041, inversely quantizes the V component 8 * 8 pixel DCT coefficient, and obtains VIDCT Transfer to the processing unit 13047.

  The VIDCT processing unit 13047 receives the 8 * 8 pixel DCT coefficient of the V component from the inverse quantization processing unit 13046, performs IDCT (Inverse Discrete Cosine Transform), and performs horizontal 8 pixels of the V component of the currently processed line. Data is obtained and transferred to the YUV-> RGB conversion unit 13048.

  The YUV-> RGB conversion processing unit 13048 converts the Y, U, and V pixel data from the IDCT processing units 13043, 13045, and 13047 into RGB.

  FIG. 43 is a block diagram of the page encoding unit in the editing unit.

  An 8 * 8 buffer 13061 of the page encoding unit 1306 in the editing unit 13 is a buffer for storing an 8 * 8 image of a sub-block.

  The horizontal sub-block counting unit 13062 counts the number of processed horizontal sub-blocks, and transfers a horizontal sub-block end signal as a signal at the end of the horizontal sub-block to the restart marker generating unit 13073.

  The RGB-> YUV conversion unit 13063 converts RGB of 8 * 8 pixels to YUV based on the JPEG standard, converts the Y component to the YDCT processing unit, the U component to the UDCT processing unit, and the V component to the VDCT processing unit. Forward.

  The YDCT processing unit 13064 performs DCT (discrete cosine transform) on the Y component and transfers the result to the quantization processing unit 13065.

  The Y quantization processing unit 13065 receives and quantizes the data after the DCT processing of the Y component from the YDCT processing unit 13064, and transfers the data to the Y entropy encoding unit 13066.

  The Y entropy encoding unit 13066 receives the data after quantization of the Y component from the quantization processing unit, encodes the data using the Huffman encoding method, and transfers the encoded data to the code format generation unit 13074.

  The UDCT processing unit 13067 performs DCT (discrete cosine transform) on the U component and transfers the U component to the quantization processing unit.

  The U quantization processing unit 13068 receives and quantizes the data after the DCT processing of the U component from the UDCT processing unit 13067 and transfers the data to the U entropy encoding unit 13069.

  The U entropy encoding unit 13069 receives the quantized data of the U component from the quantization processing unit 13068, encodes it using the Huffman encoding method, and transfers the encoded data to the code format generation unit 13074.

  The VDCT processing unit 13070 performs DCT (Discrete Cosine Transform) on the V component and transfers it to the quantization processing unit 13071.

  The V quantization processing unit 13071 receives and quantizes the data after the DCT processing of the V component from the VDCT processing unit, and transfers the data to the V entropy coding unit.

  The V entropy encoding unit 13072 receives the quantized data of the V component from the quantization processing unit, encodes the data using the Huffman encoding method, and transfers the encoded data to the code format generation unit 13074.

  The restart marker generation unit 13073 receives the horizontal subblock end signal from the horizontal subblock count unit 13062, generates a restart marker, and transfers it to the code format generation unit 13074.

  The code format generation unit 13074 receives the code data from the entropy encoding units 13066, 13069, and 13072 and the restart marker code from the restart marker generation unit 13073, and forms a code.

(1.5.1. Page coding section in the editing section)
FIG. 44 is a flowchart illustrating a processing procedure performed by the page encoding unit. FIG. 45 is a diagram for explaining the processing order of sub-blocks in a macro block.

  The page encoding unit 1306 in the editing unit 13 reads the image after the 8 * 8 rotation processing from the 8 * 8 rotation processing unit 1304 (step S501). The page encoding unit 1306 encodes the image after the 8 * 8 rotation process (step S502). It is determined whether or not one block line has been processed (step S503). If not yet (No in step S503), the process returns to step S502. If it is determined that the processing has been performed (Yes in step S503), a restart marker is inserted (step S504). It is determined whether an image of m * m block (macro block) has been processed (step S505). If it is determined that it is not yet (No in step S505), the process returns to step S502. If it is determined that the processing has been completed (Yes in step S505), the processing is terminated as it is.

(1.6. Page decryption unit)
FIG. 46 is a detailed functional block diagram of the page decoding unit shown on page 2 of the image processing apparatus according to the first embodiment.

  The memory controller I / F 141 of the page decoding unit 14 of the image processing apparatus reads the code for each macroblock in the page code memory area of the memory 4 from the read memory address generation unit 144, transfers the code to the buffer 142, and The start address for each macroblock is read from the page macroblock start address storage area 43, and an I / F process is performed with the memory controller 3 for transfer to the macroblock start address storage unit 145.

  Here, the read memory address generation unit 144 and the macroblock head address storage unit 145 constitute macroblock code address recognition means in the present invention (claim 2). The macroblock head address storage unit 145 constitutes a macroblock head address storage means in the present invention (claim 2).

  The buffer 142 temporarily stores code data to be transferred to the decoding processing unit 143.

  The decoding processing unit 143 reads and decodes the code from the page code memory area 42 of the main memory 4 and transfers the code to the image processing unit 15 in units of sub-blocks (a detailed block diagram of the image processing unit 15 is shown in FIG. 48). .

  The read memory address generation unit 144 is a unit that generates a memory address to be read from the page code memory area 42 of the main memory 4, and a code word request signal for requesting the next code word from the decoding processing unit 143 and one macro. A macroblock line end signal indicating that the horizontal decoding of the block has been completed is received, and the start address of the macroblock in the page code memory area 42 of the main memory 4 for each macroblock is received from the macroblock start address storage unit 145. By receiving it, a memory address to be read is generated.

  The macroblock head address storage unit 145 receives and stores the head address of each macroblock from the page macroblock head address storage area 43 of the main memory 4, and the macroblock number being processed from the decoding processing unit 143 and the macroblock When the line end signal is received, the memory address of the code in the middle of the code of the macroblock is received from the read memory address generation unit 144, stored, and decoded when the macroblock is decoded again. The memory address of the code being converted is read and transferred to the memory address generation unit 144.

  The controller 146 controls the page decoding unit 14.

  FIGS. 47-1 and 47-2 are flowcharts for explaining the page decoding processing procedure in the page decoding unit. FIG. 48A is a schematic diagram illustrating an example of an 8-line memory format. FIG. 48-2 is a diagram for explaining the decoding order of sub-blocks constituting a macroblock.

  The macro block head address storage unit 145 reads and sets the head address stored in the macro block head address storage area 43 of the memory 4 of the plurality of macro blocks continuous in the horizontal direction (step S601). The sub-block counter “J” in the vertical macroblock is initialized (step S602). A horizontal macroblock counter “I” is initialized (step S603).

  A head address for storing the code of the I-th macroblock is received from the macroblock head address storage unit 145 (step S604). Data in the middle of encoding the I-th macroblock is set in the register 143173 of FIG. 51 from the macroblock decoding shift value storage unit 143172 of FIG. 51 of the shift value generation unit 14317 of FIG. 50 (step S605).

  Here, the macroblock decoding shift value storage unit 143172 constitutes a macroblock decoding intermediate data storage unit in the present invention (claim 2).

  Here, the macroblock decoded shift value storage unit 143172 constitutes an output multi-value block line data storage means in the present invention (claim 12).

  The code data of the J block line of the I-th macroblock are read in the horizontal direction from the buffer 142 in FIG. 46 as shown in FIG. 48-1 (step S606). Decoding is sequentially performed for each sub-block of the J-th block line of the I-th macroblock (step S607).

  It is determined whether or not a restart marker has been detected (step S608). If it is not determined that it has been detected (No in step S608), the process returns to step S607. If it is determined that it has been detected (Yes in step S608), a shift value during decoding of the I-th macroblock is set in the macroblock decoding shift value storage unit 143172 of the shift value generation unit in FIG. S609).

  The macroblock head address storage unit 143 in FIG. 46 receives and stores the I-th macroblock head address from the read memory address generation unit 144 in FIG. 46 (step S610).

  The counter “I” of the macroblock in the horizontal direction is counted up (step S611). It is determined whether or not all the macroblocks in the horizontal direction have been processed (step S612). If it is determined that the process has not yet been completed (No in step S612), the process returns to step S604. If it is determined that the process has been completed (Yes in step S612), the counter “J” of the sub-block in the vertical macroblock is incremented (step S613).

  It is determined whether all the sub-blocks in the vertical macroblock have been processed (step S614). If it is determined that the process has not yet been completed (No in step S615), the process returns to step S603. When it is determined that the process is finished (Yes in step S614), it is determined whether or not the decoding of one page is finished (step S615). If it is determined that one page has not been combined (No in step S615), the process returns to step S601. If it is determined that the process has been completed, the process ends.

  FIG. 49 is a detailed block diagram of the decoding processing unit in the page decoding unit. The entropy decoding unit 1431 of the decoding processing unit 143 of the page decoding unit 14 sequentially reads the code data of the main memory 4, performs entropy decoding processing of the Y component, and after quantization to the Y inverse quantization processing unit 1432 The 8 * 8 pixel data of the Y component is transferred, the U component entropy decoding process is performed, and the U component 8 * 8 pixel data after the quantization is transferred to the U inverse quantization processing unit 1434, The component entropy decoding process is performed, and the 8 * 8 pixel data of the V component after the quantization is transferred to the V inverse quantization processing unit 1436. In addition, a restart marker is detected, the end of the macroblock line is detected, and a macroblock end signal is generated.

  The Y inverse quantization processing unit 1432 receives the 8 * 8 pixel data of the Y component after quantization from the Y entropy decoding unit, performs inverse quantization, obtains the DCT coefficient of the 8 * 8 pixel of the Y component, and performs YIDCT processing. Forward to the unit 1433.

  The YIDCT processing unit 1433 receives the 8 * 8 pixel DCT coefficient of the Y component from the inverse quantization processing unit, performs IDCT (Inverse Discrete Cosine Transform), and performs horizontal 8-pixel data of the Y component of the line currently being processed. Is transferred to the YUV-> RGB conversion unit 1438.

  The U inverse quantization processing unit 1434 receives the quantized U component 8 * 8 pixel data from the entropy decoding unit, performs inverse quantization, obtains the U component 8 * 8 pixel DCT coefficient, and the UIDCT processing unit. 1435.

  The UIDCT processing unit 1435 receives the 8 * 8 pixel DCT coefficient of the U component from the inverse quantization processing unit 1434, performs IDCT (Inverse Discrete Cosine Transform), and performs horizontal 8 pixels of the U component of the currently processed line. Data is obtained and transferred to the YUV-> RGB converter 1438.

  The V inverse quantization processing unit 1436 receives 8 * 8 pixel data of the V component after quantization from the entropy decoding unit, performs inverse quantization, obtains a DCT coefficient of 8 * 8 pixels of the V component, and performs a VIDCT processing unit 1437.

  The VIDCT processing unit 1437 receives the 8 * 8 pixel DCT coefficient of the V component from the inverse quantization processing unit, performs IDCT (Inverse Discrete Cosine Transform), and performs horizontal 8-pixel data of the V component of the currently processed line. Is transferred to the YUV-> RGB conversion unit 1438.

  The YUV-> RGB conversion processing unit 1438 converts the Y, U, and V pixel data from the IDCT processing units 1433, 1435, and 1437 into RGB.

  The macroblock count unit 1439 receives and counts the end signal of the macroblock line from the entropy decoding unit 1431, and generates a macroblock number being processed. When the horizontal macroblock number is counted, the initial value is restored.

  FIG. 50 is a detailed block diagram of the entropy decoding unit in the decoding processing unit. The read code register 14311 of the entropy decoding unit 1431 of the decoding processing unit 143 of the page decoding unit 4 temporarily stores the code data of the buffer 142 of FIG.

  The shifter 14312 shifts the variable length code based on the shift value obtained by the shift value generation unit 14317, and transfers the variable length code to DC, the AC value decoding units 14314 and 14315, and the restart code determination unit 14313. .

  The restart determination unit 14313 that determines the restart marker code determines whether the code from the shifter 14312 is a restart marker, and displays the determined macroblock line end signal with the read memory address generation unit 144 of FIG. 46 macroblock head address storage unit 145. In addition, the code length at that time is transferred to the MUX 14316 as the consumed code length.

  If the code from the shifter 14312 is a DC value code, the DC value decoding unit 14314 decodes the DC data, transfers it to the 8 * 8 DCT data generation unit 14318, and transfers the code length at that time to the MUX 14316 as the consumed code length. To do.

  If the code from the shifter 14312 is an AC value code, the AC value decoding unit 14315 decodes the AC data, transfers it to the 8 * 8 DCT data generation unit 14318, and transfers the code length at that time to the MUX 14316 as the consumed code length. To do.

  The MUX 14316 receives the consumed code length from the DC / AC value decoding units 14314 and 14315 and the restart code determination unit 14313 and transfers the received code length to the shift value generation unit 14317.

  The shift value generation unit 14317 obtains the start address of the next code from the consumed code length from the MUX 14316 and controls the shifter 1431 to always set the start of the code to the DC, AC value decoding unit, and restart code determination unit. To supply.

  The 8 * 8 DCT data generation unit 14318 generates 8 * 8 DCT data from the DC and AC values from the DC and AC value decoding units 14314 and 14315, and sends them to the inverse quantization units 1432, 1434, and 1436 in FIG. Forward.

  FIG. 51 is a detailed block diagram of the shift value generation unit in the entropy decoding unit. That is, this is a detailed block diagram of the shift value generation unit 14317 of the entry pe decoding unit 1431 of the decoding processing unit 143 of the page decoding unit 14.

  The MUX 143171 of the shift value generation unit 14317 normally sends the value of the adder 143174 to the register 143173 in order to obtain the shift value of the shifter 14312 in FIG. In step S605 in FIG. 47-1, the macro block shift value to be processed is read from the macro block decoding shift value storage unit 143172, transferred to the register 143173, and transferred to the register 143173. In step S609, the shift value obtained by the adder 143174 is transferred to the macroblock decoding shift value storage unit 143172, and the shift value of the currently processed macroblock is stored.

  In step S605 of FIG. 47-1, the macroblock decoding shift value storage unit 143172 reads the shift value of the macroblock to be processed from the macroblock decoding shift value storage unit 143172 and transfers it to the register 143173. In step S609 in FIG. 47-1, the shift value obtained by the adder 143174 is transferred to the macroblock decoding shift value storage unit 143172, and the shift value of the macroblock currently being processed is stored.

  The register 143173 stores the shift value of the shifter 14312 of FIG. 50 which is the head address of the next code in the accumulated one code word.

  The adder 143174 obtains the shift value of the shifter 14312 of FIG. 50, which is the head address of the next code in the accumulated one code word.

  The comparator 143175 compares the BIT length of the code word with the shift value obtained by the adder 143174, and determines whether or not the next code word is requested.

  If the result of the comparator 143175 exceeds 1 word, the subtractor 143176 subtracts the BIT length of 1 word from the shift value of the adder 143174 to read the next code word, and transfers the result to the MUX 143171. .

  The register 143177 temporarily stores the determination result of the comparator 143175, generates a code word request signal, and transfers it to the read memory address generation unit 144 of FIG.

  Here, at the time of decoding, an intermediate decoded data storage unit is included, and a code grouped into fixed-length words is being decoded as in the macroblock decoded shift value storage unit 143172 of the shift value generation unit 14317 in FIG. A shift value for managing the head address in one word of the code is temporarily stored in the macroblock decoding shift value storage unit 143172, and is temporarily saved when each macroblock is continuously decoded, and one word of the code is stored. The shift value for managing the head address is returned to the shift value generation unit 14317 in FIG. 51 again, thereby realizing decoding switching with the variable length code.

  FIG. 52 is a detailed block diagram of the macroblock head address storage unit shown in FIG. 46 in the page decoding unit. The address conversion unit 1451 of the macroblock head address storage unit 145 receives the number of the currently processed macroblock from the decoding processing unit 143 in FIG. 46 and converts it to the address of that macroblock number in the memory 1453.

  The write signal generation unit 1452 receives the macroblock line end signal from the decoding processing unit 143 in FIG. 46 and generates a write signal in the memory 1453.

  The memory 1453 stores the macroblock head address of each macroblock in the page code memory area 42 from the read memory address generation unit 144 of FIG. 46 for each macroblock continuous in the horizontal direction.

  FIG. 53 is a detailed block diagram of a macroblock decoded shift value storage unit in the shift value generation unit shown in FIG. The address conversion unit 1431721 of the macroblock decoding shift value storage unit 143172 receives the number of the currently processed macroblock from the decoding processing unit 143 of FIG. 46 and converts it to the address of the macroblock number in the memory 1431723.

  The write signal generation unit 1431722 receives the macroblock line end signal from the decoding processing unit 143 in FIG. 46 and generates a write signal in the memory 1431723.

  The memory 1431723 stores shift data in the middle of decoding from the MUX 143171 in FIG. 51 for each macroblock continuous in the horizontal direction.

(1.7. Image Processing Unit)
FIG. 54 is a functional block diagram of the image processing unit of the image processing apparatus according to the first embodiment. The buffer 151 of the image processing unit 15 temporarily stores the image data from the page decoding unit 14.

  The color correction processing unit 152 performs color correction processing on the multi-value RGB data stored in the buffer 151 and converts it into multi-value CMYK data.

  The gradation processing unit 153 converts the data after gradation processing received from the color correction processing unit 152 into binary, quaternary, 16-value data, and the like.

  A PIXEL TO PLANE conversion unit 154 converts the binary, 4-value, and 16-value data subjected to gradation processing by the gradation processing unit 153 from PXEL to PLANE only for the designated version of the data. Transfer to / F155.

  The line memory I / F 155 temporarily stores the image data converted by the PIXEL TO PLANE conversion unit 154 and transfers it to the line memory 20 (FIG. 4).

  The line memory address generation unit 156 generates an address of the line memory 20.

  The controller 157 controls the image processing unit 15.

  FIG. 55 is a flowchart illustrating an image processing procedure performed by the image processing unit. The buffer 151 receives image data from the 8-line memory 11 (step S701). The color correction processing unit 152 performs color correction processing to convert from RGB to CMYK (step S702). The gradation processing unit 153 performs gradation processing on the multi-valued CMYK image and converts it into a processed image (step S703). The CMYK image data after gradation processing is compiled into a fixed length only for the designated plane, and written to the line memory 20 (step S704). It is determined whether or not all the images have been processed (step S705). If not yet (No in step S705), the process returns to step S701. If completed (Yes in step S705), the process is finished as it is.

(2. Modification 1)
(2.1. Schematic Configuration of Image Processing Device According to Modification 1)
FIG. 56-1 is a hardware configuration diagram of the image processing apparatus according to the first modification. FIG. 56-2 is a schematic diagram of a first modification of the macroblock code format in the page code memory area. Here, as Modification 1, there is an example in which the restart marker 452 is not provided at the horizontal end of the macroblock code format 414 of the page code memory 4 shown in FIG. As shown in FIG. 56, the macro block 561 composed of n * n sub-blocks 562 does not include a restart marker at the end in the horizontal direction, so that the editing unit 1300, the page decoding unit, 1400 is different from the first embodiment.

(2.2. Editorial Department)
FIG. 57 is a detailed block diagram of the page encoding unit in the editing unit according to the first modification. Here, the page encoding unit 13060 in the editing unit 13 according to Modification 1 shown in FIG. 57 is a page encoding unit in the case of using the format having no restart marker shown in FIG.

  The 8 * 8 buffer 571 of the page encoding unit 13060 is a buffer that stores an 8 * 8 image of a sub-block.

  The RGB-> YUV conversion unit 572 converts 8 * 8 pixel RGB to YUV based on the JPEG standard, converts the Y component to the YDCT processing unit 573, the U component to the UDCT processing unit 576, and the V component to the VDCT processing. The data is transferred to the unit 579.

  The YDCT processing unit 573 performs DCT (Discrete Cosine Transform) on the Y component and transfers it to the quantization processing unit 574.

  The Y quantization processing unit 574 receives and quantizes the data after the DCT processing of the Y component from the YDCT processing unit 573, and transfers the data to the Y entropy encoding unit 575.

  The Y entropy encoding unit 575 receives the quantized data of the Y component from the quantization processing unit, encodes it using the Huffman encoding method, and transfers the encoded data to the code format generation unit 582.

  The UDCT processing unit 576 performs DCT (discrete cosine transform) on the U component and transfers the U component to the quantization processing unit 577.

  The U quantization processing unit 577 receives and quantizes the data after the DCT processing of the U component from the UDCT processing unit 576, and transfers the data to the U entropy coding unit 578.

  The U entropy encoding unit 578 receives the quantized data of the U component from the quantization processing unit, encodes the data using the Huffman encoding method, and transfers the encoded data to the code format generation unit 582.

  The VDCT processing unit 579 performs DCT (Discrete Cosine Transform) on the V component and transfers it to the quantization processing unit 580.

  The V quantization processing unit 580 receives and quantizes the data after the DCT processing of the V component from the VDCT processing unit 579, and transfers the data to the V entropy encoding unit 581.

  The V entropy encoding unit 582 receives the quantized data of the V component from the quantization processing unit 580, encodes the data using the Huffman encoding method, and transfers the encoded data to the code format generation unit 582.

  The code format generation unit 582 receives the code data from the entropy encoding units 575, 578, and 581 and forms a code.

  FIG. 58A is a flowchart for explaining the processing procedure of the page encoding unit according to the first modification. FIG. 58-2 is a diagram for explaining the order in which subblocks are read in the macroblock according to the first modification.

  An image after 8 * 8 editing processing is read from the 8 * 8 rotation processing unit 1304 (step S801). The image after the 8 * 8 pixel editing process is encoded by the encoding unit (step S802). It is determined whether one block line has been processed (step S803). One block line is indicated by a horizontal arrow in FIG.

  If it is determined that it is not yet (No in step S803), the process returns to step S802. If it is determined that one block line has been processed (Yes in step S803), it is determined whether an image of an m * m block (macro block) has been processed (step S804). If it is determined that it has not been processed yet (No in step S804), the process returns to step S802. If it is determined that the process is complete (Yes in step S804), the process ends.

(2.3. Page Decoding Unit)
FIG. 59 is a detailed block diagram of the page decoding unit in the image processing apparatus according to the first modification. The memory controller I / F 141 of the page decoding unit 1400 transfers the code for each macroblock in the page code memory area 42 of the memory 4 from the read memory address generation unit 144 to the read buffer 142, and starts the page macroblock head of the memory 4. The head address for each macroblock is read from the address storage area 43 and an interface process with the memory controller 3 for transferring to the macroblock head address storage unit 145 is performed.

  The buffer 142 temporarily stores a code for transfer to the decoding processing unit 143.

  The decoding processing unit 143 reads and decodes the code from the page code memory area 42 of the main memory 4 and transfers the code to the image processing unit 15 in units of sub-blocks (a detailed block diagram is shown in FIG. 62).

  The read memory address generation unit 144 is a unit that generates a memory address to be read from the page code memory area 42 of the main memory 4, and a code word request signal for requesting the next code word from the decoding processing unit 143 and one macro. A macroblock line end signal indicating that the horizontal decoding of the block has been completed is received, and the start address of the macroblock in the page code memory area 42 of the main memory 4 for each macroblock is received from the macroblock start address storage unit 145. As a result, the memory address to be read is generated.

  The macroblock head address storage unit 145 receives and stores the head address of each macroblock from the page macroblock head address storage area 43 of the main memory 4, and the macroblock number being processed from the decoding processing unit 143 and the macroblock When the line end signal is received, the memory address of the code in the middle of the code of the macroblock is received from the read memory address generation unit 144, stored, and decoded when the macroblock is decoded again. The memory address of the code being converted is read and transferred to the memory address generation unit 144.

  The controller 146 controls the page decoding unit 1400.

  60A and 60B are flowcharts for explaining the processing procedure of the page decoding unit in the image processing apparatus according to the first modification. FIG. 61A is a schematic diagram illustrating an example of an 8-line memory format according to the first modification. FIG. 61-2 is a diagram for explaining the decoding order of sub-blocks constituting a macroblock according to Modification 1.

  Steps S901 to S907 in FIG. 60A are the same as steps S601 to S607 in FIG.

  The horizontal sub-blocks of the I-th macro block are counted (step S908). Then, it is determined whether or not all sub-blocks have been decoded in the horizontal direction (step S909). If it is not determined that it has been detected (No in step S909), the process returns to step S907. When it is determined that it has been detected (Yes in step S909), the process proceeds to step S910.

  Steps S910 to S916 are the same as steps S609 to S615 in FIG.

  FIG. 62 is a detailed block diagram of the decoding processing unit in the editing processing unit according to the first modification.

  The entropy decoding unit 1431 of the decoding processing unit 143 of the page decoding unit 1400 sequentially reads the code data of the main memory 4, performs entropy decoding processing of the Y component, and performs quantization to the Y inverse quantization processing unit 1432 The 8 * 8 pixel data of the Y component is transferred, the U component entropy decoding process is performed, and the U component 8 * 8 pixel data after the quantization is transferred to the U inverse quantization processing unit 1434, The component entropy decoding process is performed, and the 8 * 8 pixel data of the V component after the quantization is transferred to the V inverse quantization processing unit 1436.

  The Y inverse quantization processing unit 1432 receives the 8 * 8 pixel data of the Y component after quantization from the Y entropy decoding unit, performs inverse quantization, obtains the DCT coefficient of the 8 * 8 pixel of the Y component, and performs YIDCT processing. Forward to the unit 1433.

  The YIDCT processing unit 1433 receives the 8 * 8 pixel DCT coefficient of the Y component from the inverse quantization processing unit, performs IDCT (Inverse Discrete Cosine Transform), and performs horizontal 8-pixel data of the Y component of the line currently being processed. Is transferred to the YUV-> RGB conversion unit 1438.

  The U inverse quantization processing unit 1434 receives the quantized U component 8 * 8 pixel data from the entropy decoding unit, performs inverse quantization, obtains the U component 8 * 8 pixel DCT coefficient, and the UIDCT processing unit. 1435.

  The UIDCT processing unit 1435 receives the 8 * 8 pixel DCT coefficient of the U component from the inverse quantization processing unit 1434, performs IDCT (Inverse Discrete Cosine Transform), and performs horizontal 8 pixels of the U component of the currently processed line. Data is obtained and transferred to the YUV-> RGB converter 1438.

  The V inverse quantization processing unit 1436 receives 8 * 8 pixel data of the V component after quantization from the entropy decoding unit, performs inverse quantization, obtains a DCT coefficient of 8 * 8 pixels of the V component, and performs a VIDCT processing unit 1437.

  The VIDCT processing unit 1437 receives the 8 * 8 pixel DCT coefficient of the V component from the inverse quantization processing unit, performs IDCT (Inverse Discrete Cosine Transform), and performs horizontal 8-pixel data of the V component of the currently processed line. Is transferred to the YUV-> RGB conversion unit 1438.

  The YUV-> RGB conversion processing unit 1438 converts the Y, U, and V pixel data from the IDCT processing units 1433, 1435, and 1437 into RGB.

  The macroblock count unit 1439 receives and counts the end signal of the macroblock line from the entropy decoding unit 1431, and generates a macroblock number being processed. When the horizontal macroblock number is counted, the initial value is restored.

  The macroblock line end determination unit 1440 detects the end of the macroblock line by counting the number of subblocks in the horizontal direction of the macroblock, and generates a macroblock end signal. When the end of the macroblock line of one macroblock is detected, the counter is reset to the initial value, and the end of the next macroblock line is detected.

  FIG. 63 is a detailed block diagram of the entropy decoding unit in the decoding processing unit according to the first modification. The read code register 14311 of the entropy decoding unit 143100 of the decoding processing unit 14300 of the page decoding unit 1444 temporarily stores the code data of the buffer 142 of FIG.

  The shifter 6301 shifts the variable length code by the shift value obtained by the shift value generation unit 14317, and transfers the variable length code to DC, the AC value decoding units 14314 and 14315, and the restart code determination unit 14313. .

  If the code from the shifter 14312 is a DC value code, the DC value decoding unit 14314 decodes the DC data, transfers it to the 8 * 8 DCT data generation unit 14318, and transfers the code length at that time to the MUX 14316 as the consumed code length. To do.

  If the code from the shifter 14312 is an AC value code, the AC value decoding unit 14315 decodes the AC data, transfers it to the 8 * 8 DCT data generation unit 14318, and transfers the code length at that time to the MUX 14316 as the consumed code length. To do.

  The MUX 6302 receives the consumed code length from the DC and AC value decoding units 14314 and 14315 and transfers the received code length to the shift value generation unit 6301.

  The shift value generation unit 14317 obtains the start address of the next code from the consumed code length from the MUX 6302 and controls the shifter 1431 so that the start of the code is always supplied to the DC and AC value decoding unit.

  The 8 * 8 DCT data generation unit 14318 generates 8 * 8 DCT data from the DC and AC values from the DC and AC value decoding units 14314 and 14315, and sends them to the inverse quantization units 1432, 1434, and 1436 in FIG. Forward.

  The above description has been focused on JPEG, but other variable-length coding schemes can be considered in the same way.

(3. Example of copier provided with image processing apparatus according to embodiment)
FIG. 64 is a diagram for explaining the internal mechanism of the copying machine including the image processing apparatus according to the embodiment of the present invention.

  A bundle of documents is placed on a document table 1002 in an automatic document feeder (hereinafter abbreviated as ADF) 1001 of the copying machine 1200 with the image side of the document facing up. When the start key on the operation unit is pressed, the lowermost document is fed to a predetermined position on the contact glass 1006 by the feeding roller 1003 and the feeding belt 1004. After the image data of the document on the contact glass 1006 is read by the reading unit 1050, the document that has been read is discharged by the feeding belt 1004 and the discharge roller 1005. Further, when it is detected by the document set detection 1007 that there is a next document on the document table 1002, it is fed onto the contact glass 1006 as in the case of the previous document. The feeding roller 1003, the feeding belt 1004, and the discharging roller 1005 are driven by a motor.

  Transfer sheets, which are recording media stacked on the first tray 1008 or the second tray 1009, are fed by the first paper feed unit 1011 or the second paper feed unit 1012 respectively, and are contacted with the photoconductor 1015 by the vertical transport unit 1014. It is transported to the contact position. Image data read by the reading unit 1050 is written on the photoconductor 1015 by a laser from the writing unit 1057, and a toner image is formed by passing through the developing unit 1027. The toner image on the photoconductor 1015 is transferred while the transfer paper is conveyed by the conveyance belt 1016 at the same speed as the rotation of the photoconductor 1015. Thereafter, the image is fixed by the fixing unit 1017 and discharged by the paper discharge unit 1018 to the finisher 1100 of the post-processing unit.

  The finisher 1100 of the post-processing unit can guide the transfer paper conveyed by the paper discharge roller 1019 of the main body in the normal paper discharge roller 1102 direction and the staple processing unit direction. By switching the switching plate 1101 upward, the sheet can be discharged to the normal discharge tray 1104 side via the transport roller 1103. Further, by switching the switching plate 1101 downward, the switching plate 1101 can be conveyed to the staple table 1108 via the conveying rollers 1105 and 1107.

  The transfer paper loaded on the stapling table 1108 is aligned by the paper aligning jogger 1109 every time one sheet is discharged, and is bound by the stapler 1106 upon completion of a partial copy. The group of transfer sheets bound by the stapler 1106 is stored in the staple completion discharge tray 1110 by its own weight.

  On the other hand, a normal paper discharge tray 1108 is a paper discharge tray that can move back and forth. The paper discharge tray unit 1108 that can be moved back and forth is a unit that moves back and forth for each original or each copy unit sorted by the image memory 4 and sorts the copy paper that is simply discharged.

  When images are formed on both sides of the transfer paper, the transfer paper fed from each of the paper feed trays 1008 and 1009 is not guided to the paper discharge tray side, and the branch claw 1112 for switching the path is set on the upper side. Is once stocked in the duplex feeding unit 1111. Thereafter, the transfer paper stocked on the double-sided paper feeding unit 1111 is re-fed from the double-sided paper feeding unit 1111 to transfer the toner image formed on the photoconductor 1015 again, and the branching claw 1112 for switching the path. Is set on the lower side and guided to the paper discharge tray 1104. In this way, the duplex feeding unit 1111 is used when images are created on both sides of the transfer sheet.

  The photoconductor 1015, the conveyance belt 1016, the fixing unit 1017, the paper discharge unit 1018, and the development unit 1027 are driven by a main motor, and the paper feed units 1011 and 1012 are each driven to transmit the drive of the main motor by a paper feed clutch. . The vertical conveyance unit 1014 is driven to transmit the drive of the main motor by an intermediate clutch. A reading unit (scanner) 1050 includes a contact glass 1006 on which an original is placed and an optical scanning system. The optical scanning system includes an exposure lamp 1051, a first mirror 1052, a lens 1053, a CCD image sensor 1054, and the like. Has been.

  Exposure lamp 1051 and first mirror 1052 are fixed on a first carriage (not shown), and second mirror 1055 and third mirror 1056 are fixed on a second carriage (not shown). When reading a document image, the first carriage and the second carriage are mechanically scanned at a relative speed of 2: 1 so that the optical path length does not change. This optical scanning system is driven by a scanner drive motor (not shown). The document image is read by the CCD image sensor 1054, converted into an electric signal (analog image signal), and then converted into digital data (image data). The image data is further subjected to several types of image processing.

  The image magnification is changed by moving the lens 1053 and the CCD image sensor 1054 in the horizontal direction in FIG. That is, the positions of the lens 1053 and the CCD image sensor 1054 are set in the left-right direction corresponding to the designated magnification. The writing unit 1057 includes a laser output unit 1058, an imaging lens 1059, and a mirror 1060. Inside the laser output unit 1058, a rotating polygon mirror (polygon) that rotates at a high speed at a high speed by a laser diode and a motor that are laser light sources. Mirror). Laser light emitted from the laser output unit 58 is polarized by a polygon mirror that rotates at a constant speed, passes through an imaging lens 1059, is folded by a mirror 1060, and is focused and imaged on the surface of the photoreceptor.

  The polarized laser light is exposed and scanned in a direction (main scanning direction) perpendicular to the direction in which the photosensitive member rotates, and recording is performed on a line basis of an image signal output from a selector 1064 of an image processing apparatus described later. An image (electrostatic latent image) is formed on the surface of the photosensitive member by repeating main scanning at a predetermined cycle corresponding to the rotational speed and recording density of the photosensitive member. As described above, the laser beam output from the writing unit 1057 is applied to the image forming photoconductor 1015. Although not shown, a beam sensor for generating a main scanning synchronization signal is disposed at a position near the photoconductor 1015 where the laser beam is irradiated. Based on the main scanning synchronization signal, control of image recording start timing in the main scanning direction and generation of a control signal for inputting / outputting image signals to be described later are performed.

(4. Hardware configuration and recording medium)
The image processing apparatus described above can be realized by executing a program prepared in advance on a computer system such as a personal computer or a workstation. The entire computer is controlled by a CPU (Central Processing Unit). A ROM (Read Only Memory), a RAM (Random Access Memory), a hard disk drive (HDD: Hard Disk Drive), a graphics processing device, and an input interface are connected to the CPU via a bus. The ROM and RAM store at least a part of an OS (Operating System) program and application programs to be executed by the CPU. The RAM stores various data necessary for processing by the CPU. The HDD stores an OS, various driver programs, application programs, detected data, and the like.

  An operation panel is connected to the graphic processing device. A keyboard of the operation panel is connected to the input interface. The processing function of the present embodiment can be realized by the hardware configuration which is a publicly-known technique as described above. In order to realize the present embodiment on a computer, a driver program is installed.

  The data synchronization program executed by the image processing apparatus according to the present embodiment is a file in an installable format or an executable format, and a computer-readable recording medium such as a CD-ROM, floppy (R) disk, or DVD. Recorded and provided.

  The image processing program of the present embodiment may be configured to be provided and distributed by storing it on a computer connected to a network such as the Internet and downloading it via the network.

(5. Effect)
As described in detail above, the present invention provides a macroblock head address storage unit for storing a code head address for each macroblock on the same horizontal line in the encoding unit, and a macroblock on the same horizontal line. A macroblock intermediate code storage unit for storing intermediate code data for each block is provided, the image from the scanner is subjected to a smoothing filter process, stored in a line memory of one block line, and thereafter each macroblock on the same horizontal line By encoding in parallel and storing in the main memory, no band memory in the vertical direction of the macroblock is required, and image composition processing and rotation processing are performed by the editing unit for the code data in macroblock units. When the data is encoded and stored again in the memory and then decoded by the decoding device, the same horizontal label is used. A macroblock head address storage section for storing the head address of the code for each macroblock on the screen and a macroblock intermediate code storage section for each macroblock on the same horizontal line are provided. In parallel, the image formation can be realized without the need for a band memory having a height in the vertical direction of the macroblock. In addition, high-speed editing processing can be performed, and a necessary amount of memory can be reduced.

  Further, the present invention temporarily stores a code obtained by encoding a plurality of macro block lines in a macro block unit in a multi-valued image, temporarily into an input / output code memory area, and then writes it to the HDD for writing to the HDD device. Since the memory for transfer is only one band code area, an increase in memory due to memory transfer to the HDD device can be reduced.

  Also, at the time of decoding, a macroblock head address storage unit that stores a code head address for each macroblock on the same horizontal line in the decoding unit, and intermediate decoded data for each macroblock on the same horizontal line A macroblock decoding shift value storage unit for storing macroblocks, decoding in parallel for each macroblock on the same horizontal line, and at least a macroblock vertical height band for transfer to the image processing apparatus in units of subblocks. Since no memory is required, the required amount of memory can be reduced with a simple configuration.

  In addition, the present invention temporarily stores a code obtained by encoding a plurality of macro block lines in a macro block unit in a multi-valued image in an input / output code memory area, and then combines it with a stamp image or the like by an editing device. By performing the rotation process in units of macroblocks and storing the page code in the page code memory area, it is possible to reduce an increase in memory due to the image rotation operation.

  In the present invention, when a multi-valued image is configured such that a code obtained by encoding a plurality of macroblock lines in units of macroblocks is temporarily stored in an input / output code memory area and then written to the HDD device. Since the memory for transfer to the HDD requires only one band code area, the increase in memory due to the memory transfer to the HDD device can be reduced.

  As described above, the image processing apparatus, the image processing method, and the program for executing the method on a computer according to the present invention are useful for a copying machine and are particularly suitable for a digital copying machine.

FIG. 2 is a functional block diagram of an image processing unit according to Embodiment 1 of the present invention. 2 is a hardware configuration diagram of the image processing apparatus according to Embodiment 1. FIG. 3 is a flowchart illustrating an overall flow of image formation by the image processing apparatus. FIG. 6 is a diagram for explaining a relationship between an overall flow of image forming processing according to the first embodiment and a memory. It is a schematic diagram which shows an example of the format of a main memory. It is a schematic diagram which shows an example of the format of the code memory for input / output. It is a schematic diagram which shows an example of the macroblock of a page code memory area. It is a figure explaining the flow of a scanner input, input data encoding, an edit process, and a page encoding process. It is a figure explaining the flow of a decoding process and a printing process. It is a figure explaining the flow of an encoding process and the storing to HDD. It is a figure explaining the flow of reading of the code data from HDD, an edit process, and a page encoding process. It is a figure explaining the flow of a scanner input and an encoding process. It is a figure explaining the flow of an edit process and a page encoding process. It is a figure explaining the flow of a page decoding process and print output. It is a figure explaining the flow of an encoding process, the storing to HDD, an edit process, and a page encoding process. 3 is a functional block diagram of an encoding unit of the image processing apparatus according to Embodiment 1. FIG. It is a flowchart explaining an encoding process procedure. It is a flowchart explaining an encoding process procedure. It is a schematic diagram which shows an example of 8 line memory format. It is a figure explaining the direction of the process of the subblock in a macroblock. It is a figure explaining an example of the encoding format of image data. 5 is a block diagram of an encoding processing unit in the encoding unit according to Embodiment 1. FIG. It is a detailed block diagram of an 8-line memory address generation unit. It is a schematic diagram which shows an example of MCU. It is a detailed block diagram of the entropy encoding part in an encoding process part. It is a figure explaining an AC encoding procedure. It is a figure explaining DC encoding procedure. It is a figure explaining DC / AC value cut-out processing. It is a figure explaining a DC value encoding part. It is a figure explaining an AC value encoding part. It is a detailed block diagram of the code format generation part in the encoding process part of an encoding part. It is a detailed functional block diagram of the macroblock code intermediate storage part in the encoding process part of an encoding part. It is a detailed block diagram of the macroblock head address memory | storage part of an encoding part. 3 is a functional block diagram of an editing unit of the image processing apparatus according to Embodiment 1. FIG. It is a schematic diagram which shows an example of the format of the synthetic | combination memory in an edit part. 6 is a flowchart illustrating an editing process procedure in the image processing apparatus according to the first embodiment. 6 is a flowchart illustrating an editing process procedure in the image processing apparatus according to the first embodiment. It is a figure explaining the read-out order of the data from a macroblock. It is a figure explaining the rotation process of a page level. It is a figure explaining the rotation process of a macroblock level. It is a figure explaining the rotation process of a subblock level. It is a figure explaining the rotation process of a subblock level. It is a functional block diagram of the decoding part in an edit part. It is a flowchart explaining the process sequence by the decoding process part in an edit part. It is a schematic diagram which shows the reading order of the data encoded for every macroblock, and the macroblock comprised from a subblock. It is a functional block diagram of the decoding process part in the decoding part of an edit part. It is a block diagram of the page encoding part in an edit part. It is a flowchart explaining the process sequence by a page encoding part. It is a figure explaining the processing order of the subblock in a macroblock. 3 is a detailed functional block diagram of a page decoding unit shown on page 2 of the image processing apparatus according to Embodiment 1. FIG. It is a flowchart explaining the page decoding process sequence in a page decoding part. It is a flowchart explaining the page decoding process sequence in a page decoding part. It is a schematic diagram which shows an example of 8 line memory format. It is a figure explaining the decoding order of the subblock which comprises a macroblock. It is a detailed block diagram of a decoding processing unit in the page decoding unit. It is a detailed block diagram of the entropy decoding part in a decoding process part. It is a detailed block diagram of the shift value generation part in an entropy decoding part. 47 is a detailed block diagram of a macroblock head address storage unit shown in FIG. 46 in the page decoding unit. FIG. FIG. 52 is a detailed block diagram of a macroblock decoded shift value storage unit in the shift value generation unit shown in FIG. 51. 2 is a functional block diagram of an image processing unit of the image processing apparatus according to Embodiment 1. FIG. It is a flowchart explaining the image processing procedure by an image processing part. It is a hardware block diagram of the image processing apparatus by the modification 1. It is a schematic diagram which shows the modification 1 of the macroblock code format in a page code memory area. 12 is a detailed block diagram of a page encoding unit in an editing unit according to Modification 1. FIG. 10 is a flowchart illustrating a processing procedure of a page encoding unit according to Modification 1. It is a figure explaining the order which reads a subblock in the macroblock by the modification 1, and performs a process. FIG. 11 is a detailed block diagram of a page decoding unit in an image processing apparatus according to Modification 1. 10 is a flowchart illustrating a processing procedure of a page decoding unit in an image processing apparatus according to Modification 1. 10 is a flowchart illustrating a processing procedure of a page decoding unit in an image processing apparatus according to Modification 1. It is a schematic diagram which shows an example of the 8-line memory format by the modification 1. It is a figure explaining the decoding order of the subblock which comprises the macroblock by the modification 1. FIG. 10 is a detailed block diagram of a decoding processing unit in an editing processing unit according to Modification 1. FIG. 10 is a detailed block diagram of an entropy decoding unit in a decoding processing unit according to Modification 1. 1 is a diagram illustrating an internal mechanism of a copying machine including an image processing apparatus according to an embodiment of the present invention. It is the figure which showed the algorithm of GBTC fixed length compression. It is the figure which showed the algorithm of GBTC fixed length compression. It is the figure which showed the algorithm of GBTC fixed length compression.

Explanation of symbols

1 CPU (central processing unit)
2 CPU I / F
3 Memory controller 4 Memory 5 Local bus I / F
6 ROM
7 Panel Controller 8 Panel 9 Scanner 10 Smoothing Filter Processing Unit 11 8 Line Memory 12 Encoding Unit 122 Encoding Processing Unit 123 Macroblock Head Address Storage Unit 124 Memory Address Generation Unit 125 Memory Controller I / F
126 Controller 1221 8 * 8 Buffer 1222 8-Line Memory Address Generation Unit 12221 Adder 12222 Register 12223 Multiplier 12224 Comparison Unit 12225 Adder 12226 Register 1223 RGB-> YUV Conversion Unit 1224 YDCT Processing Unit 1225 Y Quantization Processing Unit 1226 Y Entropy Encoding unit 1227 UDCT processing unit 1228 U quantization processing unit 1229 U entropy encoding unit 1233 Code format generation unit 1234 Macroblock code intermediate data storage unit 1240 VDCT processing unit 1241 V quantization processing unit 1242 V entropy encoding unit 13, 1300 Editing unit 1303 Decoding unit 13031 Decoding processing unit 1306, 13060 Page encoding unit 1302 Buffer 1303 Decoding unit 130 1 decoding unit 13032 reads the memory address generation unit (macro block code address recognition unit)
13033 Macroblock head address storage unit 1304 8 * 8 rotation processing unit 13041 Entropy decoding unit 13042 Y inverse quantization processing unit 13044 U inverse quantization processing unit 1305 Buffer 1306 Page encoding unit 13061 8 * 8 buffer 13073 Restart marker generation Part 1308 image composition part 1309 composition memory I / F
1311 Code length count unit 1313 Memory address generation unit 14, 1400 page decoding unit 143, 14300 Decoding processing unit 1431, 143100 Entropy decoding unit 14317 Shift value generation unit 143172 Macroblock decoding shift value storage unit 1432 Y inverse quantization Processing Unit 1434 U Inverse Quantization Processing Unit 1436 V Inverse Quantization Processing Unit 144 Read Memory Address Generation Unit 145 Macroblock Head Address Storage Unit 15 Image Processing Unit 16 Engine Controller 17 Printer Engine 18 HDD Control Unit 19 HDD
30 Operation panel 1200 Copier

Claims (14)

An image processing apparatus that performs variable length coding on input image data, edits, decodes, performs image processing, and outputs image data after image processing,
Editing designation means for accepting designation of editing processing content for the input image data;
Multi-value block line data storage means for storing the input image data as multi-value sub-block unit line data constituting a macroblock;
Macroblock variable length encoding means for reading the multilevel block line data from the multilevel block line data storage means and performing variable length encoding on a macroblock basis;
Macroblock head address storage means for storing the head address of the macroblock on the same horizontal line in which the macroblocks are arranged in an image during variable length coding by the macroblock variable length coding means;
Macroblock code intermediate data storage means for storing intermediate data of variable length coding processing of the macroblock for variable length coding on the same horizontal line during variable length coding by the macroblock variable length coding means When,
Macroblock code storage means for sequentially storing variable length code data generated by the macroblock variable length encoding means in units of macroblocks;
Macroblock code address recognition means for recognizing the head address of each block stored in the macroblock head address storage means corresponding to the variable length code data of the macroblock unit stored in the macroblock code storage means;
The variable length code data stored in the macroblock code storage means is read and decoded according to the head address of each block recognized by the macroblock code address recognition means in accordance with the editing processing content designated by the edit designation means. Editing means for editing,
An image processing apparatus comprising: An image processing device that inputs image data that is variable-length-coded in units of macroblocks composed of sub-blocks, edits, decodes, and outputs the processed image,
Editing designation means for accepting designation of editing processing content for the input image data;
Macroblock code storage means for storing the variable-length code data in units of macroblocks;
In accordance with the editing processing content designated by the edit designating means, the variable length code data stored in the macroblock code storage means is read, decoded, edited, variable length coded again, and the macroblock code storage means Editing means to send to
Macroblock code address recognition means for recognizing the address of each macroblock corresponding to the variable length code data stored in the macroblock code storage means;
Macroblock decoding means for receiving the start address of the macroblock from the macroblock code address storage means, reading the variable length code data of the macroblock edited by the editing means from the macroblock code storage means, and sequentially decoding the data When,
Macroblock start address storage means for storing the start address of the macroblock of the same horizontal line stored in the macroblock code storage means upon decoding by the macroblock decoding means;
Macroblock decoding intermediate data storage means for storing data in the middle of decoding the macroblock to be processed on the same horizontal line upon decoding by the macroblock decoding means;
Image processing means for receiving image data of at least the sub-block unit stored in the macroblock decoding intermediate data storage means and performing image processing;
Image output means for sequentially transferring the image data after image processing generated by the image processing means to the printer engine in the main scanning direction of the image;
An image processing apparatus comprising:   2. The image processing apparatus according to claim 1, wherein the macroblock code address recognizing means includes code length calculating means for calculating a total code length generated in a macroblock composed of a plurality of sub-blocks. . The macroblock code address recognition means includes:
4. The image processing apparatus according to claim 3, further comprising an address calculation unit that calculates an address of the macroblock code storage unit from the code length generated by the code length total calculation unit. The editing means includes
The image processing apparatus according to claim 1, further comprising a macroblock expansion storage unit that decodes and expands the image data of the macroblock.   6. The image processing apparatus according to claim 5, wherein the editing means includes image composition processing means for performing composition processing on an image stored in the macroblock development storage means. The editing means includes
The image processing apparatus includes a rotation processing unit that rotates the image data stored in the macroblock development storage unit in units of 90 degrees for each subblock according to the editing content designated by the editing designation unit. The image processing apparatus according to claim 5. The macroblock variable length encoding means includes:
2. The image processing apparatus according to claim 1, further comprising image block line end detection means for detecting the end of one block line in the horizontal direction of the image data in units of macroblocks. The image block line end detection means comprises:
9. The image processing apparatus according to claim 8, further comprising restart marker insertion means for inserting a restart marker at the end of one block line in the horizontal direction of the image data in units of macroblocks. The macroblock decoding means includes:
Code block line end detection means for detecting the end of one block line in the horizontal direction of the variable length code data stored by the macroblock code storage means;
3. The variable length code data stored in the macroblock code storage means is read and decoded using the termination detected by the code block line end detection means. The image processing apparatus described. The code block line end detection means comprises:
11. The image according to claim 10, further comprising restart marker detection means for detecting a restart marker at the end of one block line in a horizontal direction for reading a code stored by the macroblock code storage means. Processing equipment. An image processing apparatus that performs variable length coding on input image data, edits, decodes, performs image processing, and outputs image data after image processing,
Edit specification means for accepting specification of edit processing contents;
Multi-value block line data storage means for storing one-line data in units of multi-value sub-blocks;
First macroblock variable length encoding means for generating a code of a plurality of macroblock units from the multi-value block line data storage means;
First macroblock code storage means for sequentially storing a plurality of macroblock variable length code data generated by the first macroblock variable length encoding means;
First macroblock code address recognition means for recognizing an address at which each macroblock is stored for variable length code data stored in the first macroblock code storage means;
In accordance with the editing processing content designated by the editing designation means, the address that the first macroblock code address recognition means recognizes the variable length code data stored in the first macroblock code storage means. Editing means for reading using, decoding and editing; second macroblock variable length encoding means for variable length encoding the image data edited by the editing means in units of macroblocks;
Second macroblock code storage means for sequentially storing the variable length code data generated by the second macroblock variable length encoding means in units of macroblocks;
Second macroblock code address recognizing means for recognizing an address at which each macroblock is stored for variable length code data stored in the second macroblock code storage means;
Macroblock decoding means for receiving the start address of the macroblock from the second macroblock code address storage means, reading the variable length code data of the macroblock from the second macroblock code storage means, and sequentially decoding the data. When,
Output multi-value block line data storage means for storing the multi-value block line data decoded by the macroblock decoding means;
Image processing means for receiving image data in units of sub-blocks stored in the output multi-value block line data storage means and performing image processing;
Image output means for sequentially transferring the image data after the image processing generated by the image processing means to the printer engine in the main scanning direction of the image;
An image processing apparatus comprising: An image processing method for performing variable length encoding, editing and decoding input image data, performing image processing, and outputting image data after image processing,
An edit designation step for accepting designation of edit processing content for the input image data;
A multi-value block line data storage step of storing the input image data as line data in units of multi-value sub-blocks constituting a macroblock;
A macroblock variable length encoding step of reading the multilevel block line data stored in the multilevel block line data storage step and performing variable length encoding on a macroblock basis;
A macroblock head address storing step for storing a head address of the macroblock on the same horizontal line in which the macroblocks are arranged in an image during variable length coding in the macroblock variable length coding step;
A macroblock code storage step of sequentially storing the variable length code data generated in the macroblock variable length encoding step in units of the macroblock;
In accordance with the editing processing content specified in the editing specification step, the editing step of reading the variable length code data stored in the macroblock code storage step, decoding and editing,
A macroblock decoding step of reading the macroblock head address stored in the macroblock head code address storing step, reading the code data of the macroblock stored in the macroblock code storing step, and sequentially decoding the data; ,
An output multi-value block line data storing step for storing data decoded in the macroblock decoding step;
An image processing step for receiving image data in units of sub-blocks stored in the output multi-value block line data storage step, and performing image processing;
An image output step of sequentially transferring the image data after the image processing generated by the image processing step to the printer engine in the main scanning direction of the image;
An image processing method comprising:   A program for executing the image processing method according to claim 13 on a computer.

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