JP2005181751A - Display element driving device and display device equipped with the display element driving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display element driving device capable of changing γ correction characteristics corresponding to digital gradation display data and a display device equipped with the display element driving device. <P>SOLUTION: A liquid crystal driving circuit is equipped with a D/A converting circuit 36 which generates a gradation display driving voltage to be subjected to γ correction according to the digital gradation display data. The D/A converting circuit 36 is equipped with a DAC circuit 50 which generates the gradation display driving voltage to be subjected to γ correction from display analog voltages of voltage kinds in one group corresponding to digital gradation display data, and a storage circuit 40 for setting the gradation display driving voltage to be subjected to γ correction from the display analog voltages of voltage kinds in one group by corresponding to the digital gradation display data. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a display element driving apparatus for driving a display element such as a liquid crystal display element, and a display apparatus including the display element driving apparatus, and in particular, a gray scale display reference voltage generating circuit used for a liquid crystal driving apparatus. About.

  A gradation display reference voltage generating circuit used in a liquid crystal driving device for driving a liquid crystal display element as a display element is a circuit that generates an intermediate voltage between two voltages. For example, in a liquid crystal driving unit in an active matrix liquid crystal display device, an intermediate voltage is generated using resistance division. The resistance dividing resistor has a resistance ratio called γ correction, and the optical characteristics of the liquid crystal material are corrected according to the ratio of the resistance ratio to realize a more natural gradation display. ing. That is, since the gradation value and the display voltage corresponding to the gradation are not necessarily in a linear relationship, γ correction is necessary.

  The following is a configuration of a liquid crystal display device including the gradation display reference voltage generation circuit, a configuration of an active matrix TFT (Thin Film Transistor) type liquid crystal panel in the liquid crystal display device, a liquid crystal driving waveform thereof, and The configuration of the source driver will be described.

  As shown in FIG. 21, the configuration of the active matrix type liquid crystal display device 110 is divided into a liquid crystal display portion 110a and a liquid crystal driving circuit 110b as a liquid crystal driving device for driving the liquid crystal display portion 110a.

  The liquid crystal display unit 110a includes a TFT (Thin Film Transistor) type liquid crystal panel 101. On the other hand, the liquid crystal driving circuit 110b is equipped with a source driver 103 and a gate driver 104 made of an IC (integrated circuit), a controller 105, and a liquid crystal driving power source 106.

  In the above configuration, display data input from the outside is input to the source driver 103 as display data D that is a digital signal via the controller 105. The source driver 103 time-divides the input display data D and latches it in the first source driver to the n-th source driver, and then performs D / A conversion in synchronization with the horizontal synchronizing signal input from the controller 105. . Then, an analog voltage for gradation display (hereinafter referred to as “gradation display voltage”) formed by D / A converting the time-division display data D is supplied to the liquid crystal panel 101 via a source signal line (not shown). Output to the corresponding liquid crystal display element.

  On the other hand, as shown in FIG. 22, the liquid crystal panel 101 includes a pixel electrode 111, a pixel capacitor 112, a TFT 113 for controlling on / off of voltage application to the pixel electrode 111, a source signal line 114, a gate signal line 115, and A counter electrode 102 is provided. Here, the pixel electrode 111, the pixel capacitor 112, and the TFT 113 constitute the liquid crystal display element A for one pixel.

  The grayscale display voltage corresponding to the brightness of the display target pixel is applied to the source signal line 114 from the source driver 103 shown in FIG. On the other hand, the gate signal line 115 is supplied with a scanning signal from the gate driver 104 that sequentially turns on the TFTs 113 arranged in the column direction. Then, the gradation display voltage of the source signal line 114 is applied to the pixel electrode 111 connected to the drain of the TFT 113 through the TFT 113 in the on state, and is accumulated in the pixel capacitor 112 between the counter electrode 102 and the pixel electrode 111. . In this way, the light transmittance of the liquid crystal is changed according to the gradation display voltage, and pixel display is performed.

  Next, the nth source driver constituting the source driver 103 will be described with reference to FIG.

  In the n-th source driver 130, the input digital signal display data D includes R (red), G (green), and B (blue) display data (DR, DG, and DB). Then, the display data D is once latched in the input latch circuit 131, and then, in accordance with the operation of the shift register circuit 132 that shifts by the start pulse SP and the clock CK from the controller 105, the sampling memory circuit 133 is time-divided. Is remembered. Thereafter, the data are collectively transferred to the hold memory circuit 134 based on a horizontal synchronization signal (not shown) from the controller 105. S is a cascade output.

  The gradation display reference voltage generation circuit 139 generates a reference voltage of each level based on a voltage VR supplied from an external reference voltage generation circuit (corresponding to the liquid crystal driving power source 106 in FIG. 21). The data in the hold memory circuit 134 is sent to the D / A conversion circuit 136 via the level shifter circuit 135, and is converted into an analog voltage based on the reference voltage of each level. Then, the output circuit 137 outputs the gradation display voltage from the liquid crystal drive voltage output terminal 138 to the source signal line 114 of each liquid crystal display element A. That is, the number of levels of the reference voltage is the number of gradations that can be displayed.

  FIG. 24 shows a configuration of a gradation display reference voltage generation circuit 139 that generates a plurality of reference voltages as described above to generate an intermediate voltage. The gradation display reference voltage generation circuit 139 generates 64 reference voltages.

  This gradation display reference voltage generation circuit 139 has nine halftone voltage input terminals represented by V0, V8, V16, V24, V32, V40, V48, V56 and V64, and a resistance ratio for γ correction. And a total of 64 resistors (not shown) connected in series between both ends of each of the resistor elements R0 to R7. In this manner, a resistance ratio called γ correction is built in the source driver 103 so that the liquid crystal drive output voltage for conversion to the gradation display voltage has a polygonal line characteristic. Therefore, by correcting the optical characteristics of the liquid crystal material based on the ratio of the resistance ratios, it is possible to perform natural gradation display that matches the optical characteristics of the liquid crystal material. FIG. 25 shows a characteristic example of the γ-corrected liquid crystal drive output voltage in the conventional gradation display reference voltage generation circuit 139.

  In the conventional gradation display reference voltage generation circuit 139, the optimum γ correction characteristic represented by the broken line characteristic of the liquid crystal drive output voltage shown in FIG. 25 differs depending on the type of liquid crystal material and the number of pixels of the liquid crystal panel. Different for each LCD module. The resistance division ratio of the gradation display reference voltage generation circuit 139 built in the source driver 103 is determined at the design stage of the source driver 103. Therefore, there is a problem that the source driver 103 must be remade each time the γ correction characteristics are changed according to the type of liquid crystal material of the liquid crystal module to be applied and the number of pixels of the liquid crystal panel.

  For this reason, Patent Literature 1 and Patent Literature 2 have proposed a gradation display reference voltage generation circuit capable of changing the γ correction characteristics in accordance with the characteristics of the liquid crystal material and the liquid crystal panel.

For example, in Patent Document 1, the divided resistance ratio can be changed by connecting a prepared resistor with a switch. Further, in Patent Document 2, a divided resistance ratio can be changed by using a γ correction circuit using a constant current circuit for gradation voltages divided by resistors.
JP 2001-13478 A (published January 19, 2001) JP 2001-166751 A (released on June 22, 2001) "Basics of Analog IC (146, 147 pages)" by Yoshio Shirato, published by the Tokyo Denki University Press (published March 30, 1981, first edition, first edition, February 25, 1993, published second edition, first edition)

  However, the conventional display element driving device and the method of γ correction in the display device including the display element driving device finely adjust the voltages divided by the resistors, respectively, and thus exceed the voltage value divided in advance. The problem that all adjustments cannot be made occurs.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a display element driving device capable of changing γ correction characteristics corresponding to digital gradation display data, and the display element driving device. It is to provide a display device provided.

  In order to solve the above-described problems, a display element driving apparatus according to the present invention includes a display element driving device including a digital-analog conversion unit that generates a gradation display driving voltage that is γ-corrected according to digital gradation display data. In the apparatus, the digital-to-analog converting means is a grayscale display driving voltage that is γ-corrected from analog voltages for display of a group of voltage types greater than the number of gray levels constituting the digital gray scale display data. And a gray scale display driving voltage to be γ-corrected from among the analog voltages for display of the group of voltage types corresponding to the digital gray scale display data. And a γ correction voltage setting means.

  According to the above invention, the extended gradation voltage generating means generates the gradation display drive voltage from the display analog voltages of one group of voltage types that are larger than the number of gradations. Then, the γ correction voltage setting means sets the gradation display drive voltage to be γ corrected from among the display analog voltages of a group of voltage types larger than the number of gradations.

  Therefore, the relationship between the input digital gradation display data and the gradation display drive voltage to be γ-corrected is not fixed and can be changed by the setting of the γ-correction voltage setting means.

  As a result, it is possible to provide a display element driving device capable of changing the γ correction characteristic corresponding to digital gradation display data.

  The display element driving device according to the present invention is the display element driving device described above, wherein a voltage type of a group of display analog voltages in the extended gradation voltage generating means is a gradation constituting the gradation display data. It is characterized by being at least twice the number.

  According to the above invention, the voltage type of the group of display analog voltages in the extended gradation voltage generating means is at least twice the number of gradations constituting the gradation display data. A desired gradation display drive voltage can be selected from a group of display analog voltage types that are at least twice as many as the number of gradations to be configured.

  In the display element driving device according to the present invention, in the display element driving device described above, the γ correction voltage setting unit stores the combination pattern of the gradation display driving voltages to be γ corrected as binary data. A storage means is provided.

  According to the above invention, the combination pattern of the drive voltage for gradation display subjected to γ correction is stored in the storage unit. Since this storage circuit stores binary data, the change is easy.

  The display element driving apparatus of the present invention is characterized in that, in the display element driving apparatus described above, the storage means can change the combination pattern of the driving voltages for gradation display to be γ-corrected. Yes.

  According to the above invention, the storage means can change the combination pattern of the gradation display drive voltage to be subjected to the γ correction, so that the γ correction characteristic corresponding to the digital gradation display data is surely obtained. A display element driving device that can be changed can be provided.

  The display element driving apparatus according to the present invention is the display element driving apparatus described above, wherein the storage means converts the digital gradation display data into a digital signal having a number of bits larger than the number of bits constituting the gradation display data. It has a bit conversion means for converting into data.

  According to the above invention, in the storage means, the bit conversion means converts the digital gradation display data into digital data having a number of bits larger than the number of bits constituting the gradation display data.

  Therefore, the bit data can be easily changed to digital data having a larger number of bits than the number of bits constituting the gradation display data.

  According to the display element driving device of the present invention, in the display element driving device described above, the bit conversion unit is configured to add digital gradation display data to a bit that is two bits larger than the number of bits constituting the gradation display data. And a selection circuit for converting the bit into the selection circuit and an output circuit for outputting a bit less than the bit of the selection circuit by one bit from the bit of the selection circuit.

  According to the above invention, the selection circuit for converting the digital gradation display data into two bits larger than the number of bits constituting the gradation display data, and the bit of the selection circuit from the bit of the selection circuit More specifically, it is possible to easily change the digital data with a bit number larger than the number of bits constituting the gradation display data by the bit data by the output circuit that outputs one bit less than the number of bits.

  In the display element driving apparatus according to the present invention, in the display element driving apparatus described above, the extended gradation voltage generating means is a digital / analog conversion circuit using a ladder circuit in which a resistor R and a resistor 2R are combined. It is characterized by that.

  According to the above-described invention, the display element drive capable of changing the γ correction characteristic corresponding to the digital gradation display data with a simple configuration by the digital / analog conversion circuit by the ladder circuit combining the resistor R and the resistor 2R. An apparatus can be provided.

  The display element driving apparatus of the present invention is the display element driving apparatus described above, wherein the storage unit stores in advance a plurality of combinations of gradation display driving voltages to be γ-corrected. The stored γ-corrected combination display pattern of gradation display drive voltages is switchable.

  According to the above invention, the storage means stores in advance a plurality of combination patterns of the gradation display drive voltage to be γ-corrected. These combination patterns can be switched.

  Therefore, it is possible to provide a display element driving device capable of easily changing the γ correction characteristics corresponding to digital gradation display data by switching a combination pattern of a plurality of gradation display driving voltages subjected to γ correction. it can.

  The display element driving apparatus of the present invention is the display element driving apparatus described above, wherein the combination pattern of the plurality of previously stored γ-corrected gradation display driving voltages is used when liquid crystal alternating current driving is performed. It is characterized by being switched according to positive voltage application and negative voltage application.

  According to the above-described invention, a plurality of previously stored combination patterns of γ-corrected grayscale display driving voltages are switched according to positive voltage application and negative voltage application when performing liquid crystal AC drive.

  Therefore, it is possible to provide a display element driving device that can easily change the γ correction characteristic corresponding to digital gradation display data in accordance with positive voltage application and negative voltage application even in liquid crystal AC drive. .

  The display element driving apparatus of the present invention is the display element driving apparatus described above, wherein a plurality of combinations of the extended gradation voltage generating means and the γ correction voltage setting means are provided, and these are time-division driven. Thus, the number of source signal lines is larger than the number of the above combinations.

  According to the above invention, the digital-analog conversion means is provided with a plurality of combinations of the extended gradation voltage generation means and the γ correction voltage setting means. These are time-division driven to output to more source signal lines than the number of combinations.

  That is, a combination of the extended gradation voltage generation means and the γ correction voltage setting means is shared and time-division driving is performed. As a result, the circuit scale can be reduced.

  Further, in order to solve the above problems, a display device of the present invention is characterized by including the above-described display element driving device.

  According to the above invention, since the display device includes the above-described display element driving device, it is possible to provide a display device that can change the γ correction characteristic corresponding to digital gradation display data.

  In the display element driving device of the present invention and the display device provided with the display element driving device, the digital-analog converting means has a group of voltage types greater than the number of gradations constituting the digital gradation display data. Extended gradation voltage generating means for generating a gradation display drive voltage that is γ-corrected from among the display analog voltages, and display analogs for the group of voltage types corresponding to the digital gradation display data. Γ correction voltage setting means for setting a gradation display drive voltage to be γ corrected from the voltages.

  Therefore, the relationship between the input digital gradation display data and the gradation display drive voltage to be γ-corrected is not fixed and can be changed by the setting of the γ-correction voltage setting means.

  As a result, it is possible to provide a display element driving device capable of changing the γ correction characteristic corresponding to digital gradation display data.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIGS. 1 to 14 as follows.

  As shown in FIG. 10, the configuration of the liquid crystal display device 10 as an active matrix type display device according to the present embodiment is divided into a liquid crystal display unit 10a and a liquid crystal drive circuit 10b as a liquid crystal drive device for driving the liquid crystal display unit 10a. .

  The liquid crystal display unit 10 a includes a TFT (Thin Film Transistor) type liquid crystal panel 1. In the liquid crystal panel 1, a liquid crystal display element (not shown) and a counter electrode 2 which is a common electrode described in detail later are provided.

  On the other hand, the liquid crystal driving circuit 10b is equipped with a source driver 3 and a gate driver 4, which are ICs (integrated circuits), a controller 5, and a liquid crystal driving power source 6. The controller 5 inputs display data D and the control signal S1 to the source driver 3, and inputs a vertical synchronization signal S2 to the gate driver 4. Further, a horizontal synchronization signal is input to the source driver 3 and the gate driver 4.

  In the above configuration, display data input from the outside is input to the source driver 3 through the controller 5 as display data D that is a digital signal. The source driver 3 time-divides the input display data D and latches it in the first source driver to the n-th source driver, and then performs D / A conversion in synchronization with the horizontal synchronizing signal input from the controller 5. . Then, an analog voltage for gradation display (hereinafter referred to as “gradation display voltage”) formed by D / A converting the time-division display data D is supplied to the liquid crystal panel 1 via a source signal line (not shown). Output to the corresponding liquid crystal display element.

  On the other hand, the liquid crystal panel 1 includes, as shown in FIG. 11, a pixel electrode 11, a pixel capacitor 12, a TFT 13 for controlling on / off of voltage application to the pixel electrode 11, a source signal line 14, a gate signal line 15, and A counter electrode 2 is provided. Here, the liquid crystal display element A for one pixel is constituted by the pixel electrode 11, the pixel capacitor 12 and the TFT 13.

  The source signal line 14 is supplied with the gradation display voltage corresponding to the brightness of the display target pixel from the source driver 3 shown in FIG. On the other hand, the gate signal line 15 is supplied with a scanning signal for sequentially turning on the TFTs 13 arranged in the column direction from the gate driver 4. Then, the gradation display voltage of the source signal line 14 is applied to the pixel electrode 11 connected to the drain of the TFT 13 through the TFT 13 in the on state, and is accumulated in the pixel capacitor 12 between the counter electrode 2. . In this way, the light transmittance of the liquid crystal is changed according to the gradation display voltage, and pixel display is performed.

  12 and 13 show examples of liquid crystal driving waveforms. 12 and 13, reference numerals 21 and 25 denote driving waveforms of the source driver 3, and reference numerals 22 and 26 denote driving waveforms of the gate driver 4. Reference numerals 23 and 27 denote potentials of the counter electrode 2, and reference numerals 24 and 28 denote voltage waveforms of the pixel electrode 11. Here, the voltage applied to the liquid crystal material is a potential difference between the pixel electrode 11 and the counter electrode 2 and is indicated by hatching in the drawing.

  For example, in the case of FIG. 12, the TFT 13 is turned on only when the level of the drive waveform 22 of the gate driver 4 is “H”, and the voltage of the difference between the drive waveform 21 of the source driver 3 and the potential 23 of the counter electrode 2 is Applied to the pixel electrode 11. Thereafter, the level of the drive waveform 22 of the gate driver 4 becomes “L”, and the TFT 13 is turned off. In that case, since the pixel capacitance 12 exists in the pixel, the above-described voltage is maintained.

  The same applies to the case of FIG. However, FIG. 12 and FIG. 13 show the case where the voltage applied to the liquid crystal material is different, and the applied voltage is higher in the case of FIG. 12 than in the case of FIG. In this way, by changing the voltage applied to the liquid crystal material as an analog voltage, the light transmittance of the liquid crystal is changed in an analog manner to realize multi-gradation display. Note that the number of gradations that can be displayed is determined by the number of analog voltage options applied to the liquid crystal material.

  Next, the nth source driver constituting the source driver 3 will be described.

  As shown in FIG. 14, the n-th source driver 30 includes an input latch circuit 31, a shift register circuit 32, a sampling memory circuit 33, a hold memory circuit 34, a level shifter circuit 35, a D / A conversion circuit (digital / analog conversion circuit). 36 and an output circuit 37.

  In the n-th source driver 30, the input digital signal display data D includes R (red), G (green), and B (blue) display data (DR, DG, and DB). The display data D is once latched in the input latch circuit 31, and then the sampling memory circuit 33 is time-divided in accordance with the operation of the shift register circuit 32 that shifts from the controller 5 by the start pulse SP and the clock CK. Is remembered. After that, the data is transferred to the hold memory circuit 34 based on a horizontal synchronization signal (not shown) from the controller 5. S is a cascade output.

  The data in the hold memory circuit 34 is sent to the D / A conversion circuit 36 through the level shifter circuit 35, and is converted into an analog voltage based on the reference voltage of each level. Then, the output circuit 37 outputs the gradation display voltage from the liquid crystal drive voltage output terminal 38 to the source signal line 14 of each liquid crystal display element A. That is, the number of levels of the reference voltage is the number of gradations that can be displayed.

  Here, the D / A conversion circuit 36 of the present embodiment will be described in detail.

  The D / A conversion circuit 36 of this embodiment has the functions of the gradation display reference voltage generation circuit 139 and the D / A conversion circuit 136 described in [Background Art]. Therefore, the D / A conversion circuit 36 generates a reference voltage of each level based on the voltage VR supplied from the liquid crystal drive power supply 6 shown in FIG. 10 which is an external reference voltage generation circuit. For this reason, in this embodiment, since the D / A conversion circuit 36 is also provided with the reference voltage generating means, the gradation display reference voltage generating circuit 139 described in [Background Art] is eliminated.

  As shown in FIG. 1, the D / A conversion circuit 36 of the present embodiment having the above functions includes a storage circuit 40 as a γ correction voltage setting unit and a storage unit, and a DAC circuit 50 as an extended gradation voltage generation unit. It is made up of. The memory circuit 40 is provided with input terminals D0 and D1, and signals inputted to these input terminals D0 and D1 correspond to output signals from the level shifter circuit 35 shown in FIG. Further, the output voltage Vout of the DAC circuit 50 corresponds to the output voltage from the D / A conversion circuit 36 shown in FIG.

  In the D / A conversion circuit 36, a combination pattern of analog voltage values to be γ-corrected is set from a group of display analog voltages in correspondence with digital gradation display data.

  In order to simplify the description, in the present embodiment, a case will be described in which a γ correction curve is created by selecting four gradation voltages from eight gradation voltages by 2-bit input. In actual use, the number of gradations is increased so that a fine voltage can be set. For example, a correction curve is created by selecting 256 voltages from 1024 gradation voltages using an 8-bit input.

  In the present embodiment, as shown in the truth table 1 shown in FIG. 2A, binary 2-bit gradation display data input values D0 and D1 indicating gradation values 0, 1, 2, and 3 are given. In this case, the output voltage Vout shown in FIG. 3 is output. For example, an output voltage Vout of (1/8) Vdd is output at a gradation value of 0, and an output voltage Vout as a gradation display drive voltage of (4/8) Vdd is output at a gradation value of 1. In the gradation value 2, the output voltage Vout of (5/8) Vdd is output, and in the gradation value 4, the output voltage Vout of (6/8) Vdd is output. Each output voltage Vout pattern represents one of the combination patterns of analog voltage values to be γ-corrected. Then, as shown in FIG. 2B, such a combination pattern of analog voltage values to be γ-corrected is 2 in order with respect to eight types of output voltages Vout obtained by equally dividing the voltage value Vdd into eight. “000” to “111” are added in the three decimal bits, and by selecting one of them, the corresponding output voltage Vout is output. For example, with a gradation value of 1, if “100” of binary 3 bits is selected, the output voltage Vout of (4/8) Vdd is output.

  Conversely, when it is desired to output the output voltage Vout of (3/8) Vdd as an analog voltage value obtained by correcting the gradation value 1 by γ correction, “011” is used in binary 3 bits “D2 ′, D1 ′, D0 ′”. Can be easily changed to the output voltage Vout of the above (3/8) Vdd.

  That is, in this embodiment, as shown in the truth table 1 of FIG. 2A, the binary 2-bit gradation display data input values D0 and D1 indicating the gradation values 0, 1, 2, and 3 are When given, this value is set to “D2 ′, D1 ′, D0 ′”, and selection logic trial values A, B, and B for selecting “001”, “100”, “101”, “111” CD is used. In this embodiment, the selection logic trial values A, B, C, and D are binary four bits “1000”, “0100”, “0010”, and “0001”. For this reason, by changing the setting of the selection logic trial values A, B, C, and D, each value of the binary 3 bits “D2 ′, D1 ′, D0 ′” can be changed and the output voltage Vout can be easily changed. can do.

  Specifically, the memory circuit 40 that performs the above function includes a selection circuit 41 and a truth value output circuit 45 as output means, as shown in FIG. The selection circuit 41 is a circuit that obtains four selection logic trial values A, B, C, and D in the truth table 1 shown in FIG. 2A based on the values of two inputs D0 and D1. The selection circuit 41 includes, for example, an AND circuit 42 and a NOT circuit 43 as shown in FIG.

  That is, in the selection circuit 41, for example, when two inputs D0 = 0 and input D1 = 0 are input, in the output of the selection logic trial value A, any value is passed through the NOT circuits 43 and 43 and the AND circuit. 42, the output (1, 1) of the NOT circuits 43 and 43 is obtained, and the output “1” is extracted from the output of the AND circuit 42 by the logical product. In the output of the selection logic trial value B, the input D0 = 0 is directly input to the AND circuit 42, and the input D1 = 0 is input to the AND circuit 42 through the NOT circuit 43. As an output, an output “0” is extracted by the logical product. Further, in the output of the selection logic trial value C, the input D0 = 0 is input to the AND circuit 42 through the NOT circuit 43, and the input D1 = 0 is directly input to the AND circuit 42. As an output, an output “0” is extracted by the logical product. In the output of the selection logic trial value D, since both values of the two inputs D0 = 0 and D1 = 0 are directly input to the AND circuit 42, the output of the AND circuit 42 is output "0" by the logical product. Is extracted.

  On the other hand, as shown in FIG. 4, the truth value output circuit 45 in the memory circuit 40 is a 4 × 3 matrix circuit, and the output of each selected logic trial value A, B, C, and D is three. Are connected to the gates of any one of the transistors TRa and TRb. The transistor TRa is a normal Nch transistor, and when the gate signal becomes “1”, the source and drain become conductive. On the other hand, the transistor TRb has the same structure as the transistor TRb, but the transistor TRb does not always conduct between the source and the drain regardless of whether the gate voltage application is “1” or “0”. The transistors TRa and TRb can be divided in the transistor manufacturing process. For example, in the PN process of the transistor, the transistor TRa can be made separately with PN and the transistor TRb can be made without PN. This sorting can be changed depending on how to make a mask used for manufacturing. Similarly, a transistor that normally operates and a transistor that does not operate can be separately formed by using a mask in another process. Thus, data can be stored in advance by making the transistors TRa and TRb separately. Such a memory circuit 40 is a circuit generally called a mask ROM.

  In the truth value output circuit 45, after the line of binary 3 bits “D2 ′, D1 ′, D0 ′” is set to Vdd “1” by the transistor TRc which is a Pch transistor, the selection logic is examined by the inputs D0 and D1. One of the values A, B, C, and D becomes “1”, and the transistors TRa and TRb connected to the line that has become “1” are selected. For example, when the selection logic trial value A is selected, the binary 3-bit “D0 ′” line becomes Vdd “1” because the transistor TRb is not conductive. Since the transistor TRa is connected to the binary 3-bit “D2 ′, D1 ′” line, the line becomes conductive when the gate voltage becomes “1”, and becomes GND “0”.

  Similarly, when the selection logic trial value B is selected, binary 3 bits D0 '= 0, binary 3 bits D1' = 1, binary 3 bits D2 '= 1. In this way, it can be set in advance so that 3-bit data is output to the selection signal by 2 bits.

  As shown in this example, this setting can be performed not only by using a ROM (Read Only Memory) but also by an electrically rewritable EEPROM (Electrically Erasable Programmable ROM) or RAM (Random Access Memory).

  On the other hand, the DAC circuit 50 of the D / A conversion circuit 36 is generally called a DAC (D / A converter) by an R-2RDAC circuit or a ladder circuit. That is, the DAC circuit 50 connects a plurality of resistors R... Between the output voltage Vout and the ground and the resistor 2R closest to the ground, while branching the resistors 2R from the resistors R. In this case, binary three bits “D2 ′, D1 ′, D0 ′” are output to the branched one. For example, if the binary 3 bits “D2 ′, D1 ′, D0 ′” are “0, 0, 1”, (1/8) Vdd can be obtained. The description of the DAC circuit 50 is shown in, for example, Non-Patent Document 1, and will not be described in detail. However, the value of the binary 3 bits “D2 ′, D1 ′, D0 ′” is shown in FIG. The relationship shown in Truth Table 2 shown in FIG. Note that the power supply voltage is Vdd.

  In this way, four levels of voltage can be arbitrarily selected from eight gradation voltages according to the contents of the memory circuit 40, that is, ROM data. Therefore, in addition to the correction curve of the graph shown in FIG. 3, for example, the truth table 3-2 shown in FIGS. 6 (a) and 6 (b) and the graph shown in FIG. The opposite inclination curve, or the polygonal line such as the truth table 4 • 2 shown in FIGS. 6A and 6B and the graph shown in FIG. 9 can be selected. It should be noted that the polygonal lines such as the truth tables 4 and 2 shown in FIGS. 8A and 8B and the graph shown in FIG. 9 are merely examples of selections. In actual γ correction, There is no such choice.

  As a result, means for increasing the number of bits of the gradation data is arranged between the gradation data and the DA converter that converts the gradation data into analog data, and data for γ correction is added to the increased bits.

  Then, by using a rewritable storage means as the means for increasing the bits, the γ curve can be easily changed.

  That is, it is possible to select a preset gradation voltage from among the voltages generated by the multi-gradation D / A conversion circuit 36 and arbitrarily set the gradation voltage correction in the gradation data.

  As described above, in the liquid crystal driving circuit 10b of the present embodiment, the DAC circuit 50 generates the output voltage Vout from the display analog voltage of one group of voltage types that is larger than the number of gradations. Then, the memory circuit 40 sets the output voltage Vout that is γ-corrected from among the display analog voltages of a group of voltage types that are larger than the number of gradations.

  Therefore, the relationship between the input digital gradation display data and the gradation display drive voltage to be γ-corrected is not fixed and can be changed by the setting of the γ-correction voltage setting means.

  As a result, it is possible to provide the liquid crystal drive circuit 10b that can change the γ correction characteristic corresponding to the digital gradation display data.

  Further, in the liquid crystal drive circuit 10b of the present embodiment, the voltage type of the group of display analog voltages in the DAC circuit 50 is at least twice the number of gradations constituting the gradation display data. A desired gradation display drive voltage can be selected from a voltage type of a group of display analog voltages that is at least twice the number of gradations constituting the gradation display data.

  Further, in the liquid crystal drive circuit 10 b of the present embodiment, the combination pattern of the gradation display drive voltages to be γ-corrected is stored in the storage circuit 40. Since the storage circuit 40 stores binary data, the change is easy.

  Further, in the liquid crystal drive circuit 10b of the present embodiment, the storage circuit 40 can change the combination pattern of the gradation display drive voltage to be γ-corrected. A liquid crystal driving circuit 10b that can change the corresponding γ correction characteristic can be provided.

  Further, in the liquid crystal driving circuit 10b of the present embodiment, the storage circuit 40 as the bit converting means converts the digital gradation display data into digital data having a number of bits larger than the number of bits constituting the gradation display data. Convert.

  Therefore, the bit data can be easily changed to digital data having a larger number of bits than the number of bits constituting the gradation display data.

  Further, in the liquid crystal driving circuit 10b of the present embodiment, a selection circuit 41 that converts digital gradation display data into bits that are two bits larger than the number of bits constituting the gradation display data, and the selection circuit 41 More specifically, a bit larger than the number of bits constituting the gradation display data can be easily obtained from the bit data by the truth value output circuit 45 that outputs one bit less than the bit of the selection circuit 41. It can be changed to a number of digital data.

  Further, in the liquid crystal drive circuit 10b of the present embodiment, the DAC circuit 50 includes a digital / analog conversion circuit that is a ladder circuit in which a resistor R and a resistor 2R are combined.

  Therefore, it is possible to provide a liquid crystal driving circuit 10b that can change the γ correction characteristic corresponding to digital gradation display data with a simple configuration by a digital / analog conversion circuit using a ladder circuit combining a resistor R and a resistor 2R. Can do.

In addition, since the liquid crystal display device of this embodiment includes the liquid crystal driving circuit 10b, it is possible to provide a display device that can change γ correction characteristics corresponding to digital gradation display data.
[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. Configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanation thereof is omitted.

  As shown in FIG. 15, the liquid crystal drive circuit 10b of the present embodiment is a 4 × 3 × 2 bit storage circuit 60 in which two 4 × 3 bit storage circuits 40 shown in FIG. 1 are prepared. As shown in FIGS. 16A and 16B, the specific configuration of 4 × 3 bits includes storage circuits 60a and 60b, and there are two storage circuits 40 shown in FIG. However, the selection circuit 41 is provided only in the memory circuit 60b.

  As described above, since there are two 4 × 3 bit storage circuits 40, two types of patterns for selecting four voltages from eight gradation voltages can be prepared. In this embodiment, the storage circuit 60 is switched by the S signal shown in FIG. With this S signal, even when the inputs D0 and D1 are the same data, the selected voltage can be different.

  As shown in FIGS. 17 (a) and 17 (b), an example of voltage selection is shown in truth table 5-2. Thereby, when the S signal is 0 and 1, as shown in the graph of FIG. 18, for example, a completely opposite voltage can be selected.

  This setting example shows that alternating current for liquid crystal driving can be simplified. Since the display data (D0, D1) are the same and the opposite voltage can be applied to the liquid crystal, the liquid crystal drive can be switched to AC only by switching the S signal.

  Furthermore, at this time, by changing the setting of the storage circuit 60, it is possible to easily change the curve of γ correction in the AC conversion. That is, in the liquid crystal AC drive, the γ correction characteristic corresponding to the digital gradation display data is changed according to the positive voltage application and the negative voltage application.

  In this embodiment, the storage circuit 60 using two 4 × 3 bit storage circuits 40 is described. However, the present invention is not limited to this, and an arbitrary gradation can be obtained by increasing the number of bits and the selection signal. Correspondence to voltage and gradation pattern is possible.

  For example, it is possible to change the pattern of the γ correction curve according to the data to be displayed, or to reduce power consumption by reducing the number of gradations depending on the display state (for example, when waiting for a mobile phone).

  Further, by storing a plurality of γ curve data in the storage circuit 60 and selecting the γ curve data by the selection signal, the γ curve can be changed even during the operation of the driver. Further, since this changing means has no voltage value divided in advance, it is possible to freely adjust the γ correction.

  As described above, in the liquid crystal drive circuit 10b of the present embodiment, the storage circuit 60 as the storage unit stores a plurality of combination patterns of gradation display drive voltages to be γ-corrected in advance. These combination patterns can be switched.

  Therefore, it is possible to provide the liquid crystal drive circuit 10b that can easily change the γ correction characteristics corresponding to digital gradation display data by switching a combination pattern of a plurality of gradation display drive voltages subjected to γ correction. it can.

  Further, in the liquid crystal drive circuit 10b of the present embodiment, a plurality of previously stored combination patterns of γ-corrected grayscale display drive voltages are applied to positive voltage application and negative voltage application when performing liquid crystal AC drive. It is possible to switch according to.

  Therefore, it is possible to provide the liquid crystal driving circuit 10b that can easily change the γ correction characteristic corresponding to the digital gradation display data in accordance with the application of the positive voltage and the application of the negative voltage even in the liquid crystal AC driving. .

In addition, since the liquid crystal display device of this embodiment includes the liquid crystal driving circuit 10b, it is possible to provide a display device that can change γ correction characteristics corresponding to digital gradation display data.
[Embodiment 3]
The following will describe still another embodiment of the present invention with reference to FIGS. The configurations other than those described in the present embodiment are the same as those in the first embodiment and the second embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiment 1 and Embodiment 2 are given the same reference numerals, and explanation thereof is omitted.

  In the liquid crystal drive circuit 10b shown in the first and second embodiments, the D / A conversion circuit 36 shown in FIGS. 1 and 15 has one D / A conversion signal for each source signal line 14 of a liquid crystal pixel. Although a circuit is provided (see FIG. 14), the D / A conversion circuit 36 is shared by performing time division driving in order to reduce the D / A conversion circuit 36. Is possible.

  That is, as shown in FIG. 14, when the n-th source driver 30 latches with the latch signal LS corresponding to one horizontal synchronization period, the DA converted drive voltage continues to output the drive voltage during one horizontal period.

  On the other hand, instead of continuously outputting to each source signal line 14 during one horizontal synchronization period, for example, as shown in FIGS. 19A and 19B, the level shifter circuit 35 and the D / A conversion circuit The selector circuit 71 is provided between the input 36 and the selector circuit 72 between the output of the D / A conversion circuit 36 and the output circuit 37. Further, the D / A conversion circuit 36 of FIG. 1 is replaced with, for example, a D / A conversion circuit 70 provided with 10 circuits, and the level shifter circuit 35 related to the output terminals 01 to 010 in a predetermined period T1 within one horizontal synchronization period, as shown in FIG. The D / A conversion circuit 36 and the output circuit 37 are connected by selector circuits 71 and 72. First, the signal is output to the source signal line 14 of the liquid crystal panel 1, and then the selector circuits 71 and 72 are switched in a period T2, and output is performed at outputs 011 to 020, as shown in FIG. Within one horizontal synchronization period, time division is performed with T1, T2, T3, T4,.

  If the selector circuits 71 and 72 are turned off (when not selected), the output voltage Vout of the non-selected output circuit with a small capacitance or stray capacitance is maintained in the input stage of the output circuit 37 if the impedance is set to high impedance. it can. In this way, the circuit of FIG. 1 can be shared, and the circuit scale can be reduced. In FIG. 19A, “circuit of FIG. 1” is described, but the circuit of FIG. 15 may be used.

  As described above, in the liquid crystal drive circuit 10b of the present embodiment, the D / A conversion circuit 70 as the digital-analog conversion means includes a plurality of D / A conversion circuits 36 in which the storage circuit 40 and the DAC circuit 50 are combined. Are provided. These are time-division driven to output to the source signal lines 14 that are larger than the number of the combined D / A conversion circuits 36.

  That is, the D / A conversion circuit 36 in which the memory circuit 40 and the DAC circuit 50 are combined is shared and time-division driven. As a result, the circuit scale can be reduced.

  In addition, since the liquid crystal display device of this embodiment includes the liquid crystal driving circuit 10b, it is possible to provide a display device that can change γ correction characteristics corresponding to digital gradation display data.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the technical means disclosed in different embodiments can be appropriately combined. Such embodiments are also included in the technical scope of the present invention.

  The display element driving device of the present invention and the display device including the display element driving device can be applied to, for example, an active matrix liquid crystal display device using a liquid crystal element as a display element and a source driver thereof.

  Further, the display device is not limited to a liquid crystal display device including a liquid crystal display element, but includes an optical modulation element such as an electrophoretic display, a twist ball display, a reflective display using a fine prism film, and a digital mirror device. In addition to the used display, as a light emitting element, an organic EL light emitting element, an inorganic EL light emitting element, a display using a variable light emitting element such as an LED (Light Emitting Diode), a field emission display (FED), and a plasma display Can be used.

1 is a block diagram illustrating a configuration of a D / A conversion circuit according to an embodiment of a display element driving device according to the present invention. (A) (b) is explanatory drawing which shows the memory | storage circuit in the said D / A conversion circuit with a truth table. It is a graph which shows the pattern of (gamma) correction voltage obtained by the truth table shown to Fig.2 (a) (b). It is a block diagram which shows the structure of the memory circuit in the said D / A conversion circuit in detail. FIG. 3 is a circuit diagram illustrating a configuration of a selection circuit in the memory circuit. (A) (b) is explanatory drawing which shows the truth table for obtaining the pattern of another (gamma) correction voltage in the said D / A converter circuit. It is a graph which shows the pattern of (gamma) correction voltage obtained by the truth table shown to Fig.6 (a) (b). (A) (b) is explanatory drawing which shows the truth table for obtaining the pattern of another (gamma) correction voltage in the said D / A conversion circuit. It is a graph which shows the pattern of (gamma) correction voltage obtained by the truth table shown to Fig.8 (a) (b). It is a block diagram which shows the structure of the liquid crystal display device of the active matrix TFT system which mounts the said display element drive device. It is a block diagram which shows the structure of the pixel of the said liquid crystal display device. FIG. 5 is a waveform diagram showing a voltage applied to a pixel when the level of a driving waveform of a gate driver is “H” in the liquid crystal display device. In the liquid crystal display device, it is a waveform diagram showing the voltage applied to the pixel when the level of the driving waveform of the gate driver is “L”. It is a block diagram which shows the structure of the nth source driver in the said liquid crystal display device. The other embodiment of the display element drive device in this invention is shown, and it is a block diagram which shows the structure of a D / A conversion circuit. (A) and (b) are block diagrams showing in detail the configuration of the memory circuit in the D / A conversion circuit. (A) (b) is explanatory drawing which shows the memory | storage circuit in the said D / A conversion circuit with a truth table. It is a graph which shows the pattern of (gamma) correction voltage obtained by the truth table shown to Fig.17 (a) (b). (A) is a block diagram showing the configuration of a shared D / A converter circuit, showing still another embodiment of the display element driving device of the present invention, and (b) is an ASW (analogue). 2 is a circuit diagram showing a configuration of a switch. It is explanatory drawing which shows the said D / A conversion circuit with a truth table. It is a block diagram which shows the structure of the conventional liquid crystal display device of an active matrix TFT system. It is a block diagram which shows the structure of the pixel of the said liquid crystal display device. It is a block diagram which shows the structure of the nth source driver in the said liquid crystal display device. It is a circuit diagram which shows the structure of the gradation display reference voltage generation circuit of the said nth source driver. It is a graph which shows the gamma correction voltage setting state obtained by the said nth source driver.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal panel 3 Source driver 4 Gate driver 5 Controller 10 Liquid crystal display device (display device)
10a Liquid crystal display unit 10b Liquid crystal driving circuit (liquid crystal driving device)
11 Pixel electrode 12 Pixel capacity 13 TFT
14 source signal line 15 gate signal line 31 input latch circuit 32 shift register circuit 33 sampling memory circuit 34 hold memory circuit 35 level shifter circuit 36 D / A conversion circuit 37 output circuit 40 storage circuit (γ correction voltage setting means)
41 selection circuit 42 AND circuit 43 NOT circuit 50 DAC circuit (extended gradation voltage generation means, storage means)
60 Memory circuit (γ correction voltage setting means)
D0 Input terminal D1 Input terminal Vout Output voltage

Claims (11)

In a display element driving device including digital-analog converting means for generating a gradation display driving voltage that is γ-corrected according to digital gradation display data,
The digital-analog conversion means is:
Extended gradation voltage generating means for generating a gradation display drive voltage for γ correction from a group of display analog voltages of a group of voltage types larger than the number of gradations constituting the digital gradation display data;
Γ correction voltage setting means for setting a gradation display drive voltage to be γ corrected from the display analog voltages of the group of voltage types in correspondence with the digital gradation display data. A display element driving device.   2. The display element according to claim 1, wherein a voltage type of a group of display analog voltages in the extended gradation voltage generation means is at least twice the number of gradations constituting the gradation display data. Drive device.   3. The display element according to claim 1, wherein the γ correction voltage setting means includes storage means for storing a combination pattern of the gradation display driving voltages subjected to γ correction as binary data. Drive device.   4. The display element driving apparatus according to claim 3, wherein the storage means is capable of changing a combination pattern of the gradation display driving voltages subjected to the γ correction.   2. The storage means comprises bit conversion means for converting digital gradation display data into digital data having a bit number larger than the number of bits constituting the gradation display data. The display element drive device of any one of -4. The bit conversion means includes
A selection circuit for converting the digital gradation display data into 2 bits more than the number of bits constituting the gradation display data;
6. The display element driving device according to claim 5, further comprising: an output circuit that outputs a bit that is one bit less than the bit of the selection circuit.   2. The display element driving device according to claim 1, wherein the extended gradation voltage generating means comprises a digital / analog conversion circuit using a ladder circuit in which a resistor R and a resistor 2R are combined. The storage means stores in advance a plurality of combination patterns of gradation display drive voltages to be γ-corrected,
3. The display element driving apparatus according to claim 1, wherein the plurality of previously stored combination patterns of gradation display driving voltages subjected to γ correction are switchable.   The combination pattern of the plurality of previously stored γ-corrected gradation display drive voltages stored in advance is switched according to a positive voltage application and a negative voltage application when performing liquid crystal AC drive. 9. The display element driving device according to 8.   A plurality of combinations of the extended gradation voltage generation means and the γ correction voltage setting means are provided, and these are time-division driven to output more source signal lines than the number of combinations. The display element driving device according to claim 1.   A display device comprising the display element driving device according to claim 1.

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