JP2005181061A - Electronic circuit and its test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic circuit and its test method capable of debugging easily flip-flop circuits during circuit operation by operating only a small group of flip-flop circuits, while keeping the states of other flip-flop circuits operated by a common clock, as they are. <P>SOLUTION: A logic sum circuit is arranged on a synchronous circuit, to thereby enable supplying of both the common clock and a debugging clock, and the common clock is suspended and the debugging clock is supplied to a desired flip-flop circuit, to thereby execute debugging operation, while keeping the state of the flip-flop circuits having no relation to debugging. Even when the debugging clock is supplied to all the flip-flop circuits, the original state can be kept by storing outputted information. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electronic circuit that operates in synchronization with a common clock.

  In recent years, a device called a system-on-chip in which a complex and large-scale electronic circuit is configured in a semiconductor element has become widespread. The semiconductor device 1 includes a large-scale circuit such as a central control unit 2 (CPU), a storage unit 3 (MEMORY), a digital signal processing unit 4 (DPS), and a USER LOGIC 5, as shown in FIG. The electronic circuit formed in the semiconductor device 1 is synchronously designed by an automatic synthesis tool in consideration of a scan test or the like.

  FIG. 8 shows a configuration example of a part of the USER LOGIC 5 which is a complete synchronization circuit. The flip-flop circuit (FF) 10 is connected to the data bus (CPU bus 11) of the CPU 2, and the CPU 2 can read the value. A flip-flop circuit 9 for retiming the CPU read signal (RD) is connected to the flip-flop circuit 10. A common clock (CLK) is supplied to each of the two flip-flop circuits 10 and 9 and another flip-flop circuit 8 not connected to the CPU bus 11. When a flip-flop circuit exists in the logic circuits 12, 13, and 14 connected to the flip-flop circuit, the same clock (CLK) is also supplied to the flip-flop circuit.

  On the other hand, it is difficult to test a complicated and large-scale synchronous circuit as described above. Various methods have been proposed as a method of testing the synchronous circuit in which a flip-flop circuit is incorporated in a logic circuit (see, for example, Patent Document 1).

JP 2001-108727 A (FIGS. 1 and 2)

  In such verification of the synchronous circuit, a common clock is operated to check whether the circuit operates in accordance with the purpose. When operation different from the purpose occurs, it is necessary to confirm which part in the circuit is different from the specification. In debugging such a circuit, when it is desired to read the contents of the flip-flop circuit 10 in a certain state, it is necessary to perform a read operation in consideration of the number of clocks necessary for reading in advance. However, when the common clock 5 is operated to read the value of the flip-flop circuit 10, the state of another flip-flop circuit 8 also changes. That is, there is a problem that the entire circuit advances by performing the debugging operation, and the circuit state becomes different. Only the flip-flop circuit to be debugged cannot be operated individually. Further, the flip-flop circuit 8 that is not connected to the CPU bus has a problem that there is no debugging method such as confirming a halfway state or setting a certain value.

  In order to solve the above problems, the present invention makes it possible to easily debug a flip-flop circuit in the middle of a circuit operation by operating only some of the flip-flop circuits while maintaining the state of other flip-flop circuits operating with a common clock. Provided is an electronic circuit that can perform the same and a test method thereof.

  An electronic circuit of the present invention is an electronic circuit that includes a plurality of flip-flop circuits and operates in synchronization with a common clock, and outputs a logical sum of a common clock and a debug clock, a control signal, and a logic A first flip-flop circuit that operates in synchronization with a debug clock output from the sum circuit is provided. When the control signal is a read signal output from the second flip-flop circuit that operates in synchronization with the debug clock, information held by the first flip-flop circuit is read out. When the control signal is a write signal output from the third flip-flop circuit that operates in synchronization with the debug clock, information is written into the first flip-flop circuit. Reading and writing of such information is performed via a CPU bus connected to the first flip-flop circuit. The electronic circuit can include a fourth flip-flop circuit that receives only a common clock, or a fifth flip-flop circuit that receives a debug clock from an OR circuit. A test bus can be connected to the fifth flip-flop circuit. The electronic circuit can also include a selector for selecting the input from the test bus to the fifth flip-flop circuit and other inputs based on the debug signal. A memory circuit that holds information output from the fifth flip-flop circuit and outputs the information in synchronization with a debug clock based on a debug signal may be provided.

  On the other hand, the electronic circuit test method of the present invention is directed to an electronic circuit having a plurality of flip-flop circuits and operating in synchronization with a common clock, and a first step of stopping supply of the common clock during operation of the electronic circuit And a second step of operating the specific flip-flop circuit by supplying a debug clock and a control signal synchronized with the debug clock to the specific flip-flop circuit. When the control signal is a read signal, information held in the specific flip-flop circuit is read. When the control signal is a write signal, information is written to the specific flip-flop circuit. A step of resuming the supply of the common clock can be provided. In the second step, a flip-flop circuit different from the specific flip-flop circuit may include a step of outputting information held in synchronization with the debug clock. In addition, a step of inputting information to a flip-flop circuit different from the specific flip-flop circuit in synchronization with a debug clock can be provided.

  According to the electronic circuit and the test method thereof of the present invention, it is possible to debug a specific flip-flop circuit while saving the contents of other flip-flop circuits during the synchronization operation of the electronic circuit. Also, when debugging is desired from the middle of circuit operation, it is not necessary to operate the circuit from the beginning to advance the circuit to a desired state, and to reduce the time required for debugging by returning the stored value. Is possible.

  In the example of the electronic circuit shown in FIG. 1, a common clock (CLK) and a debugging clock (DCLK) are input to the OR circuit 16. The logical sum output is supplied to the flip-flop circuits 9 and 10, respectively. One flip-flop circuit 9 is a CPU timing signal (RD) retiming circuit. The other flip-flop circuit 10 is connected to the logic circuit 14, and information is read according to the retimed read signal. The read information is output to the CPU bus 11. The common clock (CLK) is input to the synchronous circuit including the flip-flop circuit 8 before the OR circuit 16. The flip-flop circuit 8 is connected to the logic circuits 12 and 13.

  FIG. 2 shows an example of a clock in the electronic circuit. The OR circuit 16 can output a logical sum of the common clock (CLK) and the debug clock (DCLK). This logical output is supplied to flip-flop circuits 9 and 10. Only the common clock (CLK) is supplied to the other flip-flop circuits 8.

  When the common clock 5 in operation is stopped in the test of the electronic circuit, the flip-flop circuit 8, which is not related to CPU reading, maintains the state when the clock is stopped. At this time, a debug clock (DCLK) is supplied to the OR circuit 16. The flip-flop circuits 9 and 10 are operated by the debug clock (DCLK), and the contents of the flip-flop circuit 10 are output to the CPU bus 11 and read out. As described above, all the flip-flop circuits that operate synchronously with the supply of the common clock but are not related to CPU reading can maintain the state when the common clock is stopped. Therefore, the flip-flop circuit 10 can be debugged during the operation. After debugging, the operation of the electronic circuit can be started again from the state where the common clock is stopped.

  FIG. 3 shows another example of the electronic circuit of the present invention. This electronic circuit has substantially the same configuration as that of FIG. 1, but all flip-flop circuits operate in response to the output of the OR circuit 16. Accordingly, when the common clock 5 is stopped and the debug clock (DCLK) is supplied from the OR circuit 16, the flip-flop circuit 8 not related to the CPU reading outputs the contents to the connected test bus 17. . The operations of the flip-flop circuits 9 and 10 are the same as described above.

  FIG. 4 further shows another example of the electronic circuit of the present invention. The configuration is almost the same as the configuration of FIG. Here, the flip-flop circuit 19 is a CPU write signal (WR) retiming circuit. The other flip-flop circuit 20 is connected to the CPU bus 11 and information supplied from the CPU bus 11 is written in accordance with the retimed write signal (WR). Again, when the common clock is stopped, the flip-flop circuit 8 unrelated to writing maintains the state at that time.

  FIG. 5 shows another configuration example of the electronic circuit of the present invention. Here, the output of the OR circuit 16 is supplied to all flip-flop circuits. Information is written into the flip-flop circuit 20 from the CPU bus 11. However, information can also be written to the flip-flop circuit 8 that is not connected to the CPU bus 11. That is, a selector (SEL) 23 is connected to the flip-flop circuit 8. The selector 23 is connected to a logic circuit 12 that supplies information to the flip-flop circuit 8 and a test bus 21 during normal operation. In response to the DEBAG signal (DEBAG-1), the selector 23 connects either of them to the flip-flop circuit 8. For example, information output from the test bus 21 when the DEBAG signal is “1” is input to the flip-flop circuit 8. As a result, during debugging, the common clock (CLK) is stopped, the debugging clock (DCLK) is supplied, and various values can be set in the flip-flop circuit 8. In debugging, it is possible to shorten the debugging time by omitting the operation of the electronic circuit until the operation is confirmed and setting the circuit state to the state to be debugged.

  FIG. 6 shows an example of the memory circuit 25 that holds information output from the flip-flop circuit 8 to the test bus 17. In this example, the memory circuit 25 includes a flip-flop circuit 24, but other memory elements are possible. The flip-flop circuit 24 enables the debug signal (DEBAG-2), and the output information to the test bus 17 as shown in FIG. 3 is output by the debug clock (DCLK) to the test bus 21 shown in FIG. Can be output as information. The test buses 17 and 20 can be the same bus. By using the CPU read and CPU write using these configurations and the debug clock, it is possible to return to the state when the values of the respective flip-flop circuits are stored. For this reason, when debugging, the time required to advance the circuit from the initial state to this state can be saved.

  The debugging operation requires a control unit for controlling this. The control unit can be formed on a semiconductor chip on which the above-described synchronization circuit is arranged. Alternatively, a control unit can be provided separately, and a test can be performed by connecting to a semiconductor chip during the test.

  A plurality of the various flip-flop circuits described above can be arranged. The selector 23 or the test bus 17 or both can be arranged in all the flip-flop circuits 8 not connected to the CPU bus.

1 is a block diagram illustrating a configuration example of an electronic circuit of the present invention. The figure which shows the example of the clock applied to the electronic circuit shown by FIG. The block diagram which shows the other structural example of the electronic circuit of this invention. The block diagram which shows the further another structural example of the electronic circuit of this invention. The block diagram which shows the further another structural example of the electronic circuit of this invention. FIG. 11 is a block diagram illustrating a configuration example of a memory circuit applied to an electronic circuit of the present invention. The block diagram of the example of basic composition to a system on chip. The block diagram which shows the structural example of the electronic circuit which performs the conventional synchronous operation | movement.

Explanation of symbols

8, 9, 10 Flip-flop circuit 11 CPU bus 12, 13, 14, 15 Logic circuit 17, 21 Test bus 19, 20 Logic circuit

Claims (16)

An electronic circuit having a plurality of flip-flop circuits and operating in synchronization with a common clock, the logical sum circuit outputting a logical sum of the common clock and the debug clock, and the debug output from the control signal and the logical sum circuit An electronic circuit comprising a first flip-flop circuit that operates in synchronization with a general clock. 2. The electronic circuit according to claim 1, wherein the control signal is a read signal output from a second flip-flop circuit that operates in synchronization with the debug clock, and information held in the first flip-flop circuit is read out. The electronic circuit according to claim 2, wherein the information is output to a CPU bus connected to the first flip-flop circuit. 2. The electronic circuit according to claim 1, wherein the control signal is a write signal output from a third flip-flop circuit that operates in synchronization with the debug clock, and information is written to the first flip-flop circuit. 5. The electronic circuit according to claim 4, wherein the information is input from a CPU bus connected to the first flip-flop circuit. 6. The electronic circuit according to claim 1, further comprising a fourth flip-flop circuit that receives only the common clock. 6. The electronic circuit according to claim 1, further comprising a fifth flip-flop circuit that receives a debug clock from the OR circuit. 8. The electronic circuit according to claim 7, wherein a test bus is connected to the fifth flip-flop circuit. 9. The electronic circuit according to claim 7, further comprising a selector that selects an input from the test bus and other inputs to the fifth flip-flop circuit based on a debug signal. The electronic circuit according to claim 9, further comprising a storage circuit that holds information output from the fifth flip-flop circuit and outputs the information in synchronization with the debug clock based on a debug signal. A test method for an electronic circuit having a plurality of flip-flop circuits and operating in synchronization with a common clock,
A first step of stopping the supply of the common clock during operation of the electronic circuit;
A second step of supplying a debug clock and a control signal synchronized with the debug clock to a specific flip-flop circuit, and operating the specific flip-flop circuit;
A test method for an electronic circuit comprising: 12. The method of testing an electronic circuit according to claim 11, wherein the control signal is a read signal, and information held in the specific flip-flop circuit is read. 12. The method of testing an electronic circuit according to claim 11, wherein the control signal is a write signal, and information is written to the specific flip-flop circuit. 12. The method of testing an electronic circuit according to claim 11, further comprising the step of restarting the supply of the common clock. 13. The method of testing an electronic circuit according to claim 11 or 12, wherein in the second step, a flip-flop circuit different from the specific flip-flop circuit outputs information held in synchronization with a debug clock. . 14. The electronic circuit test method according to claim 11, further comprising a step of inputting information to a flip-flop circuit different from the specific flip-flop circuit in synchronization with a debug clock.

Images