JP2005176225A - Signal correcting apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a duty of an output signal of a data slicer is distorted and abnormality occurs in bit synchronism that is detected in a bit synchronizing circuit, if a time constant of the data slicer changes. <P>SOLUTION: A signal width acquisition section 12 acquires, as a signal width, a length of a term wherein a signal level of an input signal 100 is fixed, and a signal width history management section 13 manages a history of the signal width. A determination section 15 determines based on the acquired signal width and the history of the signal width whether or not correction is to be performed. If the correction is determined to be performed, the determination section 15 outputs a correcting instruction 105 just for a time of a correction amount 204 outputted from a correction amount management section 24. While the correcting instruction 105 is outputted, a correction performance section 16 corrects a delay input signal 101 outputted from a delay section 11. Thus, correction can be properly performed at high speed by deciding whether or not correction is to be performed based on the history of the signal width. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a signal correction apparatus, and more particularly to a signal correction apparatus that changes a change timing of a signal that is output from a data slicer or the like and changes to a rectangular shape.

  A receiver used in a digital radio communication system is equipped with a demodulator for reproducing the transmitted digital data based on the modulated analog signal. FIG. 6 is a block diagram showing a configuration of a conventional FSK (Frequency Shift Keying) demodulator. The FSK demodulator includes a reception front end unit 1, an IF (Intermediate Frequency) filter 2, an FM demodulator 3, a baseband filter 4, a data slicer 5, and a bit synchronization circuit 6.

  An RF (Radio Frequency) signal received by an antenna (not shown) or the like is input to the FSK demodulator shown in FIG. The input RF signal is first converted into an IF signal (intermediate frequency signal) by the reception front end unit 1. This IF signal is filtered by the IF filter 2 and further converted into an analog baseband signal by the FM demodulator 3. The analog baseband signal is subjected to band limitation by the baseband filter 4, and then converted to a binary signal that changes into a rectangular shape by the data slicer 5. The bit synchronization circuit 6 detects bit synchronization from the output signal of the data slicer 5 and reproduces original digital data transmitted from the transmitter using the detected bit synchronization.

  The data slicer 5 converts the FM demodulated analog baseband signal into a signal (a binary signal) that takes two kinds of values, a high level and a low level. More specifically, the data slicer 5 has a threshold value called a slicing level, and the output signal of the data slicer 5 is set to a high level according to the comparison result between the output signal of the baseband filter 4 and the slicing level. Or switch to low level.

  In order to simplify the configuration of the data slicer 5, it is preferable to fix the slicing level to a certain value. However, the DC level at the output end of the FM demodulator 3 is affected by a frequency shift caused by receiving a transmission signal from an unspecified transmitter, fluctuation due to drift, and the like. For this reason, a practical demodulator cannot fix the slicing level to a certain value. Therefore, the data slicer 5 needs to change the slicing level to an optimal value according to the state of the received signal.

  FIG. 7 is a circuit diagram showing an example of a detailed configuration of the data slicer 5. This data slicer is a commonly used RC integration type application data slicer, and includes a comparator 7, a resistor 8, and a capacitor 9. The resistor 8 and the capacitor 9 constitute an RC integrating circuit. The analog baseband signal output from the baseband filter 4 is input to the input terminal IN. The RC integration circuit obtains an average DC voltage of the analog baseband signal input from the input terminal IN. The obtained average DC voltage is used as a slicing level in the comparator 7. The comparator 7 compares the analog baseband signal output from the baseband filter 4 with the slicing level, and outputs a value “1” when the former is larger and a value “0” when the latter is larger.

  In the demodulator shown in FIG. 6, in order to maintain a good bit error rate (hereinafter referred to as BER) of the output signal, the data slicer 5 matches the original data transmitted as accurately as possible. Therefore, it is necessary to convert an analog signal into a binary signal. For example, when the duty of the output signal of the data slicer 5 is disturbed, an abnormality occurs in the bit synchronization detected by the bit synchronization circuit 6, and the BER of the output signal deteriorates. Therefore, in order to prevent the slicing level from deviating from the average DC voltage of the analog baseband signal, it is necessary to increase (enlarge) the time constant of the RC integration circuit included in the data slicer 5.

  However, on the other hand, the time constant of the RC integration circuit cannot be made sufficiently heavy in a wireless communication system that transmits and receives packets with short time slots, such as Bluetooth (R). This is because the slicing level in the data slicer 5 is adjusted during reception of a preamble or the like. However, in a wireless communication system that transmits and receives packets with short time slots, the preamble itself is short and the slicing level needs to be adjusted in a short time. Because there is. For this reason, the time constant of the RC integration circuit included in the data slicer 5 must be lightened (smaller). However, if the time constant of the RC integration circuit is reduced, as described above, the duty of the output signal of the data slicer 5 is disturbed, the bit synchronization detected by the bit synchronization circuit 6 becomes abnormal, and the BER of the output signal of the demodulator is generated. Will deteriorate.

  FIG. 8 is a diagram illustrating how the duty of the output signal of the data slicer 5 is disturbed when the time constant of the RC integration circuit included in the data slicer 5 is reduced. When the time constant of the RC integration circuit is sufficiently heavy, the RC integration circuit accurately and stably obtains the average DC voltage of the input signal (the ideal slicing level in FIG. 8) as the slicing level, and the data slicer 5 The output signal is a signal having an accurate duty (ideal output signal in FIG. 8). On the other hand, when the time constant of the RC integration circuit is light, the slicing level in the RC integration circuit varies as shown in FIG. 8 (in FIG. 8, the slicing level at the time of level variation). 5 is disturbed (in FIG. 8, the output signal at the time of level fluctuation).

  FIG. 9 is a diagram showing the sampling timing in the bit synchronization circuit 6. In FIG. 9, time C represents the minimum value of the time interval at which the signal level of the ideal input signal changes (hereinafter referred to as unit time), and the upward arrow represents the sampling timing in the bit synchronization circuit 6. As shown in FIG. 9A, when a signal whose duty is not disturbed is input, the bit synchronization circuit 6 samples the input signal at equal intervals and outputs normal data. On the other hand, as shown in FIGS. 9B and 9C, when a signal with a disturbed duty is input, the signal width (the length of the period during which the signal level is constant) is shorter than one unit time. May be.

  In general, it is difficult to align the signal width of the output signal of the data slicer 5 to an integral multiple of unit time. For this reason, the bit synchronization circuit 6 can cope with a certain amount of signal width disturbance instead of sampling at a fixed timing set every unit time (see FIG. 9B). Sampling method. For example, in the example shown in FIG. 9C, the bit synchronization circuit 6 performs sampling at a timing after a predetermined time α from the change timing of the input signal. If the signal level of the input signal does not change even after one unit time has elapsed, the bit synchronization circuit 6 performs sampling at the timing when one unit time has elapsed from the timing at which sampling was performed immediately before.

  The bit synchronization circuit 6 can correctly perform sampling by the above method only when the signal level to be sampled is input over about 50% or more of one unit time. For example, in the above method, the signal level to be sampled is input only about 20% of one unit time, and if sampling is performed within the remaining 80% period, an error occurs in data. I can't respond.

  As described above, when a signal having a level to be sampled for only a short time in one unit time is input, sampling is performed when a signal having an incorrect level is input (FIG. 9B). Sampling is performed when the input signal is unstable (time Tb in FIG. 9B), or sampling is performed a plurality of times during one unit time (time Tc in FIG. 9C). And a time Td) occurs.

In order to solve the above problem, there has been conventionally known a method of changing the slicing level rapidly under certain circumstances and stabilizing under other circumstances by dynamically switching the time constant of the RC integration circuit. (For example, Patent Document 1).
Japanese Patent Laid-Open No. 9-23247

  However, in the method described in Patent Document 1, the characteristics of the resistor and the capacitor, which are factors that determine the time constant, vary depending on factors such as the manufacturing process and temperature. Therefore, the variation in the signal width of the output signal of the data slicer can be reduced. It may not be sufficiently suppressed. In addition, when it is not known at what timing and in what pattern a signal that changes is received, it is difficult to generate a signal for controlling the time constant. For this reason, a technique for improving the reliability of the output signal of the data slicer by a method different from the switching of the time constant is required.

  Therefore, the present invention provides a signal correction device that corrects the change timing of a signal that changes in a rectangular shape output from a data slicer included in a wireless communication system that transmits and receives a packet having a short time slot at high speed. For the purpose.

  The signal correction apparatus of the present invention includes a delay unit that delays an input signal, a signal width acquisition unit that acquires the signal width of the input signal, a signal width history management unit that manages a history of the signal width, the acquired signal width, and A determination unit that determines whether to perform correction based on a history of signal width, a correction amount management unit that manages the length of time for correction as a correction amount, and a correction amount management unit according to the determination result in the determination unit A correction execution unit that corrects the delayed input signal by the amount of correction managed in step (b).

  In this case, the determination unit uses the first method when the signal width is equal to or smaller than the first threshold value, the signal width is equal to or larger than the second threshold value, and the next signal width is equal to the first threshold value. When it is larger than the threshold value, it is determined that the correction is performed by the second method, the correction amount management unit manages the first and second correction amounts, and the correction execution unit performs the correction by the first method. When the first correction amount is corrected by the second method, the second correction amount may be used. The correction execution unit may extend the signal width back and forth in time when performing the correction by the first method, and extend the signal width later in time when performing the correction by the second method.

  Alternatively, the signal correction apparatus may further include an error rate measurement unit that obtains the code error rate of the corrected signal, and the correction amount management unit may change the correction amount based on the code error rate.

  Alternatively, the signal correction device further includes a forced termination determination unit that outputs a forced termination signal when a state in which it is determined that no correction is performed continues for a predetermined time, and the correction execution unit outputs the forced termination signal. Correction may be stopped.

  According to the signal correction apparatus of the present invention, a threshold (referred to when an output signal is generated in the preceding circuit is determined by determining whether to perform correction based on the signal width of the input signal and its history. For example, even when the duty of the input signal is disturbed because the slicing level in the data slicer has changed, the input signal can be corrected correctly at high speed.

  In addition, the input signal can be correctly corrected at high speed without depending on the characteristics of the previous circuit. In this way, by absorbing the characteristic variation of the preceding circuit, the number of sample trial productions of the preceding circuit can be reduced, and the development period can be shortened.

  If the error rate measuring unit is provided, the input signal correction amount and the threshold value used in the correction determination are set to suitable values according to the communication state, and the input signal under various circumstances is set. Optimal correction can be performed.

  If the compulsory determination end unit is provided, the power consumption of the apparatus can be reduced by stopping the correction execution unit while it is not necessary to perform correction on the delayed input signal.

  Hereinafter, signal correction devices according to first to third embodiments of the present invention will be described with reference to the drawings. The signal correction apparatus according to each embodiment operates with a time shorter than one unit time of the input signal (minimum value of the time interval at which the signal level of the ideal input signal changes) as one cycle. In the following, for example, it is assumed that one unit time of the input signal is 1 microsecond, and the signal correction apparatus operates with one-third microsecond as one unit time (that is, at 13 MHz).

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the signal correction apparatus according to the first embodiment of the present invention. A signal correction apparatus 10 shown in FIG. 1 includes a delay unit 11, a signal width acquisition unit 12, a signal width history management unit 13, a correction amount management unit 14, a determination unit 15, and a correction execution unit 16. The signal correction device 10 is used, for example, in a demodulator included in a receiver of a digital radio communication system, with a data slicer 5 provided in the previous stage and a bit synchronization circuit 6 provided in the subsequent stage.

  A data slicer 5 provided at the front stage of the signal correction device 10 compares an input analog signal (not shown) with a slicing level obtained internally, and when the former is larger, the value “1” is set. When the value is larger, the value “0” is output. The output signal of the data slicer 5 becomes the input signal 100 of the signal correction device 10.

  The delay unit 11 delays the input signal 100 by a predetermined time D and outputs a delayed input signal 101. For this reason, the delay unit 11 accumulates the input signal 100 in chronological order and outputs the accumulated signals in chronological order. Note that the delay time D in the delay unit 11 is determined to be a value that can correct the delay input signal 101 correctly even after obtaining a signal width, updating a signal width history, and determining whether correction is necessary. .

  The signal width acquisition unit 12 acquires the signal width (length of a period during which the signal level is constant) 102 of the input signal 100. More specifically, the signal width acquisition unit 12 is based on the input signal 100 accumulated in the delay unit 11 and each time it detects that the input signal 100 has changed, a pulse signal having a width of 1/13 microseconds. And a value representing the time difference from the pulse signal generated immediately before in units of 1/13 microseconds is output as the signal width information 102. The signal width acquisition unit 12 may perform the above processing on the input signal 100 instead of the input signal 100 accumulated in the delay unit 11.

  The signal width history management unit 13 manages the history of the signal width acquired by the signal width acquisition unit 12. More specifically, the signal width history management unit 13 accumulates the signal width information 102 sequentially output from the signal width acquisition unit 12 as many as required by the determination in the determination unit 15, and stores the result as the signal width history. Output as information 103.

  The correction amount management unit 14 manages the length of time for which the correction execution unit 16 performs correction. More specifically, the correction amount management unit 14 holds a predetermined fixed value (or a fixed value supplied from the outside of the signal correction device 10), and outputs the held value to the determination unit 15 as the correction amount 104. To do.

  Whether the determination unit 15 performs correction based on the signal width information 102 output from the signal width acquisition unit 12, the signal width history information 103 output from the signal width history management unit 13, and the threshold value held therein. Determine whether or not. When the determination unit 15 determines to perform correction, the determination unit 15 outputs a correction command 105 over the time of the correction amount 104 output from the correction amount management unit 14.

  The correction execution unit 16 performs correction on the delayed input signal 101 while the correction command 105 is being output, and outputs the corrected signal as the output signal 106. Instead of the configuration described above, the correction execution unit 16 directly receives the correction amount 104 from the correction amount management unit 14 and receives the correction command 105. It is good also as performing correction with respect to.

  The output signal 106 of the correction execution unit 16 becomes an output signal of the signal correction device 10. The bit synchronization circuit 6 connected to the subsequent stage of the signal correction device 10 detects the bit synchronization from the output signal 106 and uses the detected bit synchronization to convert the original digital data transmitted from the transmitter (not shown). Reproduce.

  Hereinafter, details of the correction processing in the signal correction apparatus 10 will be described. The correction amount management unit 14 has two types of correction amounts ΔY and ΔW inside, and outputs these two types of correction amounts as correction amounts 104 to the determination unit 15. The signal width acquisition unit 12 outputs the signal width last acquired from the input signal 100 (latest signal width) as the signal width information 102. The signal width history management unit 13 outputs the signal width (signal width history) previously acquired from the input signal 100 as the signal width history information 103.

  The determination unit 15 has two types of threshold values L and K inside. The determination unit 15 determines whether to perform correction based on the signal width information 102, the signal width history information 103, and these two types of threshold values. More specifically, when the signal width is equal to or smaller than the threshold value L, the determination unit 15 corrects the signal width by extending it back and forth in time (see FIG. 2A. Hereinafter, referred to as the first correction). ). When the signal width is equal to or larger than the threshold value K, the determination unit 15 performs correction (see FIG. 2B, hereinafter referred to as second correction) that extends the signal width later in time. judge. However, even if the signal width is equal to or larger than the threshold value K, if the next signal width is equal to or smaller than the threshold value L, the determination unit 15 determines not to perform the second correction (see FIG. 2 (c)).

  When the determination unit 15 determines to perform the first correction, the signal width equal to or smaller than the threshold value L is output from the delay unit 11 and the signal width equal to or smaller than the threshold value L is output. At the same time, the correction command 105 is output for the time of ΔY / 2. Further, when the determination unit 15 determines to perform the second correction, the correction command 105 is output for the time of ΔW after the signal width equal to or greater than the threshold value K is output from the delay unit 11. While the correction command 105 is output, the correction execution unit 16 corrects the delayed input signal 101 to a different signal level (i.e., high level if low level, low level if high level).

  These correction processes are summarized as follows. When the signal width is equal to or smaller than the threshold value L, the determination unit 15 determines that the correction is performed by the first method, and the correction execution unit 16 moves the signal width forward and backward by the first correction amount ΔY. The delay input signal 101 is corrected so as to extend. When the signal width is equal to or greater than the second threshold value K and the next signal width is greater than the first threshold value L, the determination unit 15 determines that correction is performed by the second method. The correction execution unit 16 corrects the delayed input signal 101 so that the signal width increases in time later by the second correction amount ΔW.

  FIG. 2 is a diagram illustrating an example of correction processing in the signal correction apparatus 10. In FIG. 2, the corrected signal is drawn with a broken line. The signal correction apparatus 10 outputs an output signal 106 obtained by delaying the input signal 100 that changes in a rectangular shape by a delay time D in the delay unit 11. As shown in FIG. 2A, when the input signal 100 includes a signal width W1 that is equal to or smaller than the threshold value L, in the output signal 106, the signal width is extended forward and backward by ΔY. Specifically, when correction is not performed, when the start time of the signal width equal to or smaller than the threshold value L is T1 and the end time is T2, it is equal to or smaller than the threshold value L after the actual correction. The signal width start time is (T1−ΔY / 2) and the end time is (T2 + ΔY / 2).

  Also, as shown in FIG. 2B, when the input signal 100 includes a signal width W2 that is equal to or greater than the threshold value K, in the output signal 106, this signal width is extended later by ΔW. . Specifically, when the end time of the signal width equal to or greater than the threshold value K is T3 when correction is not performed, the end of the signal width equal to or greater than the threshold value K after the actual correction is performed. The time is (T3 + ΔW).

  However, if the signal correction apparatus 10 performs correction even when the input signal 100 includes a signal width W3 equal to or greater than the threshold value K and the next signal width W4 is equal to or less than the threshold value L, FIG. As shown in the figure, in the output signal 106, the signal width below the threshold value L may disappear. Therefore, as shown in FIG. 2 (c), even if the input signal 100 includes the signal width W3 equal to or greater than the threshold value K, if the next signal width W4 is equal to or less than the threshold value L, the output signal In 106, the signal width W3 is not changed, but only the signal width W4 is changed.

  As described above, according to the signal correction apparatus according to the present embodiment, when the output signal is generated in the preceding circuit by determining whether to perform correction based on the signal width of the input signal and its history. Even when the duty of the input signal is disturbed due to a change in the threshold value referred to (for example, the slicing level in the data slicer), the input signal can be corrected correctly at high speed.

  In addition, the input signal can be correctly corrected at high speed without depending on the characteristics of the previous circuit. In this way, by absorbing the characteristic variation of the preceding circuit, the number of sample trial productions of the preceding circuit can be reduced, and the development period can be shortened.

(Second Embodiment)
FIG. 4 is a block diagram showing a configuration of a signal correction apparatus according to the second embodiment of the present invention. The signal correction apparatus 20 shown in FIG. 4 adds an error rate measurement unit 27 to the signal correction apparatus 10 (FIG. 1) according to the first embodiment, and the correction amount management unit 14 and the determination unit 15 are respectively set. The correction amount management unit 24 and the determination unit 25 are replaced. Among the constituent elements of the present embodiment, the same constituent elements as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted. Hereinafter, details of the error rate measurement unit 27, the correction amount management unit 24, and the determination unit 25 will be described.

  The input signal 100 input to the signal correction device 20 appropriately includes a known data pattern (hereinafter referred to as an adjustment pattern). The error rate measurement unit 27 accumulates correct data of the adjustment pattern therein, and when the adjustment pattern is input to the signal correction device 20, the output signal 106 output from the correction execution unit 16 and the correct data. To measure the error rate of the output signal 106. The error rate measuring unit 27 outputs the measured error rate as error rate information 207.

  The correction amount management unit 24 is obtained by adding a function of appropriately switching the correction amount 204 to the correction amount management unit 14 described in the first embodiment. When the minimum value and the maximum value of the correction amount ΔY in the correction amount management unit 24 are set to ΔYm and ΔYM, the correction amount management unit 24 sets a value between ΔYm and ΔYM as the optimum correction amount ΔY based on the error rate information 207. Is output. The same applies to the correction amount ΔW.

  The determination unit 25 is obtained by adding a function of appropriately switching between two types of threshold values to the determination unit 15 described in the first embodiment. When the minimum value and the maximum value of the threshold value L in the determination unit 25 are Lm and LM, respectively, the determination unit 25 outputs a value between Lm and LM as the optimum threshold value based on the error rate information 207. The same applies to the threshold value K.

  While the adjustment pattern is input to the signal correction device 20, the error rate measuring unit 27 measures the error rate of the output signal 106, the correction amount in the correction amount management unit 24, and the threshold value (correction) in the determination unit 25. The lower limit value and the upper limit value used in the determination are adjusted to suitable values based on the error rate information 207. While the adjustment pattern is not input to the signal correction device 20, the correction amount in the correction amount management unit 24 and the threshold value in the determination unit 25 are fixed.

  As described above, according to the signal correction apparatus according to the present embodiment, the input signal correction amount and the threshold value used for correction determination are set to suitable values according to the communication state, and under various circumstances. Optimal correction can be performed on the input signal.

(Third embodiment)
FIG. 5 is a block diagram showing a configuration of a signal correction apparatus according to the third embodiment of the present invention. The signal correction device 30 shown in FIG. 5 adds a forced termination determination unit 38 to the signal correction device 10 (FIG. 5) according to the first embodiment, and replaces the correction execution unit 16 with a correction execution unit 36. Is. Among the constituent elements of the present embodiment, the same constituent elements as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted. Details of the forced termination determination unit 38 and the correction execution unit 36 will be described below.

  The forced termination determination unit 38 monitors the correction command 105 output from the determination unit 15 and outputs a forced termination command 308 to the correction execution unit 36 when a state where the correction command 105 is not output continues for a predetermined time. .

  The correction execution unit 36 is obtained by adding a function for forcibly terminating the correction to the correction execution unit 16 described in the first embodiment. When receiving the forced termination command 308, the correction execution unit 36 immediately stops the correction for the delayed input signal 101. When the correction execution unit 36 receives the correction command 105 from the determination unit 15, the correction execution unit 36 cancels the correction stop state and restarts the correction for the delayed input signal 101.

  As described above, according to the signal correction apparatus according to the present embodiment, the correction execution unit 36 stops while it is not necessary to perform correction on the delayed input signal 101. Thereby, the power consumption of the apparatus can be reduced.

  The forced termination determination unit 38 outputs a control signal supplied from the outside of the signal correction device 30 in addition to outputting the forced termination command 308 when the state where the correction command 105 is not output continues for a predetermined time. In response, the forced termination instruction 308 may be output.

  For example, in the Bluetooth (R) system, it is not necessary to change the slicing level of the data slicer 5 after the access code is detected, so a method of increasing the time constant of the data slicer 5 is adopted. In a system employing this method, it is known in advance that after the access code is detected, the duty of the output signal of the data slicer is not significantly disturbed and the input signal does not need to be corrected. Therefore, when this method is adopted, it is preferable to stop the correction for the input signal after detecting the access code. Therefore, an access code detection end signal (called a packet control signal in the Bluetooth (R) system) is input to the forced end determination unit, and when the access code detection end signal is input, the correction for the input signal is forcibly ended. By doing so, the power consumption of the circuit can be reduced.

  The signal correction apparatus according to the present invention can correct a signal that changes in a rectangular shape at high speed, and is used, for example, when correcting the output signal of a data slicer in a demodulator included in a receiver of a wireless communication system. In addition to this, the present invention can be widely used for correcting a signal that changes in a rectangular shape, such as a binary signal obtained by performing analog-digital conversion using a comparator.

The block diagram which shows the structure of the signal correction apparatus which concerns on the 1st Embodiment of this invention. The figure which shows the example of the correction process in the signal correction apparatus which concerns on the 1st Embodiment of this invention. Diagram showing how small signal width disappears due to improper correction The block diagram which shows the structure of the signal correction apparatus which concerns on the 2nd Embodiment of this invention. The block diagram which shows the structure of the signal correction apparatus which concerns on the 3rd Embodiment of this invention. The block diagram which shows the structure of the conventional FSK demodulator Circuit diagram showing the detailed configuration of a conventional data slicer Diagram showing how the duty of the output signal is disturbed when the slicing level fluctuates The figure which shows the sampling timing in the conventional bit synchronous circuit

Explanation of symbols

10, 20, 30 ... signal correction device 11 ... delay unit 12 ... signal width acquisition unit 13 ... signal width history management unit 14, 24 ... correction amount management unit 15, 25 ... determination unit 16, 36 ... correction execution unit 27 ... error Rate measuring unit 38 ... forced termination determining unit 100 ... input signal 101 ... delayed input signal 102 ... signal width information 103 ... signal width history information 104, 204 ... correction amount 105 ... correction command 106 ... output signal 207 ... error rate information 308 ... Forced termination instruction

Claims (5)

A signal correction device that changes a change timing of a signal that changes to a rectangular shape,
A delay unit for delaying the input signal to obtain a delayed input signal;
A signal width acquisition unit that acquires, as a signal width, a length of a period in which the signal level of the input signal is constant;
A signal width history management unit for managing the history of the signal width acquired by the signal width acquisition unit;
A determination unit for determining whether to perform correction based on the signal width acquired by the signal width acquisition unit and the history of the signal width managed by the signal width history management unit;
A correction amount management unit that manages the length of time for correction as a correction amount;
A signal correction apparatus comprising: a correction execution unit that corrects the delayed input signal by an amount of correction managed by the correction amount management unit according to a determination result in the determination unit. The determination unit uses the first method when the signal width acquired by the signal width acquisition unit is equal to or less than a first threshold value, the signal width is equal to or greater than a second threshold value, and When the next signal width is larger than the first threshold value, it is determined that correction is performed by the second method,
The correction amount management unit manages the first and second correction amounts as the correction amount,
The correction execution unit is configured to output the delayed input signal by the amount of the first correction amount when performing the correction by the first method, and by the amount of the second correction amount when performing the correction by the second method. The signal correction apparatus according to claim 1, wherein:   When performing the correction by the first method, the correction execution unit performs signal correction when performing the correction by the second method so that the signal width extends forward and backward by the amount of the first correction amount. The signal correction apparatus according to claim 2, wherein the delay input signal is corrected so that a width is increased later in time by the second correction amount. An error rate measurement unit for obtaining a code error rate of the signal corrected by the correction execution unit;
The signal correction apparatus according to claim 1, wherein the correction amount management unit changes the correction amount based on a code error rate obtained by the error rate measurement unit. A forced termination determination unit that outputs a forced termination signal to the correction execution unit when a state in which the determination unit determines not to perform correction continues for a predetermined time;
The signal correction apparatus according to claim 1, wherein the correction execution unit stops correction of the delayed input signal when the forced end signal is output.

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