JP2005175132A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of semiconductor devices capable of suppressing adverse effect on element characteristics and forming an extension region wherein a joining depth is comparatively shallow. <P>SOLUTION: A liner insulation film 18 covers a side circumferential wall of a gate electrode 17a and the end of a gate insulation film to suppress damages to the gate insulation film and a semiconductor substrate caused in the manufacturing process, and a source and drain region 20 is formed and thereafter the extension region 21 is formed to make the joining depth of the extension region 21 comparatively shallow. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device including an insulated gate field effect transistor (hereinafter referred to as MISFET).

  In recent years, higher performance and higher integration of semiconductor devices such as LSI using MISFET have been advanced. Along with this, not only the reduction in dimensions in the surface direction of the semiconductor substrate, such as the gate size of the MISFET, the width of the element isolation region, the width of the wiring, etc. It is also necessary to reduce the depth dimension of the semiconductor substrate, such as the junction depth.

  For this reason, an extension region having a relatively shallow junction depth is formed so as to be adjacent to the channel region directly under the gate insulating film and used for electrical conduction between the channels. On the other hand, the source and drain regions are formed on the semiconductor substrate so as to overlap with a part of the extension region using a region in which the side wall is formed on the gate electrode as a mask. Further, the source and drain regions are connected to the wiring through the contact region. Further, the step of forming the extension region is usually performed before the step of forming the source and drain regions (see, for example, Patent Document 1).

  A conventional semiconductor device such as an LSI using a MISFET has been improved in performance and integration by the above-described method. However, there are the following problems in further miniaturization of elements for higher performance and higher integration.

  That is, in the conventional MISFET manufacturing process, after forming the extension region, the source and drain regions are formed. Therefore, in the heat treatment process for forming the source and drain regions, the extension regions are also heat treated under the same conditions.

  The source and drain regions into which the high-concentration impurity is implanted are used for crystal recovery and impurity recovery in the impurity diffusion layer in order to reduce parasitic resistance (contact resistance) at the contact portion connected to the wiring or to suppress depletion at the gate electrode. It is essential to improve the activation rate of the introduced impurities. Therefore, for example, a relatively high temperature heat process of 1000 ° C. or higher is required.

  For example, arsenic or boron, which is an impurity imparting conductivity type, is ion-implanted with low acceleration energy, and even in an extension region formed relatively shallow, the impurity diffusion layer is formed in the depth direction by the above-described relatively high temperature thermal process. spread. For this reason, miniaturization of the element is hindered, and the element characteristics are also deteriorated.

In addition, a method for forming an extension region after forming a source and drain region including a heat treatment step at a relatively high temperature has been studied. However, the process becomes complicated, and problems such as etching of the substrate surface and introduction of damage to the end portion of the gate insulating film, which occur during the side wall forming process of the gate electrode, occur.
JP 2000-150882 A (page 12, FIG. 1)

  The present invention has been made to solve the above-described problems, and suppresses adverse effects on device characteristics such as etching of the substrate surface and introduction of damage to the edge of the gate insulating film, and the junction depth is relatively shallow. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming an extension region.

  In order to solve the above problems, a first aspect of the present invention is a method for manufacturing a semiconductor device, comprising: forming an element isolation region in a semiconductor substrate; and forming a gate insulating film in an element region surrounded by the element isolation region. A step of forming a gate electrode film on the gate insulating film, a step of selectively processing the gate electrode film to form a gate electrode, and a liner on the gate electrode and the semiconductor substrate. A step of stacking and forming an insulating film and a first sidewall insulating film; and the liner insulating film and the first sidewall insulating film so as to leave the liner insulating film and the first sidewall insulating film formed on the side peripheral wall of the gate electrode. A step of selectively processing one sidewall insulating film, and an element immediately below the gate electrode, the liner insulating film, and the first sidewall insulating film using the gate electrode, the liner insulating film, and the first sidewall insulating film as a mask. region A step of introducing a first impurity imparting a conductivity type into one region of the element region so as to sandwich the source region and forming a source region and a drain region; the first sidewall insulating film; the first sidewall insulating film; A step of selectively removing the liner insulating film existing between the semiconductor substrate and the element so as to sandwich an element region immediately below the gate electrode and the liner insulating film with the gate electrode film and the liner insulating film as a mask; And introducing a second impurity which gives the same conductivity type as the first impurity into one region to form an extension region.

  According to a second aspect of the present invention, as a method for manufacturing a semiconductor device, a step of forming an element isolation region in a semiconductor substrate, a step of forming a gate insulating film in an element region surrounded by the element isolation region, Forming a gate electrode film on the gate insulating film; forming a mask insulating film on the gate electrode film; and selectively processing the mask insulating film and the gate electrode film to form a gate electrode. A step of stacking and forming a liner insulating film and a first sidewall insulating film on the mask insulating film and the semiconductor substrate; a liner insulating film and a first sidewall formed on a side peripheral wall of the gate electrode; Selectively processing the liner insulating film and the first sidewall insulating film so as to leave an insulating film; and using the gate electrode, the liner insulating film and the first sidewall insulating film as a mask, the gate electrode, La Introducing a first impurity imparting a conductivity type into one region of the element region so as to sandwich the element region immediately below the first insulating layer and the first sidewall insulating film, and forming a source and drain region; A step of selectively removing the side wall insulating film, the liner insulating film existing between the first side wall insulating film and the semiconductor substrate, and the gate electrode film and the liner insulating film as a mask. A step of selectively growing a silicon film in a region where the semiconductor substrate is exposed so as to sandwich the electrode; and the same as the first impurity in the region of the element region existing under the silicon film and the silicon film that has been selectively grown And introducing a second impurity imparting a conductivity type to form an extension region.

  According to the present invention, by covering the side peripheral wall of the gate electrode and the edge of the gate insulating film with the liner insulating film, damage to the gate insulating film and the semiconductor substrate received in the manufacturing process can be suppressed, and the source and drain regions can be formed. By forming the extension region later, the junction depth of the extension region can be made relatively shallow. Thus, a method for manufacturing a semiconductor device having good element characteristics can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1A to FIG. 3I are sectional views showing a first embodiment of a semiconductor device manufacturing method according to the present invention in the order of steps. In the first embodiment, the present invention is applied to a MISFET having a CMOS circuit structure.

  First, a manufacturing process for forming an element isolation region in a semiconductor substrate will be described with reference to FIGS.

  As shown in FIG. 1A, a first insulating film 11 and a second insulating film 12 are laminated and formed on a surface region of a P-type silicon substrate 10 which is a semiconductor substrate. For example, a silicon oxide film is used as the first insulating film 11, and a silicon nitride film is used as the second insulating film 12, for example. Subsequently, the second insulating film 12 and the first insulating film 11 are selectively etched using a lithography method and an etching method to form a mask pattern.

  Next, the silicon substrate 10 is etched by dry etching using the second insulating film 12 and the first insulating film 11 as a mask to form a shallow trench. Further, as shown in FIG. 1B, for example, a silicon oxide film is formed as the third insulating film 13 by using the CVD method. The third insulating film 13 is embedded in the trench and is also deposited on the silicon substrate 10.

  Next, the CMP method and the etching method are used to flatten the surface of the silicon substrate 10, while the third insulating film 13 formed on the surface of the silicon substrate 10, the second insulating film 12 used as a mask, and the first insulating film 12 are used. The insulating film 11 is removed.

  As shown in FIG. 1C, a shallow trench isolation element isolation region 14 in which the third insulating film 13 is embedded is formed.

Subsequently, a silicon oxide film (not shown) having a thickness of about 5 nm is formed on the surface of the silicon substrate 10. After that, among the element regions selectively isolated by the element isolation region 14 of the silicon substrate 10, phosphorus as an N-type impurity is introduced into the P-channel MISFET formation region by an ion implantation method to form an N-type well region 15a. . On the other hand, boron as a P-type impurity is introduced into the N-channel MISFET formation region by ion implantation to form a P-type well region 15b. The dose amounts at this time are about 1E12 cm ^{−2 to} 1E13 cm ⁻² , respectively. Thereafter, for example, rapid heating is performed at 1,000 to 1,100 ° C. to activate the introduced impurities. Thereby, regions of the P-channel MISFET and the N-channel MISFET in the CMOS circuit structure are formed.

  Next, a manufacturing process for forming a gate structure will be described with reference to FIGS. 2 (d) to 3 (i).

  First, as shown in FIG. 2D, the surface of the silicon substrate 10 is thermally oxidized and then plasma nitrided to form a thermal oxynitride film having a thickness of about 1 to 2 nm as the gate insulating film 16. Next, a polycrystalline silicon film is formed to a thickness of, for example, about 100 nm as the gate electrode film 17 using the LPCVD method.

  Next, as shown in FIG. 2E, the gate electrode film 17 and the gate insulating film 16 are selectively etched by using a lithography method, a dry etching method, and a wet etching method, and the gate insulating film 16 and the gate electrode 17a. A laminated structure is formed.

  Further, as shown in FIG. 2F, a silicon nitride film having a thickness of about 2 nm is formed as the liner insulating film 18 by the LPCVD method. Subsequently, a silicon oxide film having a thickness of about 30 nm is formed as the first sidewall insulating film 19 by using the LPCVD method.

  Subsequently, the surface regions of the silicon substrate 10 and the gate electrode film 17 are selectively removed by using anisotropic etching by RIE, and as shown in FIG. The liner insulating film 18 is left on the side wall surface of the gate electrode 17a.

Next, source and drain regions 20 are formed by ion implantation using the gate electrode 17a, the first sidewall insulating film 19 and the liner insulating film 18 as a mask. That is, boron, which is a P-type impurity, is selectively introduced into the N-type well region 15a, and arsenic, which is an N-type impurity, is selectively introduced into the P-type well region 15b by an ion implantation method. The dose amounts at this time are about 1E15 cm ^{−2 to} 1E16 cm ⁻² , respectively. After that, for example, rapid heating is performed at 1,000 ° C. for about 10 seconds to activate the introduced impurities.

  Subsequently, as shown in FIG. 3H, after the first sidewall insulating film 19 is removed by wet etching or the like, the liner insulating film 18 remains on the gate sidewall by performing anisotropic etching by a dry etching method. To process.

Further, the extension region 21 is formed by ion implantation using the gate electrode 17a and the liner insulating film 18 as a mask. That is, boron, which is a P-type impurity, is selectively introduced into the N-type well region 15a, and arsenic, which is an N-type impurity, is selectively introduced into the P-type well region 15b by an ion implantation method. The dose amount at this time is about 1E14 cm ^{−2 to} 1E15 cm ⁻² , respectively. Thereafter, for example, rapid heating at about 900 ° C. is performed to activate the introduced impurities.

  When forming the gate electrode 17a, a method of selectively processing the gate electrode 17a and the liner insulating film 18 after forming the extension region 21 without selectively processing the gate insulating film 16 is used. May be.

  Next, a silicon oxide film having a thickness of about 30 nm is formed by LPCVD. Subsequently, as shown in FIG. 3I, the surface regions of the silicon substrate 10 and the gate electrode 17a are selectively removed by using anisotropic etching by the RIE method, and the gate electrode 17a and the liner insulating film 18 are removed. A second sidewall insulating film 19a is formed on the sidewall surface.

Further, a cobalt film (not shown) having a thickness of about 10 nm is formed by sputtering. Thereafter, for example, heat treatment is performed at about 500 ° C. in a nitrogen atmosphere. By this heat treatment, the silicon of the source and drain regions, the extension region 21, and the gate electrode 17a reacts with the cobalt film to form a cobalt silicide film. Subsequently, the unreacted cobalt film is removed by using a wet etching method. Next, a heat treatment at about 750 ° C. is performed to change the cobalt silicide film from a high resistance CoSi film to a low resistance CoSi ₂ , thereby forming a metal silicide electrode layer 22 made of CoSi ₂ .

  Thereafter, an interlayer insulating film made of a silicon oxide film (not shown) is deposited on the entire surface of the silicon substrate 10 using the CVD method, and then the surface is flattened by heat treatment, CMP method or the like. Contact holes are opened in the interlayer insulating film, and metal wirings such as Al and Cu connected to the gate electrode, source and drain regions of the N channel MISFET, and the gate electrode, source and drain regions of the P channel MISFET are formed.

  Further, a multilayer wiring structure is formed by repeatedly depositing an interlayer insulating film and forming a metal wiring as necessary. Further, the entire surface of the silicon substrate 10 is covered with a surface protective film, and the pad portion is opened to complete the first embodiment of the semiconductor device manufacturing method according to the present invention.

  According to the present embodiment, the side wall portion and the gate insulating film end portion of the gate electrode 17a are covered with the liner insulating film 18, so that the gate insulating film 16, the extension region 21, and the source by dry etching, ion implantation, etc. in the manufacturing process. In addition, damage to the drain region 20 can be suppressed.

  Further, by using a silicon nitride film as the liner insulating film 18 and a silicon oxide film as the first side wall insulating film 19, there is an advantage that the etching selectivity can be increased when the periphery of the gate electrode 17a is processed.

  Further, by forming the liner insulating film 18 as thin as about 5 nm, the end of the gate insulating film 16 can be protected and the junction depth of the extension region 21 can be controlled to be relatively shallow. The appropriate thickness of the liner insulating film 18 depends on the element size, but it needs to be suppressed to about 2 nm to 10 nm in order to be applied to a miniaturized element. That is, when the liner insulating film 18 is thick, it becomes difficult to control the junction depth of the extension region 21 to be shallow.

  Further, according to the present embodiment, by forming the extension region 21 after the formation of the source and drain regions 20, the junction depth of the extension region 21 can be made relatively shallow. Furthermore, the effect can be increased by keeping the heat treatment temperature in the formation of the extension region 21 lower than the heat treatment temperature in the formation of the source and drain regions 20.

  FIGS. 4A to 7K are cross-sectional views showing a second embodiment of the semiconductor device manufacturing method according to the present invention in the order of steps. As in the first embodiment, the second embodiment is an example in which the present invention is applied to a MISFET having a CMOS circuit structure. Also, the difference from the first embodiment is that it has a step of applying a selectively grown silicon film to the extension region.

  First, a manufacturing process for forming an element isolation region in a semiconductor substrate will be described with reference to FIGS.

  As shown in FIG. 4A, a first insulating film 11 and a second insulating film 12 are laminated and formed on a surface region of a P-type silicon substrate 10 which is a semiconductor substrate. For example, a silicon oxide film is used as the first insulating film 11, and a silicon nitride film is used as the second insulating film 12, for example. Subsequently, the second insulating film 12 and the first insulating film 11 are selectively etched using a lithography method and an etching method to form a mask pattern.

  Next, the silicon substrate 10 is etched by dry etching using the second insulating film 12 and the first insulating film 11 as a mask to form a shallow trench. Further, as shown in FIG. 4B, for example, a silicon oxide film is formed as the third insulating film 13 by using the CVD method. The third insulating film 13 is embedded in the trench and is also deposited on the silicon substrate 10.

  Next, the CMP method and the etching method are used to flatten the surface of the silicon substrate 10, while the third insulating film 13 formed on the surface of the silicon substrate 10, the second insulating film 12 used as a mask, and the first insulating film 12 are used. The insulating film 11 is removed.

  As shown in FIG. 4C, a shallow trench isolation element isolation region 14 in which the third insulating film 13 is embedded is formed.

Subsequently, a silicon oxide film (not shown) having a thickness of about 5 nm is formed on the surface of the silicon substrate 10. After that, among the element regions selectively isolated by the element isolation region 14 of the silicon substrate 10, phosphorus as an N-type impurity is introduced into the P-channel MISFET formation region by an ion implantation method to form an N-type well region 15a. . On the other hand, boron as a P-type impurity is introduced into the N-channel MISFET formation region by ion implantation to form a P-type well region 15b. The dose amounts at this time are about 1E12 cm ^{−2 to} 1E13 cm ⁻² , respectively. Thereafter, for example, rapid heating at about 1,000 to 1,100 ° C. is performed to activate the introduced impurities. Thereby, regions of the P-channel MISFET and the N-channel MISFET in the CMOS circuit structure are formed.

  Next, a manufacturing process for forming the gate structure will be described with reference to FIGS.

First, as shown in FIG. 5D, a thermal oxynitride film having a thickness of about 1 to 2 nm is formed as the gate insulating film 16 by thermally oxidizing the surface of the silicon substrate 10 and then plasma nitriding. Next, using a LPCVD method, a polycrystalline silicon film is formed as the gate electrode film 17 to about 80 nm, for example. Further, for example, boron is doped in the P-channel MISFET region, and arsenic is doped in the N-channel MISFET region, for example, by using an ion implantation method or the like, about 1E15 cm ^{−2 to} 1E16 cm ⁻² . Further, an LPCVD method is used as the mask insulating film 17b to form a silicon nitride film of about 20 nm.

  Next, as shown in FIG. 5E, the mask insulating film 17b, the gate electrode film 17, and the gate insulating film 16 are selectively etched by using a lithography method, a dry etching method, and a wet etching method to obtain a gate insulating film. 16, a laminated structure including the gate electrode 17a and the mask insulating film 17b is formed.

  Further, as shown in FIG. 5F, a silicon nitride film of about 5 nm is formed as the liner insulating film 18 by LPCVD. Subsequently, a silicon oxide film having a thickness of about 30 nm is formed as the first sidewall insulating film 19 by using the LPCVD method.

  Subsequently, the surface regions of the silicon substrate 10 and the mask insulating film 17b are selectively removed by using anisotropic etching by the RIE method, and the first sidewall insulating film 19 and the liner insulating film 18 are moved to the gate electrode 17a side. Remain on the wall.

Next, source and drain regions 20 are formed by ion implantation using the gate electrode 17a, the first sidewall insulating film 19 and the liner insulating film 18 as a mask. That is, boron, which is a P-type impurity, is selectively introduced into the N-type well region 15a, and arsenic, which is an N-type impurity, is selectively introduced into the P-type well region 15b by an ion implantation method. The dose amounts at this time are about 1E15 cm ^{−2 to} 1E16 cm ⁻² , respectively. Thereafter, for example, rapid heating at about 1,000 ° C. is performed to activate the introduced impurities.

  Subsequently, as shown in FIG. 6G, the first sidewall insulating film 19 is removed by a wet etching method, and then anisotropic etching using a dry etching method is performed, whereby the liner insulating film 18 is formed. The liner insulating film 18 is left on the side wall by being selectively removed.

  Next, a selective growth silicon film 23 having a thickness of about 10 nm is formed only in a region where the surface of the silicon substrate 10 is exposed using a selective growth method by LPCVD. Since the mask insulating film 17b is formed on the gate electrode 17a, the silicon film does not grow.

Further, as shown in FIG. 6H, an extension region 21 is formed by ion implantation using the gate electrode 17a and the liner insulating film 18 as a mask. That is, boron, which is a P-type impurity, is selectively introduced into the N-type well region 15a, and arsenic, which is an N-type impurity, is selectively introduced into the P-type well region 15b by an ion implantation method. The dose amount at this time is about 1E14 cm ^{−2 to} 1E15 cm ⁻² , respectively. Thereafter, for example, rapid heating at about 900 ° C. is performed to activate the introduced impurities.

  Next, a silicon oxide film having a thickness of about 30 nm is formed by LPCVD. Subsequently, as shown in FIG. 6I, the surface regions of the selectively grown silicon film 23 and the mask insulating film 17b are selectively removed by using anisotropic etching by the RIE method, and the gate electrode 17 and the liner insulation are removed. A second sidewall insulating film 19 a is formed on the sidewall surface of the film 18.

  Subsequently, as shown in FIG. 7J, the mask insulating film 17b on the gate electrode 17a is selectively removed by wet etching.

Further, a cobalt film (not shown) having a thickness of about 10 nm is formed by sputtering. Thereafter, for example, heat treatment is performed at about 500 ° C. in a nitrogen atmosphere. By this heat treatment, the silicon of the source and drain regions, the extension region 21, and the gate electrode 17a reacts with the cobalt film to form a cobalt silicide film. Subsequently, the unreacted cobalt film is removed by using a wet etching method. Next, heat treatment is performed at about 750 ° C. to change the cobalt silicide film from a high resistance CoSi film to a low resistance CoSi ₂ film, and as shown in FIG. 7 (k), a metal silicide electrode layer 22 made of CoSi _2. Form.

  Thereafter, an interlayer insulating film made of a silicon oxide film (not shown) is deposited on the entire surface of the silicon substrate 10 using the CVD method, and then the surface is flattened by heat treatment, CMP method or the like. Contact holes are opened in the interlayer insulating film, and metal wirings such as Al and Cu connected to the gate electrode, source and drain regions of the N channel MISFET, and the gate electrode, source and drain regions of the P channel MISFET are formed.

  Further, a multilayer wiring structure is formed by repeatedly depositing an interlayer insulating film and forming a metal wiring as necessary. Further, the entire surface of the silicon substrate 10 is covered with a surface protective film, and the pad portion is opened to complete the second embodiment of the semiconductor device manufacturing method according to the present invention.

  According to the present embodiment, the side wall portion and the gate insulating film end portion of the gate electrode 17a are covered with the liner insulating film 18, so that the gate insulating film 16, the extension region 21, and the source by dry etching, ion implantation, etc. in the manufacturing process. In addition, damage to the drain region 20 can be suppressed.

  Further, by using a silicon nitride film as the liner insulating film 18 and a silicon oxide film as the first side wall insulating film 19, there is an advantage that the etching selectivity can be increased when the periphery of the gate electrode 17a is processed.

  Further, by forming the liner insulating film 18 as thin as about 5 nm, the end of the gate insulating film 16 can be protected and the junction depth of the extension region 21 can be controlled to be relatively shallow. The appropriate thickness of the liner insulating film 18 depends on the element size, but it needs to be suppressed to about 2 nm to 10 nm in order to be applied to a miniaturized element. That is, when the liner insulating film 18 is thick, it becomes difficult to control the junction depth of the extension region 21 to be shallow.

  Further, according to the present embodiment, by forming the extension region 21 after the formation of the source and drain regions 20, the junction depth of the extension region 21 can be made relatively shallow. Furthermore, in the present embodiment, as a method of forming the extension region 21, by providing the selective growth silicon film 23, the junction depth of the extension region 21 can be further reduced. In addition, the effect can be increased by suppressing the heat treatment temperature in the formation of the extension region 21 to be lower than the heat treatment temperature in the formation of the source and drain regions 20.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

  In addition to the silicon nitride film and the silicon oxide film, a mixed film of a silicon nitride film and a silicon oxide film may be used as the liner insulating film, the first sidewall insulating film, and the second sidewall insulating film.

  Further, a method of manufacturing a semiconductor device, wherein the liner insulating film is a silicon oxide film and the first sidewall insulating film is a silicon nitride film, may be used.

  Furthermore, the semiconductor device manufacturing method may be characterized in that the thickness of the liner insulating film is 2 nm to 10 nm.

  In addition to cobalt silicide, the metal silicide layer may be silicide of nickel, tungsten, titanium, molybdenum, tantalum, palladium, platinum, niobium, or the like.

Also, the composition ratio of metal to silicon in the metal silicide layer is not necessarily CoSi _{2 in} the case of a cobalt silicide film, for example. The same applies to other metal silicides.

  In addition to the silicon oxynitride film, the gate insulating film may be a silicon oxide film, a silicon nitride film, or a stacked film of a silicon oxide film and a silicon nitride film. Needless to say, a metal oxide film such as a titanium oxide film or a hafnium oxide film can be used alone or in combination in a laminated structure.

  The semiconductor substrate is not limited to a silicon substrate, but a similar effect can be obtained with a III-V semiconductor substrate such as a GaAs substrate, or an insulating substrate such as an SOI substrate.

The schematic diagram of the cross section which shows the 1st Example in the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows the 1st Example in the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows the 1st Example in the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows the 2nd Example in the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows the 2nd Example in the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows the 2nd Example in the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows the 2nd Example in the manufacturing method of the semiconductor device by this invention in process order.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Silicon substrate 11 1st insulating film 12 2nd insulating film 13 3rd insulating film 14 Element isolation region 15a N-type well region 15b P-type well region 16 Gate insulating film 17 Gate electrode film 17a Gate electrode 17b Mask insulating film 18 liner insulating film 19 first side wall insulating film 19a second side wall insulating film 20 source and drain region 21 extension region 22 metal silicide electrode layer 23 selective growth silicon film

Claims (5)

Forming an element isolation region in a semiconductor substrate;
Forming a gate insulating film in an element region surrounded by the element isolation region;
Forming a gate electrode film on the gate insulating film;
Selectively processing the gate electrode film to form a gate electrode;
Laminating a liner insulating film and a first sidewall insulating film on the gate electrode and the semiconductor substrate; and
Selectively processing the liner insulating film and the first sidewall insulating film so as to leave the liner insulating film and the first sidewall insulating film formed on the side wall of the gate electrode;
Using the gate electrode, the liner insulating film, and the first sidewall insulating film as a mask, a conductive type is formed in a region of the element region so as to sandwich the element region immediately below the gate electrode, the liner insulating film, and the first sidewall insulating film. Introducing a first impurity to provide source and drain regions; and
Selectively removing the first sidewall insulating film and the liner insulating film existing between the first sidewall insulating film and the semiconductor substrate;
Using the gate electrode film and the liner insulating film as a mask, a second impurity imparting the same conductivity type as the first impurity is formed in a region of the element region so as to sandwich the element region immediately below the gate electrode and the liner insulating film. And a step of forming an extension region. A method for manufacturing a semiconductor device, comprising: After the step of forming the extension region,
Forming a second sidewall insulating film on the gate electrode and the semiconductor substrate;
Selectively processing the second sidewall insulating film so as to leave the second sidewall insulating film formed on the side peripheral wall of the gate electrode;
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of selectively forming a metal silicide layer on at least the source and drain regions. Forming an element isolation region in a semiconductor substrate;
Forming a gate insulating film in an element region surrounded by the element isolation region;
Forming a gate electrode film on the gate insulating film;
Forming a mask insulating film on the gate electrode film;
Selectively processing the mask insulating film and the gate electrode film to form a gate electrode;
Laminating a liner insulating film and a first sidewall insulating film on the mask insulating film and the semiconductor substrate; and
Selectively processing the liner insulating film and the first sidewall insulating film so as to leave the liner insulating film and the first sidewall insulating film formed on the side peripheral wall of the gate electrode;
Using the gate electrode, the liner insulating film, and the first sidewall insulating film as a mask, a first impurity imparting a conductivity type is introduced into one region of the element region so as to sandwich the element region under the gate electrode, and the source and Forming a drain region;
Selectively removing the first sidewall insulating film and the liner insulating film existing between the first sidewall insulating film and the semiconductor substrate;
A step of selectively growing a silicon film in a region where the semiconductor substrate is exposed so as to sandwich an element region immediately below the gate electrode, the liner insulating film, and the first sidewall insulating film, using the gate electrode film and the liner insulating film as a mask; When,
A step of introducing an extension region by introducing a second impurity which gives the same conductivity type as the first impurity into the selectively grown silicon film and a region of the element region existing under the silicon film. A method of manufacturing a semiconductor device. After the step of forming the extension region,
Forming a second sidewall insulating film on the gate electrode and the silicon film;
Selectively processing the second sidewall insulating film so as to leave the second sidewall insulating film formed on the side peripheral wall of the gate electrode;
4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of selectively forming a metal silicide layer on at least the source and drain regions.   The step of forming the source and drain regions includes a step of ion-implanting the first impurity and a step of performing a heat treatment for activating the first impurity, and the step of forming the extension region is a first step. And the step of performing a heat treatment for activating the second impurity, and the temperature of the heat treatment for activating the second impurity activates the first impurity. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature is lower than a temperature of the heat treatment to be performed.

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