JP2005175029A - Method of manufacturing bipolar transistor and bipolar transistor manufactured thereby - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a bipolar transistor which can reduce a manufacturing cost by reducing the number of manufacturing processes, and to provide the bipolar transistor manufactured by the same. <P>SOLUTION: A buried collector region is formed inside a semiconductor substrate, and a collector electrode formation region is formed in the semiconductor substrate to the depth of the buried collector region, and an interlayer dielectric formed of the same material as that of the collector electrode formation region is formed on top of the collector electrode formation region. Thereafter, an opening for collector electrode is formed by etching in the interlayer dielectric and in the collector electrode formation region. A collector electrode is formed in the opening for collector electrode to complete the bipolar transistor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a bipolar transistor manufacturing method and a bipolar transistor manufactured by the method.

  Conventionally, a bipolar transistor has a collector resistance reduced by forming a collector electrode in an opening for a collector electrode penetrating from an interlayer insulating film provided on an upper portion of a semiconductor substrate to an internal buried collector region. The speed was increased.

  The bipolar transistor having such a structure has been manufactured by the following manufacturing method.

  As shown in FIG. 7 (a), the bipolar transistor 100 is formed by forming an N-type buried collector region 102 in a P-type semiconductor layer 101 and then forming an N-type epitaxial layer made of silicon on the surface of the P-type semiconductor layer 101. The semiconductor substrate 104 is formed by forming the layer 103.

  Next, after forming an element isolation region 105 at a predetermined position on the surface of the semiconductor substrate 104, a polycrystalline silicon layer 106 is formed so as to cover all of them, and only a region serving as a base layer is opened using a resist mask. Then, a P-type diffusion region 116 is formed by ion implantation.

  Next, after removing the resist mask, an emitter formation region is opened, an emitter opening is made by a sidewall technique using the insulating film 117, and a polycrystalline silicon layer 107 containing an N-type impurity is formed thereon. To do. Thereafter, heat treatment is performed to diffuse and activate impurities in the base layer and the emitter layer. In the figure, 118 is an intrinsic base region.

  Next, as shown in FIG. 7B, the polysilicon layer 106 and the insulating film 117 are removed by etching so as to leave the base lead portion 108, and the N-type epitaxial layer 103 in the collector electrode region is etched. Thus, a through hole 109 reaching the depth of the N-type buried collector region 102 is formed.

  Next, as shown in FIG. 7C, an interlayer insulating film 110 made of silicon oxide is formed so as to cover the entire upper side of the semiconductor substrate 104.

  Next, as shown in FIG. 7 (d), a predetermined position of the interlayer insulating film 110 is removed by etching to form a contact hole 113 for forming the base electrode 111 and the emitter electrode 112, and the interlayer insulating film The through-hole 109 filled with 110 is etched again to form the collector electrode opening 114.

  The collector electrode opening 114 formed at this time passes through two layers of different materials, such as an interlayer insulating film 110 made of silicon oxide and an N-type epitaxial layer 103 made of silicon, and reaches a depth of the buried collector region 102. It has become.

  Next, the base electrode 111 and the emitter electrode 112 are formed by embedding an electrode member in each contact hole 113 in FIG. (E), and at the same time, the collector electrode 115 is formed by embedding the electrode member in the collector electrode opening 114 as well. It was manufactured (for example, refer to Patent Document 1).

  As described above, in the conventional bipolar transistor 100, when the collector electrode opening 114 is formed, the first etching is performed on the N-type epitaxial layer 103 made of silicon to form the through hole 109, and then the oxidation is performed. The interlayer insulating film 110 made of silicon was formed by performing the second etching.

That is, etching was performed twice in order to form the collector electrode opening 114.
Japanese Patent No. 3132460

  However, in the above conventional bipolar transistor manufacturing method, it is necessary to form a collector electrode opening that penetrates two different layers such as an interlayer insulating film made of silicon oxide and an N-type epitaxial layer made of silicon. When forming the electrode opening, first, a through hole reaching the depth of the N type buried collector region is formed by etching the N type epitaxial layer made of silicon, and then the entire upper surface including the through hole is formed. Then, after forming an interlayer insulating film made of silicon oxide, the through-hole filled with the interlayer insulating film is etched again.

  As described above, in order to form the collector electrode opening, it is necessary to perform etching twice on the same region, which increases the number of manufacturing steps, which may increase the manufacturing cost of the bipolar transistor. there were.

  Therefore, in the present invention according to claim 1, the buried collector region is formed in the semiconductor substrate, the collector electrode forming region is formed in the semiconductor substrate to a depth reaching the buried collector region, and the same material as the collector electrode forming region is formed thereon. Then, a collector electrode opening is formed in the interlayer insulating film and the collector electrode formation region by etching, and a collector electrode is formed in the collector electrode opening.

  Further, in the present invention according to claim 2, in the present invention according to claim 1, the collector electrode forming region is formed by implanting an impurity having an accelerated oxidation effect into a predetermined position of the semiconductor substrate, and then oxidizing it. It was decided to form.

  According to the third aspect of the present invention, the buried collector region provided inside the semiconductor substrate, the collector electrode forming region formed to the depth reaching the buried collector region in the semiconductor substrate, and the collector electrode forming region are made of the same material. An interlayer insulating film, a collector electrode opening through which the interlayer insulating film and the collector electrode forming region are etched, and a collector electrode provided in the collector electrode opening are provided.

  And in this invention, there exists an effect described below.

  That is, in the present invention according to claim 1, the buried collector region is formed in the semiconductor substrate, the collector electrode forming region is formed in the semiconductor substrate to the depth reaching the buried collector region, and the same material as the collector electrode forming region is formed thereon. After that, a collector electrode opening is formed in the interlayer insulating film and the collector electrode formation region by etching, and a collector electrode is formed in the collector electrode opening. Since the region and the interlayer insulating film are formed of the same material, it is possible to form an opening for the collector electrode that penetrates the collector electrode forming region and the interlayer insulating film by a single etching. Can reduce the number of manufacturing costs of bipolar transistors Kill.

  Further, in the present invention according to claim 2, the collector electrode formation region is formed by implanting impurities having a speed-up oxidation effect into a predetermined position of the semiconductor substrate and then oxidizing them. Can be formed easily.

  According to the third aspect of the present invention, the buried collector region provided inside the semiconductor substrate, the collector electrode forming region formed to the depth reaching the buried collector region in the semiconductor substrate, and the collector electrode forming region are made of the same material. Since the interlayer insulating film, the collector electrode opening through which the interlayer insulating film and the collector electrode forming region have been etched, and the collector electrode provided in the collector electrode opening are provided, the collector electrode opening is formed. By reducing the number of steps, the bipolar transistor can be manufactured at low cost.

  The bipolar transistor according to the present invention includes a buried collector region provided inside a semiconductor substrate, a collector electrode forming region formed in the semiconductor substrate to a depth reaching the buried collector region, and an interlayer made of the same material as the collector electrode forming region. It has an insulating film, a collector electrode opening through which the interlayer insulating film and the collector electrode formation region are etched, and a collector electrode provided in the collector electrode opening.

  In this bipolar transistor manufacturing method, first, a collector electrode formation region is formed from a surface to a depth reaching the buried collector region on a semiconductor substrate having a buried collector region formed therein.

  The collector electrode formation region is formed by selectively changing the material of the semiconductor substrate with respect to a predetermined region of the semiconductor substrate, and in particular, the same material as that of the interlayer insulating film formed on the upper portion of this region in a later process. It is said.

  Next, a base layer and an emitter layer are sequentially stacked on the semiconductor substrate on which the collector electrode formation region is formed, thereby forming a base region and a collector region, respectively, and then an interlayer insulating film is formed on the surface of the semiconductor substrate. .

  Next, in the interlayer insulating film, a collector electrode opening reaching the buried collector forming region is formed by etching a predetermined position, and contact holes reaching the base region and the emitter region are formed.

  Finally, a collector electrode, a base electrode, and an emitter electrode are formed by embedding electrode members in the collector electrode openings and the respective contact holes.

  As described above, in the present invention, the collector electrode forming region and the interlayer insulating film are formed of the same material, so that the etching for the collector electrode is performed once under the same conditions as the etching conditions for forming the contact hole. Therefore, the number of manufacturing steps can be reduced and the manufacturing cost can be reduced.

  In particular, the collector electrode formation region is formed by modifying the material of the semiconductor substrate by implanting impurities having a speed-up oxidation effect into the semiconductor substrate.

  Therefore, the collector electrode formation region can be made to be an oxide film of the same quality as the interlayer insulation film by the oxidation treatment after the formation of the collector electrode formation region due to the action of the impurity having the accelerated oxidation effect, and the interlayer insulation film etching process Thus, the collector electrode opening can be formed by etching up to the collector electrode formation region.

  A bipolar transistor manufacturing method according to the present invention will be described below with reference to the drawings.

  In the present embodiment, as shown in FIG. 1, a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) in which a bipolar transistor 1a, an N-channel MOS transistor 1b, and a P-channel MOS transistor (not shown) are mounted on the same semiconductor substrate 5 is used. ) 1 will be described as an example, but the present invention is not limited to this, and can also be applied to manufacturing a semiconductor device in which a bipolar transistor and other semiconductor elements are mixedly mounted on the same substrate.

  As shown in FIG. 2, the semiconductor substrate 5 for forming the BiCMOS 1 forms an embedded collector region 3 by diffusing an N-type impurity in a required position of the P-type Si (silicon) substrate 2, thereby forming the P-type Si substrate 2. An N-type epitaxial layer 4 is formed on the upper surface.

  Further, an oxide film is formed on the surface of the N-type epitaxial layer 4 by thermal oxidation, and a LOCOS 6 is formed on the oxide film by forming a required LOCOS formation mask (not shown) and performing steam oxidation. doing.

  After the LOCOS 6 is formed, an element isolation region 7 is formed under the LOCOS 6 by implanting boron ions or the like that are P-type impurities. In addition, P well 8 is formed by implanting boron ions into a required position of N channel MOS transistor 1b when element isolation region 7 is formed.

  After the formation of the element isolation region 7, a tungsten silicide layer is formed on the surface of the semiconductor substrate 5, and the tungsten silicide layer is patterned to form the gate 9 of the N-channel MOS transistor 1b and the gate of the P-channel MOS transistor. Thereafter, a first TEOS (tetraethoxysilane) oxide film 10 is formed on the surface of the semiconductor substrate by a low pressure CVD (Chemical Vapor Deposition) method.

  After the formation of the first TEOS oxide film, a mask layer 11 made of a resist is formed on the surface of the first TEOS oxide film 10.

  The mask layer 11 is provided with a first opening for forming the collector electrode formation region 13 and a second opening for forming the source and drain of the N-channel MOS transistor 1b. The first opening and the second opening Then, arsenic ions, which are N-type impurities, are implanted into the N-type epitaxial layer 4 to form the collector electrode forming region 13, the source forming region 12 of the N-channel MOS transistor 1b, and the drain forming region 12 ′. .

At this time, the impurity implanted into the collector electrode formation region 13 uses arsenic ions,
Other impurity ions having accelerated oxidation effect such as phosphorus and antimony can also be used.

After the collector electrode formation region 13 is formed, the mask layer 11 is removed, and then, a Si ₃ N ₄ (silicon nitride) layer 14 is formed on the semiconductor substrate 5 as an oxidation resistant mask layer.

An oxidation opening 13a is formed in the upper portion of the collector electrode forming region 13 of the Si ₃ N ₄ layer 14 as shown in FIG.

  Then, by performing steam oxidation, as shown in FIG. 4, the collector electrode forming region 13 made of a silicon oxide film is formed by oxidizing the silicon in the collector electrode forming region 13 portion.

  In particular, an oxide film can be formed in the collector electrode forming region 13 as much as possible by implanting impurities having a speed-up oxidation effect.

  Moreover, this oxide film reaches the buried collector region 3, and during steam oxidation, the source formation region 12, the drain formation region 12 'of the N-channel MOS transistor 1b, and the source of the P-channel MOS transistor By activating the impurities implanted into the formation region and the drain formation region, the source region 15 and drain region 15 ′ of the N-channel MOS transistor 1b and the source and drain regions of the P-channel MOS transistor are formed.

Next, as shown in FIG. 5, after the collector electrode forming region 13 made of an oxide film is formed, the Si ₃ N ₄ layer 14 is removed to form the base layer 18.

  The base layer 18 is a SiGe mixed crystal layer (silicon silicon) in which impurities of the base layer are added non-selectively on the upper surface of the semiconductor substrate 5 after providing a base opening in the collector-base junction region portion of the first TEOS oxide film 10. (Germanium mixed crystal layer) 16 is epitaxially grown, and at the same time, a polycrystalline silicon / germanium layer serving as the base lead portion 17 is formed. Thereafter, the base layer 18 is patterned into a predetermined shape.

  After the formation of the base layer 18, a second TEOS oxide film 19 is formed on the upper surface of the semiconductor substrate 5 by a low pressure CVD method, and after providing an emitter opening 20a at the base-emitter junction of the second TEOS oxide film 19, An amorphous silicon layer 21 containing an emitter impurity is formed on the upper surface of the semiconductor substrate 5, and after this amorphous silicon layer 21 is patterned into a predetermined shape, a heat treatment is performed from the impurity diffusion layer on the SiGe mixed crystal layer 16. An emitter layer 20 is formed.

  After the emitter layer 20 is thus formed, an interlayer insulating film 22 made of a silicon oxide film is formed on the upper surface of the semiconductor substrate 5 by a low pressure CVD method.

  After the formation of the interlayer insulating film 22, the upper surface of the interlayer insulating film 22 is planarized by CMP (Chemical Mechanical Polishing).

  After planarization of the interlayer insulating film 22, a resist film is formed on the upper surface of the interlayer insulating film 22, and an opening for forming the contact hole 23 and an opening for forming the collector electrode opening 24 are formed in the resist film. This constitutes a resist pattern.

  By using this resist pattern, the interlayer insulating film 22 is etched by the RIE (Reactive Ion Etching) method to form the contact hole 23 and the collector electrode opening 24.

  In particular, since the collector electrode forming region 13 is made of the same silicon oxide as the interlayer insulating film 22, it can be continuously etched following the etching of the interlayer insulating film 22, and can be performed once without changing the etching conditions. The collector electrode opening 24 reaching the collector electrode formation region 13 can be formed by this etching.

  Finally, as shown in FIG. 1, barrier metal is formed as an electrode member in each contact hole 23 and collector electrode opening 24, and then tungsten is buried to embed tungsten 25, base electrode 26, collector of bipolar transistor 1a. The electrode 27, the gate electrode 28, the source electrode 29, and the drain electrode 30 of the N-channel MOS transistor 1b and the P-channel MOS transistor are formed, and a multilayer wiring layer and a protective insulating film are formed on the surface.

  As described above, in the BiCMOS 1 of the present embodiment, the N-type impurity is implanted into the source / drain formation regions 12 and 12 of the N-channel MOS transistor 1b constituting the BiCMOS, and also in the collector electrode formation region 13 of the bipolar transistor 1a. N-type impurities are implanted at the same time, and then heat treatment is performed on the N-type impurities implanted in the source / drain formation regions to form the source region 15 and the drain region 15 ′, and the accelerated oxidation action by the N-type impurities is utilized Thus, a collector electrode forming region 13 made of a silicon oxide film is formed.

  Therefore, the collector electrode forming region 13 can be formed of a silicon oxide film made of the same material as the interlayer insulating film 22 without increasing the number of manufacturing steps, and the buried collector region is formed by the action of an N-type impurity having an accelerated oxidation effect. It can be oxidized to a depth up to 3.

  Thus, the collector electrode forming region 13 is etched at once to the depth reaching the buried collector region 3 along with the etching of the interlayer insulating film 22, and penetrates from the surface of the interlayer insulating film 22 to the depth reaching the buried collector region 3. A collector electrode opening 24 can be formed.

  Further, since the base layer 18 and the emitter layer 20 of the bipolar transistor 1a are formed after the source / drain regions 15, 15 ′ and the P-channel MOS transistor source / drain regions of the N-channel MOS transistor 1b are formed, Since the layer 18 and the emitter layer 20 can be prevented from being affected by the heat treatment for forming the source / drain regions 15 and 15 ′, the base layer 18 and the emitter layer 20 can be shallowly joined. BiCMOS 1 equipped with bipolar transistor 1a capable of high-speed operation can be manufactured.

It is explanatory drawing which shows the bipolar transistor which concerns on this invention. It is explanatory drawing which shows the manufacturing process of the bipolar transistor which concerns on this invention. It is explanatory drawing which shows the manufacturing process of the bipolar transistor which concerns on this invention. It is explanatory drawing which shows the manufacturing process of the bipolar transistor which concerns on this invention. It is explanatory drawing which shows the manufacturing process of the bipolar transistor which concerns on this invention. It is explanatory drawing which shows the manufacturing process of the bipolar transistor which concerns on this invention. It is explanatory drawing which shows the manufacturing process of the conventional bipolar transistor.

Explanation of symbols

1a Bipolar transistor 1b N-channel MOS transistor 1 BiCMOS
2 P-type Si (silicon) layer 3 Embedded collector region 4 N-type epitaxial layer 5 Semiconductor substrate 6 Element isolation insulating layer 7 Element isolation region 8 P well 9 Gate 10 First TEOS oxide film 11 Mask layer 12 Source formation region 12 ′ Drain formation Region 13 Collector electrode forming region 13a Oxidation opening 14 Si ₃ N ₄ layer 15 Source region 15 ′ Drain region 16 SiGe mixed crystal layer 17 Base lead portion 18 Base layer 19 Second TEOS oxide film 20 Emitter layer 20a Emitter opening 21 Emitter opening Impurity-containing amorphous silicon layer 22 Interlayer insulating film 23 Contact hole 24 Collector electrode opening 25 Emitter electrode 26 Base electrode 27 Collector electrode 28 Gate electrode 29 Source electrode 30 Drain electrode

Claims (3)

A buried collector region is formed inside the semiconductor substrate, a collector electrode forming region is formed in the semiconductor substrate to a depth reaching the buried collector region, and an interlayer insulating film made of the same material as the collector electrode forming region is formed thereon Then, a collector electrode opening is formed by etching in the interlayer insulating film and the collector electrode formation region, and a collector electrode is formed in the collector electrode opening. 2. The method of manufacturing a bipolar transistor according to claim 1, wherein the collector electrode forming region is formed by implanting an impurity having a speed-up oxidation effect at a predetermined position of the semiconductor substrate and then oxidizing the impurity. A buried collector region provided in a semiconductor substrate; a collector electrode forming region formed in the semiconductor substrate to a depth reaching the buried collector region; an interlayer insulating film made of the same material as the collector electrode forming region; and the interlayer insulation A bipolar transistor comprising: a collector electrode opening through which a film and the collector electrode formation region are etched, and a collector electrode provided in the collector electrode opening.

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