JP2005174365A - Data processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable high-speed processing of data even when a load is varied depending on data to be processed. <P>SOLUTION: This data processing system asynchronously applies a plurality of successive processes to a plurality of pixel data serially inputted, and is provided with: a plurality of MPUs for executing a plurality of respective processes, the plurality of processes each including an attribute determination process for detecting the attribute on the basis of the plurality of pixel data; and a data flow control part for changing over processes executed by the plurality of MPUs (YES or NO in S72) according to the attribute detected on the basis of the plurality of pixel data by the attribute determination process (S71). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data processing system, and more particularly to a data processing system that executes a plurality of processes in a predetermined order by a plurality of processing units.

  FIG. 30 is a block diagram showing an outline of a synchronous pipeline type data processing apparatus as the first prior art. A conventional data processing device includes an MPU 70, an image input device 71, processing units 72 to 76 that respectively perform five processes of SH correction, Log conversion, MTF correction, gamma correction, and binarization, and an image output device 77. including. The image input device 71 includes a photoelectric conversion element such as a CCD, a driving system for operating the photoelectric conversion element, and an A / D converter. For example, a sampled analog signal is generated by scanning a mixed original composed of continuous tone images and line drawings. Then, the sampled analog signal is quantized by the A / D converter as continuous tone reflectance data in which one pixel has a value of, for example, 8 bits (256 gradations), and a digital signal is output.

  The processing unit 72 performs SH correction processing. The SH correction process is also referred to as shading correction, and refers to a correction process for removing reading unevenness (shading unevenness) caused by variations in performance or the like in the photoelectric conversion elements of the CCD of the image input device 71.

  The processing unit 73 performs a log conversion process. The log conversion process is a process for calculating and outputting 8-bit continuous tone density data having a log relationship with the continuous tone reflectance data subjected to the SH correction process.

  The processing unit 74 performs MTF correction processing. The MTF correction processing is sharpness correction, and sharpness correction is performed on 8-bit continuous tone density data obtained by subjecting the image data to log conversion processing by the processing unit 73 using a digital filter such as a Laplacian filter. .

  The processing unit 75 performs gamma correction processing. The gamma correction process is a process of correcting a difference in gradation curve between the image input device 71 and the image output device 77 in order to realize a gamma characteristic as desired for the entire data processing apparatus. For example, this is a process of outputting non-linear gamma correction data using a 256 word 8-bit LUT (Look Up Table). The gamma correction processing can also be performed for the operator to set his / her desired gamma characteristics.

  The processing unit 76 performs binarization processing. The binarization processing is processing for converting gamma-corrected 8-bit continuous tone density data into 1-bit binary data corresponding to light and dark. For the binarization processing, for example, an area gradation binarization method such as an error diffusion binarization method is used.

  The image output device 77 is a printer such as an electrophotographic printer or an inkjet printer, and prints 1-bit binary data binarized by the processing unit 76 on an output medium such as paper.

  The image input device 71, the processing units 72 to 76, and the image output device 77 are connected by an image data bus, and process data input in synchronization with a common pixel clock.

  As described above, in the synchronous pipeline type data processing apparatus shown in the first prior art, the image data input by the image input apparatus 71 is sequentially processed by the processing units 72 to 76 for each pixel data. Is done. In order to synchronize input / output of pixel data among the image input device 71, the processing units 72 to 76, and the image output device 77, a pixel clock corresponding to each piece of pixel data is a clock oscillator (not shown). The image input 71, the processing units 72 to 76, and the image output device 77 operate in synchronization with the pixel clock.

  In the second prior art, there is a method in which the five processes shown in the first prior art are asynchronously processed by five processing units. FIG. 31 is a block diagram for explaining the asynchronous processing method. Referring to FIG. 31, processing blocks 81, 82, 83 can operate by operating with their own clocks 85, 86, 87, respectively. However, since each processing block operates without being synchronized, data cannot be directly exchanged between the processing blocks. For this reason, it is necessary to provide buffer memories 83 and 84 having a predetermined capacity between the blocks. This is because by providing the buffer memories 83 and 84, the difference in processing speed between the processing blocks 80, 81 and 82 can be absorbed.

  Furthermore, there is a parallel processing method for processing the same processing in parallel as the third conventional technique. For example, in the technique disclosed in Japanese Patent Laid-Open No. 61-28164, a pipeline processor in which a plurality of image pipeline processors to be processed in parallel are connected in a ring form a task (image data) and an object program and task for each task. A technique is disclosed in which each table is loaded from a memory and predetermined tasks are processed in parallel.

  However, in the synchronous pipeline type data processing apparatus shown in the first prior art, each of the image input apparatus 71, the processing blocks 72 to 76, and the image output apparatus 77 operates in synchronization with the pixel clock. Therefore, the pixel clock must be generated in accordance with the image input device 71, the processing blocks 72 to 76, and the image output device 77 having the slowest operation speed. For this reason, a circuit must be configured in accordance with a processing block (processing block with a low operation speed) that becomes a bottleneck, and circuit design is difficult.

  Also, in the asynchronous processing method data processing apparatus shown in the second prior art, the processing block which is a bottleneck determines the processing speed of the data processing apparatus, compared to the synchronous pipeline method shown in the first prior art. However, this increases the cost because a buffer memory is required. In addition, since writing and reading of data from the two processing blocks occur in the buffer memory, each of the processing blocks arbitrates so that any one processing block can access the buffer memory. There is a problem that it must be performed by a processing block or by a controller provided for each buffer memory.

  Further, in the parallel processing method shown in the third prior art, since processing with a large processing load is processed by a plurality of processing blocks connected in parallel, processing can be performed at high speed, but processing with heavy processing is executed. In order to add extra blocks in advance, if the load of the processing block varies depending on the input data, when the load is small, one of the processing blocks connected in parallel will not be used. There was a problem of poor performance.

  The present invention has been made to solve the above-mentioned problems, and has been devised to control asynchronous processing, enabling high-speed processing of data even when the load varies depending on the data to be processed. An object of the present invention is to provide a data processing system.

  In order to achieve the above-described object, according to one aspect of the present invention, a data processing system is a data processing system that asynchronously performs a series of a plurality of processes on a plurality of input data that are serially input. The plurality of processing units that execute each of the processes and the plurality of processes include an attribute determination process that detects an attribute for each of the plurality of input data, according to the attribute detected for each of the plurality of input data by the attribute determination process And an operation control means for switching processing executed by the plurality of processing units.

  Preferably, the operation control means includes a prediction means for predicting loads of a plurality of processes, and the processing unit that executes the immediately preceding process immediately before the load process predicted to have a large load by the prediction means includes the immediately preceding process and the load process. The process to be executed is switched so as to execute the two processes.

  Preferably, the operation control unit includes a prediction unit that predicts the load of a plurality of processes, and the processing unit that executes the immediately following process immediately after the load process predicted to have a large load by the prediction unit includes the load process and the immediately following process. The process to be executed is switched so as to execute the two processes.

  Preferably, the plurality of processing units include at least one preliminary processing unit that is greater than the number of the plurality of processes and that does not execute any of the plurality of processes before switching of the processing by the operation control unit. It includes a prediction unit that predicts a load of a plurality of processes, and the preliminary processing unit switches a process to be executed so as to execute a load process in which the load is predicted to be large by the prediction unit.

  Preferably, the information processing apparatus further includes a storage unit that stores a result of processing executed by each of the plurality of processing units, and the operation control unit includes a prediction unit that predicts a load of the plurality of processes, and the prediction unit predicts that the load is large. The processing unit that executes the process subsequent to the load process is switched so that the process is executed so as to execute the load process.

  Preferably, the plurality of processing units deliver the input data after executing the self-processing to a processing unit that executes a process immediately after the self-processing executed by the self among the plurality of processes.

  According to these inventions, it is possible to provide a data processing system capable of high-speed data processing because the processing executed by the processing unit is switched according to the input data load regardless of the type of input data. Can do.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals denote the same or corresponding members.

[First Embodiment]
FIG. 1 is a block diagram showing an outline of a data processing apparatus according to the first embodiment of the present invention. Referring to the figure, a data processing apparatus according to the first embodiment includes an image input apparatus 1 that inputs image data, MPUs 2 to 6 that perform various processes on the input image data for each pixel data, and processing The operation statuses of the image output device 8 that outputs the image data to a recording medium such as paper, the image input device 1, the MPU 2 to 6, and the image output device 8 (hereinafter referred to as “MPU 1 to 8”) are monitored A status register 10, a data flow control unit 9 that controls operations of the MPUs 1 to 8 with reference to the status register 10, an input buffer memory 11 that temporarily stores image data input by the image input device 1, and an image And an output buffer memory 12 for temporarily storing image data output from the output device.

  The MPUs 2 to 6 are microprocessing units, and the contents to be processed by the MPUs 2 to 6 are determined by instructions from the data flow control unit 9 and stored in a ROM provided in the data flow control unit 9. By loading the processing program, the processing to be executed by each of the MPUs 2 to 6 is determined. In the initial state, for example, when the data processing apparatus is turned on or when one page of image data is input, MPU2 performs SH correction processing, MPU3 performs Log conversion processing, and MPU4 performs MTF correction processing. The MPU 5 receives an instruction from the data flow control unit 9 to perform gamma correction processing and the MPU 6 performs binarization processing, and each program is loaded by each MPU 2-6. The contents of the five processes of the SH correction process, the log conversion process, the MTF correction process, the gamma correction process, and the binarization process are the same as those described in the first prior art of the prior art. The description here will not be repeated.

  Similarly, the image input device 1 and the image output device 8 are the same as the image input device 71 and the image output device 77 described in the related art, respectively, and thus description thereof will not be repeated.

  The MPUs 1 to 8 are connected to the data flow control unit 9 by the system bus 14 and are connected to the status register 10 by the system bus 15. The MPUs 1 to 8 are connected to each other by the image data bus 13 so that pixel data can be transferred between the MPUs 1 to 8 and input / output to the input buffer memory 11 and the output buffer memory 12 can be performed. It has become.

  In the data processing apparatus shown in FIG. 1, image data is stored in the input buffer memory 11 for each pixel data by reading a document with the image input apparatus 1. In the MPU 2, the pixel data stored in the input buffer memory 11 is read out in the order stored in the image input device 1 and subjected to SH correction processing. Pixel data that has been subjected to SH correction processing by the MPU 2 is delivered to the MPU 3. The MPU 3 performs a log conversion process on the pixel data received from the MPU 2 and delivers the pixel data to the MPU 4. As described above, the pixel data is sequentially transferred to the MPUs 2 to 6 and subjected to SH correction processing, Log conversion processing, MTF correction processing, gamma correction processing, and binarization processing, and binarization processing is performed in the MPU 6. The pixel data is stored in the output buffer memory 12. The image output device 8 stores the processed pixel data in the output buffer memory, and at the same time performs display output on a display or print output on a recording medium such as paper.

  FIG. 2 is a diagram for explaining a procedure of data transfer between the MPU that executes the former stage process and the MPU that executes the latter stage process. FIG. 2 shows an example of a procedure for data transfer between the MPU 3 and the MPU 4. When the processing is completed in the MPU 3, a signal REQ for requesting delivery of the pixel data DATA to the MPU 4 is transmitted. After receiving the signal REQ requesting delivery from the MPU 3, the MPU 4 transmits to the MPU 3 a signal ACK for responding to data delivery to the MPU 3 when the processing currently being performed by the MPU 4 is completed. When the MPU 3 receives the signal ACK corresponding to the data transfer from the MPU 4, the MPU 3 transmits pixel data DATA to the MPU 4. In this manner, the MPU 3 and the MPU 4 deliver pixel data DATA while executing processing asynchronously.

  Between each of the MPUs 2 to 6, the pixel data DATA is transferred according to the above-described procedure, and the respective MPUs 2 to 6 sequentially perform processing. However, depending on the pixel data, the time required for processing in each of the MPUs 2 to 6 is not equal. For example, for some pixel data, the MTF correction process takes time, and the load on the MPU 4 increases. As a result, the MPU 4 becomes a bottleneck, and the data processing speed of the entire data processing apparatus decreases. .

  In order to avoid this problem, the data processing apparatus according to the present embodiment monitors the processing loads of the MPUs 2 to 6 with the status register 10, and the data flow control unit 9 detects the upstream of the MPU whose processing load has increased. The MPU that executes the process is instructed to execute the process that is executed by the MPU having a heavy load. This will be described in detail.

  FIG. 3 is a flowchart showing the flow of processing performed by the data flow control unit 9. Referring to the figure, data flow control unit 9 refers to status register 10 and monitors the processing load of each MPU 2-6 (step S01). The status register 10 stores the processing time required to process the pixel data sent from each of the MPUs 2 to 6 and the address of the processed pixel data. The data flow control unit looks at the contents of the status register 10. Thus, it is possible to grasp the loads of the MPUs 2 to 6.

  As a result, if there is an MPU with a large processing load (YES in step S02), an MPU that performs a process preceding the MPU with a large load is executed with an MPU with a large load in addition to the currently performed processing. A control signal ON is output so as to continue the processing (step S03). For example, referring to FIG. 1, when the load of MPU 4 that performs MTF correction processing increases, data flow control unit 9 detects that the load of MPU 4 has increased from the state of status register 10, and performs MTF correction. A control signal is output to the MPU 3 that executes the log conversion process, which is the preceding stage of the process, so that the MPT 3 continues the MTF correction process in addition to the log conversion process currently performed by the MPU 3. As a result, the MPU 3 performs the MTF correction process in addition to the log conversion process.

  If there is no MPU with a large processing load (NO in step S02), a control signal OFF indicating that the initial setting process is executed is output to each of the MPUs 2 to 6 (step S04).

  Thereafter, it is determined whether or not the processing has been completed for all the pixel data (step S05). If there is unprocessed pixel data, the above processing is repeated, and if all the pixel data is processed, the processing is performed. Exit.

  In this way, the processing executed by the MPU having increased load can be performed in parallel with the MPU that performs the preceding processing, so that the load can be distributed and the data processing speed of the entire data processing apparatus can be increased. Can be increased.

  When the data flow control unit 9 determines an MPU with a large load (step S02 in FIG. 3), it is performed by referring to the address of data processed by each MPU 2-6.

  FIG. 4 is a diagram illustrating a difference in address value of pixel data executed by each MPU. The image data input to the image input apparatus 1 has an address value for each pixel data, and these address values are given in the order of input to the image input apparatus 1. This is obtained as the address value of the input buffer memory 11 when the image data input to the image input device 1 is stored in the input buffer memory 11. Each of the MPUs 2 to 6 transmits the address value of the pixel data to the status register 10 every time the processing of the pixel data is completed. The data flow control unit 9 determines the address difference (dif_1, dif_2, dif_3) of the pixel data executed by each MPU 2-6 from the address value of the pixel data executed by each MPU stored in the status register 10. , Dif_4). When the calculated address difference becomes smaller than a predetermined set value, it is determined that the load on the MPU preceding the MPU having the reduced address difference has increased. For example, when the address difference dif_2, which is the difference between the address value executed by the MPU 5 that performs gamma correction processing and the address value executed by the MPU 4 that performs MTF correction processing, becomes smaller than a preset threshold value reg_2. Determines that the load on the MPU 4 that performs the MTF correction process, which is the preceding process, has increased.

  The address difference dif_1 indicates an address difference between the MPU 6 that performs binarization processing and the MPU 5 that performs gamma correction, and dif_2 indicates the address difference between the MPU 5 that performs gamma correction processing and the MPU 4 that performs MTF correction processing. Dif_3 indicates an address difference between the MPU 4 that performs the MTF correction process and the MPU 3 that performs the Log conversion process, and dif_4 indicates an address difference between the MPU 3 that performs the Log conversion process and the MPU 2 that performs the SH correction process. Show. When this address difference is small, it indicates that the load on the MPU in the previous stage is large. Further, when the address difference becomes smaller than the threshold value by the data flow control unit 9, it is determined that the load on the preceding MPU has increased. This threshold value is determined for each address difference (dif_1, dif_2, dif_3, dif_4), and is stored in advance in the ROM inside the data flow control unit.

  The reason why the threshold value reg differs between MPUs is as follows. For example, when a matrix operation consisting of a plurality of pixels is performed as in a process using a Laplacian filter in the MTF correction process, a considerable address difference is required. FIG. 5 is a diagram for explaining pixel data when performing an MTF correction process using a 3 × 3 filter. Referring to the figure, when the MTF correction process is performed using a 3 × 3 filter, the log conversion process is completed for all the pixels surrounded by the 3 × 3 matrix centering on the pixel to be processed. Need to be. Therefore, in the MTF correction process, data for one line before and after the pixel to be processed is necessary. Therefore, the log conversion process, which is the previous stage of the MTF correction process, is performed by the address of the pixel to be the target of the MTF correction process. And an address difference of (number of pixels for one line + 1) is required. Considering this, it is necessary to set a threshold value for an address difference between MPU 4 that performs MTF correction processing and MPU 3 that performs Log conversion processing.

  Therefore, the threshold value reg_1 for the address difference dif_1, the threshold value reg_2 corresponding to dif_2, the threshold value reg_3 corresponding to dif_3, and the threshold value reg_4 corresponding to dif_4 are one or more, preferably one. The threshold value reg_2 corresponding to dif_2 may be a threshold value of (number of pixels for one line + 1) or more, preferably (number of pixels for one line + 1).

  FIG. 6 is a flowchart showing the flow of processing performed in each of the MPUs 2 to 6. Referring to the figure, pixel data are captured in MPUs 2-6 (step S11). The MPU 2 takes in the pixel data from the input buffer memory 11, and the MPUs 3 to 6 receive the pixel data from the MPU that performs the previous processing. For example, MPU3 receives pixel data from MPU2.

  Next, it is determined whether or not a control signal is received from the data flow control unit 9 (step S12). The control signal received here is either the control signal ON or the control signal OFF. If the received control signal is the control signal ON (YES in step S12), the subsequent processing program is loaded from the ROM in the data flow control unit 9, and the current processing (initial setting processing) and the subsequent processing are loaded. The two processes are executed (step S14).

  If the control signal ON has not been received, that is, if the control signal OFF has been received (NO in step S12), the currently executed process (initial setting process) is executed (step S13). Thereafter, the processed pixel data is output (step S15). In the MPUs 2 to 5, the processed pixel data is delivered to the MPUs 3 to 6 that execute subsequent processing. For example, the MPU 2 delivers the processed pixel data to the MPU 3. The MPU 6 delivers the processed pixel data to the image output device 7.

  Thereafter, the address of the pixel data and the processing time or processing speed of the pixel data are written in the status register 10 (step S16).

  Then, it is determined whether or not the processing of all the pixel data has been completed (step S17). If the processing has not been completed, the processing from step S10 to step S16 is repeated, and the processing of all the pixel data is completed. When it is finished, the process is finished.

  For example, in the MPU 3, the initial setting process and the subsequent process are the log conversion process, and the subsequent process is the MTF correction process.

  FIG. 7 is a diagram showing processing performed in each of the MPUs 2 to 6 when the data flow control unit 9 determines that the load on the MPU 4 is large in the data processing apparatus according to the present embodiment. Referring to FIG. 7, in MPU 3, in addition to the log conversion process, the MTF correction process is executed. The pixel data flow in this state is the first flow. Pixel data that has been subjected to SH correction processing by the MPU 2 is subjected to Log conversion processing and MTF correction processing by the MPU 3, and then delivered to the MPU 5. Gamma correction processing is performed. As a second flow, the pixel data subjected to the SH correction process in the MPU 2 is subjected only to the log conversion process in the MPU 3 and then delivered to the MPU 4 to be subjected to the MTF correction process, and then delivered to the MPU 5 and subjected to gamma. Correction processing is performed.

  As described above, in the data processing apparatus according to the present embodiment, the load of each of the MPUs 2 to 6 is constantly monitored by the data flow control unit 9 and is currently performed on the MPU preceding the MPU that is determined to have a large load. In addition to the existing processing, the processing performed by the MPU having a large load is also executed in parallel, so that the load is distributed among the MPUs 2 to 6, and as a result, the data processing speed of the entire data processing apparatus is increased. be able to.

  In the present embodiment, the data flow control unit 9 always monitors the load of each of the MPUs 2 to 6, and the MPU that executes the process preceding the process executed by the MPU that is determined to have a large load is currently being used. In addition to the process being performed, the process executed by the MPU having a large load is also executed in parallel. However, the MPU that executes the process subsequent to the process executed by the MPU that has been determined to have a large load is currently being used. In addition to the processing being performed, the processing executed by the MPU having a large load may be executed in parallel. Thus, by changing the processing executed by the MPUs 2 to 6 in the data flow control unit 9, the load can be distributed among the MPUs 2 to 6, and the data processing speed of the entire data processing apparatus can be increased. it can.

  In this case, the process of the data flow control unit 9 is executed by the MPU having a large load in addition to the currently performed process for the MPU performing the subsequent process of the MPU having a large load in step S03 of FIG. The control signal ON is output so as to continue the process (step S03). For example, referring to FIG. 1, when the load of MPU 4 that performs MTF correction processing increases, data flow control unit 9 detects that the load of MPU 4 has increased from the state of status register 10, and performs MTF correction. A control signal is output to the MPU 5 that executes the gamma correction process, which is a process subsequent to the process, so as to perform the MTF correction process in addition to the gamma correction process currently performed by the MPU 5. As a result, the MPU 3 performs MTF correction processing and gamma correction processing.

  On the other hand, in the processing of the MPUs 3 to 6, when the received control signal is the control signal ON in step S13 of FIG. 6, the processing program of the previous stage is loaded from the ROM in the data flow control unit 9 in step 14 to Two processes, the process being performed (initial setting process) and the preceding process, are executed (step S14).

  FIG. 8 shows a state of processing executed by the MPUs 2 to 6 when the data flow control unit 9 determines that the load on the MPU 4 is large in the data processing apparatus in this case. Referring to FIG. 8, in MPU 5, MTF correction processing and gamma correction processing are executed. Also, the pixel data flow in this state is as a first flow. The pixel data subjected to the log conversion process in the MPU 3 is subjected to the MTF correction process in the MPU 4 and then delivered to the MPU 5 for the gamma correction process. Is given. As a second flow, pixel data that has been subjected to log conversion processing by the MPU 3 is transferred to the MPU 5 and subjected to MTF correction processing and gamma correction processing.

[Second Embodiment]
FIG. 9 is a block diagram showing an outline of a data processing apparatus according to the second embodiment. Referring to the figure, a data processing apparatus according to the second embodiment includes an image input apparatus 1 that inputs image data, MPUs 21 to 26 that perform various processes on the input image data for each pixel data, and processing Refer to the image output device 8 that outputs the image data to a recording medium such as paper, the image input device 1, the MPUs 21 to 26, the status register 10 that monitors the operation status of the image output device 8, and the status register 10. A data flow control unit 20 that controls operations of the MPUs 21 to 26, an input buffer memory 11 that temporarily stores image data input by the image input apparatus 1, and an output buffer that temporarily stores image data output from the image output apparatus And a memory 12.

  The MPUs 21 to 25 perform SH correction processing, Log conversion processing, MTF correction processing, gamma correction processing, and binarization processing, respectively, in the initial setting state. The MPU 26 performs no processing in the initial setting state.

  In the data processing apparatus according to the second embodiment, the MPU 26 executes in parallel the processing executed by the MPU that is considered to have a high load among the MPUs 21 to 25 by the data flow control unit 20.

  FIG. 10 is a flowchart showing a flow of processing performed by the data flow control unit 20 in the second embodiment. Referring to the figure, the data flow control unit 20 acquires the address of the pixel data executed by each MPU stored in the status register 10 (step S31). An address difference is obtained from the address value of pixel data executed by each MPU acquired from the status register, and an MPU having a large load is detected from the obtained address difference (step S32). If it is determined that there is an MPU having a large load (YES in step S32), a control signal is output to the MPU 26 so as to perform a process to be executed by the MPU determined to have a large load (step S33).

  On the other hand, if it is determined that there is no MPU having a large load (NO in step S32), a control signal is output to the MPU 26 to be reset (step S34).

  Thereafter, it is determined whether or not all pixel data has been completed (step S35). If there is unprocessed pixel data, the above processing is repeated, and if all pixel data has been processed, the processing is terminated. .

  FIG. 11 is a flowchart showing the flow of processing performed by the MPU 26. Referring to the figure, MPU 26 receives a control signal output from the data flow control unit (step S41). The control signal received here is either a control signal indicating that processing with a large load is performed or a control signal indicating that resetting is performed.

  Next, it is determined whether or not the received control signal is a reset signal (step S42). If the received control signal is a reset signal, reset processing is performed so that no processing is performed (step S44). Proceed to step S47.

  On the other hand, if it is determined that the signal is not a reset signal, that is, if a control signal indicating that a process with a heavy load is to be performed is received (NO in step S42), a program for the process with a heavy load is stored in the data flow control unit. The data is loaded from the ROM 20 and the process is executed (step S43).

  Then, the processed pixel data is output (step S45). In this case, for example, when the processing that is considered to be heavy is binarization processing, the processed pixel data is output to the image output device 8. In the case of other processing, the data is delivered to the MPU that executes the subsequent processing. For example, when the processing that is considered to be heavy is the MTF correction processing, the data is delivered to the MPU 24 that executes the gamma correction processing that is the subsequent processing.

  FIG. 12 is a diagram illustrating processing performed by each of the MPUs 21 to 26 when the data flow control unit 20 determines that the load on the MPU 23 that performs MTF correction processing is large. Referring to the figure, in MPU 26, upon reception of a control signal indicating that the MTF correction processing output from data flow control unit 20 is performed, an MTF correction processing program is loaded from the ROM in data flow control unit 20, and MTF correction is performed. Processing is executed. In this case, there are two pixel data flows: a flow in which pixel data that has undergone log conversion processing in the MPU 22 is delivered to the MPU 23 and a flow in which the pixel data is delivered to the MPU 26. The pixel data delivered to the MPU 23 or MPU 26 is subjected to the MTF correction process and then delivered to the MPU 24.

  As described above, the data processing apparatus according to the second embodiment is provided with the MPU 26 that does not perform any processing in the initial setting state, and is executed by the MPU that is determined to have a large load by the data flow control unit 20. Is executed in parallel by the MPU 26 that does not perform any processing, so that the load on the MPUs 21 to 25 can be distributed by the MPUs 21 to 26, so that the data processing apparatus as a whole can speed up data processing. it can.

[Third Embodiment]
FIG. 13 is a block diagram illustrating an outline of a data processing device according to the third embodiment. The data processing apparatus according to the third embodiment includes an image input apparatus 1 that inputs image data, MPUs 31 to 35 that perform various processes on the input image data for each pixel data, and processed image data on paper. The image output device 8 that outputs to a recording medium such as the image input device 1, the MPUs 31 to 35, the status register 10 that monitors the operation status of the image output device 8, and the operation of the MPUs 31 to 35 with reference to the status register 10 A data flow control unit 30 to be controlled, an input buffer memory 11 that temporarily stores image data input by the image input device 1, an output buffer memory 12 that temporarily stores image data output from the image output device, and each MPU 31 Intermediate buffer memories 13 to 17 for storing the pixel data processed in the above.

  The data processing apparatus according to the third embodiment can temporarily store the pixel data processed by the MPUs 31 to 35 in the corresponding intermediate buffer memories 13 to 17. In an initial setting state, the MPU 31 is set to perform SH correction processing, the MPU 32 performs Log conversion processing, the MPU 33 performs MTF correction processing, the MPU 34 performs gamma correction processing, and the MPU 35 performs binarization processing. The intermediate buffer memory 13 is subjected to SH correction processing, the intermediate buffer memory 14 is subjected to Log conversion processing, the intermediate buffer memory 15 is subjected to MTF correction processing, and the intermediate buffer memory 15 is subjected to MTF correction processing. The memory 16 stores pixel data that has undergone gamma correction processing, and the intermediate buffer memory 17 stores pixel data that has undergone binarization processing.

  FIG. 14 is a flowchart showing the flow of processing performed by the data flow control unit 30 in the third embodiment. Referring to the figure, in data flow control unit 30, the load of each MPU 31-35 is monitored from the address value of the pixel data processed by each MPU 31-35 stored in status register 10 (step S51). ). It is determined whether or not there is an MPU having a large load from the acquired address value of the pixel data executed by each MPU 31 to 35 (step S52).

  When it is determined that there is an MPU with a large load, a control signal is output to the MPU that executes a process subsequent to the process with a large load so that the process with the large load is performed ( Step S53). On the other hand, when it is determined that there is no MPU with a large load (NO in step S52), a control signal is output to reset all the MPUs (step S54).

  Then, it is determined whether or not the processing has been completed for all the pixel data (step S55). If there is unprocessed pixel data, the above processing is repeated and the processing for all the pixel data is completed. If so, the process ends.

  FIG. 15 is a flowchart showing the flow of processing performed by the MPUs 31 to 35 in the third embodiment. Referring to the figure, MPUs 31 to 35 receive a control signal output from data flow control unit 30 (step S61). The control signal received here is either a control signal indicating that a process with a heavy load is performed or a control signal indicating reset.

  It is determined whether or not the control signal received in step S70 is a control signal instructing reset (step S62). If it is not a control signal for instructing resetting, it is a control signal for instructing execution of processing with a heavy load. Therefore, a processing program with a heavy load is loaded from the ROM in the data flow control unit 30, and the loaded program is executed. (Step S64).

  If the received control signal is a control signal for instructing reset (YES in step S62), an initial setting process is executed (step S63). Here, when a control signal instructing execution of a heavy load process has been received and a heavy load process has already been executed, if a control signal indicating a reset is received, the heavy load process is executed. Stop and resume execution of the initial setting process. For example, when it is determined that the load on the MPU 33 that performs the MTF correction process is large and a control signal is output to the MPU 34 to perform the MTF correction process, the MPU 34 stops the execution of the gamma correction process that is the initial setting process. Then, the MTF correction process is executed. Thereafter, when the load on the MPU 33 decreases, the data flow control unit 30 outputs a control signal for instructing the MPU 34 to reset. The MPU 34 stops the MTF correction process and restarts the gamma correction process, which is the initial setting process, when receiving the control signal instructing the reset.

  Next, the processed pixel data is output (step S65). Pixel data is output to the intermediate buffer memories 13-17. Since the pixel data to be stored is determined in each of the intermediate buffer memories 13 to 17, for example, when the MTF correction process is performed by the MPU 34, the pixel data subjected to the MTF correction process is output to the intermediate buffer memory 15. Is done.

  Next, the address of the pixel data processed by the MPUs 31 to 35 and the processing time or processing speed required to process the pixel data are written in the status register 10 (step S66). Thereafter, it is determined whether or not the processing has been completed for all the pixel data (step S67). If there is unprocessed pixel data, the above processing is repeated, and the processing is completed for all the pixel data. If so, the process ends.

  FIG. 16 is a diagram illustrating a state of processing executed by the MPUs 31 to 35 when the data flow control unit 30 determines that the load on the MPU 33 is large. Referring to FIG. 16, MPU 34 loads the MTF correction processing program from the ROM in data flow control unit 30 in response to the reception of the control signal instructing the execution of the preceding process output from data flow control unit 30. Correction processing is executed. Similarly, the MPU 35 loads a gamma correction processing program from the ROM in the data flow control unit 9 and receives the control signal instructing execution of the preceding process output from the data flow control unit, and the gamma correction processing is executed. The At this time, the MPU 34 reads the pixel data subjected to the log conversion process from the intermediate buffer memory 14, performs the MTF correction process, and writes the pixel data after the MTF correction process to the intermediate buffer memory 15. Further, the MPU 35 reads the pixel data that has been subjected to the MTF correction processing from the intermediate buffer memory 15, performs the gamma correction processing, and writes the pixel data after the gamma correction processing to the intermediate buffer memory 16.

  As described above, the data processing apparatus according to the third embodiment is provided with the intermediate buffer memories 13 to 17 for storing the processed pixel data in each of the MPUs 31 to 35, and the data flow control unit 20 has a heavy load. When it is determined that there is an MPU, the previous process is executed by the MPU that executes the subsequent process of the heavy load process, so that the process can be completed as quickly as the previous process. The data processing speed of the entire apparatus can be increased. Further, since the process can be completed as quickly as the preceding process, new image data, for example, image data of the next page can be input quickly.

  Furthermore, since the intermediate buffer memories 13 to 18 for storing the results of executing the processing in each MPU are provided, it is possible to absorb the difference in processing speed that is different among the MPUs 31 to 35 that execute the processing asynchronously, and Even if the contents of the processing executed by the MPUs 31 to 35 are changed, the type of pixel data stored in the intermediate buffer memories 13 to 18 does not change, so the contents of the processing executed by the MPUs 31 to 35 are easily changed. be able to.

[Fourth Embodiment]
FIG. 17 is a block diagram illustrating an outline of a data processing device according to the fourth embodiment. Referring to the figure, a data processing apparatus according to the fourth embodiment includes an image input apparatus 1 that inputs image data, MPUs 41 to 46 that perform various processes on the input image data for each pixel data, and processing Refer to the image output device 8 that outputs the image data to a recording medium such as paper, the image input device 1, the MPUs 41 to 46, the status register 10 that monitors the operation status of the image output device 8, and the status register 10. A data flow control unit 40 that controls the operation of the MPUs 41 to 46, an input buffer memory 11 that temporarily stores image data input by the image input apparatus 1, and an output buffer that temporarily stores image data output from the image output apparatus And a memory 12.

  The MPUs 41 to 45 perform SH correction processing, area determination processing, color conversion processing, MTF correction processing, and gamma correction processing, respectively, in the initial setting state. The MPU 46 does not perform any processing in the initial setting state.

  In the data processing apparatus according to the fourth embodiment, the MPU 46 executes in parallel the processing executed by the MPU that is determined to have a large load among the MPUs 41 to 45 by the data flow control unit 40. The data processing apparatus according to the fourth embodiment is different from the data processing apparatus according to the above-described embodiments in that color image data is handled and that area determination processing is added to processing performed on pixel data. Different.

  The area discrimination process is to perform a predetermined process on a plurality of pixel data included in a predetermined area including the image data to be processed, thereby determining an attribute of the predetermined area and to which the pixel data to be processed belongs. This is processing for determining the attribute of the area. Examples of the attributes of the predetermined area include a character area, a line drawing area, and a background area. This area determination processing is performed by a known method, for example, by using a 3 × 3 matrix and comparing pixel data existing in the matrix.

  Then, the time required for the subsequent processing, for example, the MTF correction processing, changes for the pixel data whose attributes are determined by the region determination processing. For example, when the attribute of the pixel data is determined to be the character attribute or the line drawing attribute by the area determination process, the time required for the MTF correction process becomes longer than that when the attribute is determined to be the background attribute. As a result, the load on the MPU that executes the MTF correction process increases. Therefore, it is possible to predict the load of the MPU that executes the subsequent processing (Log conversion, MTF correction, gamma correction, binarization) based on the result of the region determination processing.

  In the data processing apparatus according to the fourth embodiment, the processing executed by the MPUs 41 to 46 is changed depending on the attribute of the pixel data determined by the region determination processing.

  FIG. 18 is a flowchart showing the flow of processing performed by the data flow control unit 40 in the fourth embodiment. Referring to the figure, the data flow control unit 40 acquires the result of the area determination process executed by the MPU 42 (step S71). It is determined from the result of the region determination process of the acquired pixel data whether the pixel data has a character attribute or a line drawing attribute (step S72). If the character attribute or line drawing attribute is determined, a control signal is output to the MPU 46 to perform MTF correction processing (step S73). On the other hand, if the character attribute or line drawing attribute is not determined (NO in step S72), a control signal is output to the MPU 46 to be reset (step S74). Thereafter, it is determined whether or not the processing of all the pixel data has been completed (step S75). If there is unprocessed pixel data, the above processing is repeated and the processing has been completed for all the pixel data. If so, the process ends.

  FIG. 19 is a flowchart showing the flow of processing performed by the MPU 46 in the fourth embodiment. Referring to the figure, MPU 46 receives a control signal output from data flow control unit 40 (step S81). The control signal received here is either a control signal indicating execution of the MTF correction process or a control signal indicating resetting.

  Next, it is determined whether or not the received control signal is a reset signal (step S82). If the received control signal is a reset signal, reset processing is performed so that no processing is performed (step S84). Proceed to step S87.

  On the other hand, when it is determined that the signal is not a reset signal, that is, when a control signal indicating that processing with a large load is performed is received (NO in step S82), the program for MTF correction processing is stored in the ROM in the data flow control unit 40. And the process is executed (step S83). Then, the processed pixel data is output (step S85). In this case, the pixel data is handed over to the MPU 45 that executes processing subsequent to the MTF correction processing. Next, the address of pixel data processed by the MPU 46 and the processing time or processing speed required for processing the pixel data are written into the status register 10 (step S86).

  Thereafter, it is determined whether or not the processing has been completed for all the pixel data (step S87). If there is unprocessed pixel data, the above processing is repeated, and the processing is completed for all the pixel data. If so, the process ends.

  FIG. 20 is a diagram illustrating a process performed by the MPU 46 when it is determined that the pixel data processed by the MPU 42 that performs the area determination process has a character attribute or a line drawing attribute. Referring to the figure, MPU 46 receives the control signal indicating the execution of the MTF correction process output from data flow control unit 40, and executes the MTF correction process. In this case, there are two flows of pixel data: a flow in which pixel data subjected to color conversion in the MPU 43 is delivered to the MPU 44 and a flow in which the pixel data is delivered to the MPU 46. The pixel data delivered to the MPU 44 or MPU 46 is subjected to the MTF correction process and then delivered to the MPU 45 that executes the gamma correction process.

  When the pixel data is determined to be a character attribute or a line drawing attribute in the area determination process, the pixel data in the vicinity of the pixel data usually have the same attribute. Therefore, the process executed by the MPUs 41 to 46 shown in FIG. 20 continues while the pixel data processed by the MPU 42 that executes the area determination process is determined as the character attribute or the line drawing attribute. When it is determined that the pixel data is not the character attribute or the line drawing attribute by the area determination process, the MPUs 41 to 46 execute an initial setting process. That is, the MPU 46 enters a state where no processing is performed.

  As described above, the data processing apparatus according to the fourth embodiment does not perform the process in the initial setting state when the MPU 42 that executes the area determination process determines that the pixel data is the character attribute or the line drawing attribute. Thus, since the MTF correction processing that is predicted to have a large load is performed, the loads in the MPUs 41 to 45 can be distributed by the MPUs 41 to 46. As a result, data processing can be performed at high speed by dynamically changing the processing executed by the MPUs 41 to 46 according to the attributes of data input to the data processing device.

[Fifth Embodiment]
FIG. 21 is a block diagram illustrating an outline of a data processing device according to the fifth embodiment. Referring to the figure, a data processing apparatus according to a fifth embodiment includes an image input apparatus 1 that inputs image data, MPUs 51 to 56 that perform various processes on the input image data for each pixel data, and processing Refer to the image output device 8 that outputs the image data to a recording medium such as paper, the image input device 1, the MPUs 51 to 56, the status register 10 that monitors the operation status of the image output device 8, and the status register 10. A data flow control unit 50 that controls the operation of the MPUs 51 to 56, an input buffer memory 11 that temporarily stores image data input by the image input apparatus 1, and an output buffer that temporarily stores image data output from the image output apparatus A memory 12 and intermediate buffer memories 13 to 18 for storing pixel data processed by the MPUs 51 to 56 are included.

  The data processing apparatus according to the fifth embodiment can temporarily store the pixel data processed by the MPUs 51 to 56 in the corresponding intermediate buffer memories 13 to 18. In the initial setting state, the MPU 51 performs SH correction processing, the MPU 52 performs area determination processing, the MPU 53 performs Log conversion processing, the MPU 54 performs MTF correction processing, the MPU 55 performs gamma correction processing, and the MPU 56 performs binarization processing. Is set as follows.

  The intermediate buffer memory 13 is subjected to SH correction processing, the intermediate buffer memory 14 is subjected to area discrimination processing, the intermediate buffer memory 15 is subjected to Log conversion processing, and the intermediate buffer memory 15 is subjected to Log conversion processing. The memory 16 stores pixel data that has undergone MTF correction processing, the intermediate buffer memory 17 stores pixel data that has undergone gamma correction processing, and the intermediate buffer memory 18 stores pixel data that has undergone binarization processing. .

  Since the area determination processing has been described in the fourth embodiment, description thereof will not be repeated here. The data processing apparatus according to the fifth embodiment predicts the load of the MPU that executes the subsequent processing (Log conversion, MTF correction, gamma correction, binarization) based on the result of the region determination processing, thereby reducing the MPU 51 to MPU 51. The processing executed in 56 is dynamically changed.

  FIG. 22 is a flowchart showing the flow of processing performed by the data flow control unit 50 in the fifth embodiment. Referring to the figure, the data flow control unit 9 acquires the result of the area determination process executed by the MPU 52 (step S90). As a result of the area determination processing acquired in step S90, it is determined whether or not the processed pixel data has a character attribute or a line drawing attribute (step S91). If the pixel data is determined to be a character attribute or a line drawing attribute (YES in step S91), the MPU 55, 56 that executes the subsequent process (gamma correction process, binarization process) of the MTF correction process is used. A control signal is output to execute the process. That is, a control signal is output to the MPU 55 that executes the gamma correction process so as to execute the MTF correction process, which is the preceding stage of the gamma correction process, and binary for the MPU 56 that executes the binarization process. A control signal is output so as to perform a gamma correction process that is a process preceding the conversion process.

  On the other hand, if the pixel data is not determined to be a character attribute or a line drawing attribute (NO in step S91), a control signal is output to reset the MPU 55, 56 (step S93).

  Thereafter, it is determined whether or not processing of all pixel data has been completed (step S94). If there is unprocessed pixel data, the above-described processing is repeated, and processing has been completed for all pixel data. Ends the process.

  FIG. 23 is a flowchart showing a flow of processing performed by the MPUs 51 to 56 in the fifth embodiment. Referring to the figure, MPUs 55 and 56 receive a control signal output from data flow control unit 40 (step S101). The control signal received here is either a control signal indicating execution of the previous stage process or a control signal indicating reset.

  If the received control signal is not a control signal indicating reset (NO in step S102), the received control signal is a control signal indicating execution of the preceding process, so that the MPUs 55 and 56 are included in the data flow control unit 50. The previous processing program is loaded from the ROM, and the MTF correction process is executed (step S84). The MPU 55 loads an MTF correction processing program, and the MPU 56 loads a gamma correction processing program. On the other hand, if the received control signal is a control signal indicating reset (YES in step S102), a reset process is performed to execute an initial setting process (step S103).

  When the processing is completed, processed pixel data is output (step S106). The MPUs 55 and 56 write the pixel data to the intermediate buffer memory 16 when executing the MTF correction process, and write the pixel data to the intermediate buffer memory 17 when executing the gamma correction process. If so, the pixel data is written into the intermediate buffer memory 18.

  Next, the address of the pixel data processed by the MPUs 55 and 56 and the processing time or processing speed required to process the pixel data are written into the status register 10 (step S106). Thereafter, it is determined whether or not the processing has been completed for all the pixel data (step S107). If there is unprocessed pixel data, the above processing is repeated, and the processing is completed for all the pixel data. If so, the process ends.

  In the data processing apparatus according to the present embodiment, an initial setting processing program is loaded by the MPUs 51 to 56, and processing is executed for each pixel data. For the MPU 55 and the MPU 56, initially, the initial setting processing program is loaded from the ROM in the data flow control unit 50 and executed. However, the control signal instructing the execution of the preceding process is received from the data flow control unit 50. In this case, the program for the previous process is loaded from the ROM in the data flow control unit 50, and the program is executed.

  FIG. 24 is a diagram showing processing performed by the MPUs 51 to 56 when the data flow control unit 50 determines that the pixel data is a character attribute or a line drawing attribute from the MPU 52. Referring to the figure, MTF correction processing is executed in MPU 55, and gamma correction processing is executed in MPU 56. At this time, in the MPU 55, the pixel data to be processed is read from the intermediate buffer memory 15, and the data after the MTF correction processing is written to the intermediate buffer memory 16. In the MPU 56, the pixel data to be processed is read from the intermediate buffer memory 16, and the pixel data after the gamma correction processing is written to the intermediate buffer memory 17.

  As described above, in the data processing apparatus according to the fifth embodiment, the MPU 52 that performs the area determination process determines whether the pixel data has the character attribute or the line drawing attribute, and the determination result is sent to the data flow control unit 50. . In the data flow control unit 50, when the pixel data is determined to be a character or line drawing attribute based on the determination result sent from the MPU 52, the MPU 55 performs the MTF correction process and the MPU 56 executes the gamma correction process. Control signals are output to the MPU 55 and the MPU 56. When it is determined that the pixel data does not have the character attribute or the line drawing attribute, a signal indicating reset is output to the MPU 55 and the MPU 56, and the MPU 55 performs gamma correction processing and the MPU 56 performs binarization processing.

  As described above, the data processing apparatus according to the fifth embodiment predicts the load of the MPU that performs subsequent processing by determining the attribute of the pixel data to be processed, and responds to the predicted load. Since the process executed by each MPU is dynamically changed, the data processing speed of the entire data processing apparatus can be improved.

  Moreover, since the intermediate buffer memories 13 to 18 for storing the results of executing the processing in each MPU are provided, it is possible to absorb the difference in processing speed that is different between the MPUs 51 to 56 that execute the processing asynchronously, and Even if the contents of the processing executed by the MPUs 51 to 56 are changed, the type of pixel data stored in the intermediate buffer memories 13 to 18 does not change, so the contents of the processing executed by the MPUs 51 to 56 are easily changed. be able to.

[Sixth Embodiment]
FIG. 25 is a block diagram illustrating an outline of a data processing device according to the sixth embodiment. Referring to the figure, a data processing apparatus according to the sixth embodiment includes an image input apparatus 1 that inputs image data, MPUs 61 to 65 that perform various processes on the input image data for each pixel data, and processing Refer to the image output device 8 that outputs the image data to a recording medium such as paper, the image input device 1, the MPUs 61 to 65, the status register 10 that monitors the operation status of the image output device 8, and the status register 10. A data flow control unit 60 that controls the operation of the MPUs 61 to 65, an input buffer memory 11 that temporarily stores image data input by the image input apparatus 1, and an output buffer that temporarily stores image data output from the image output apparatus A memory 12 and intermediate buffer memories 13 to 17 for storing pixel data processed by the MPUs 61 to 65 are included.

  The data processing apparatus according to the sixth embodiment can temporarily store the pixel data processed by the MPUs 61 to 65 in the corresponding intermediate buffer memories 13 to 17. In the initial setting state, the MPU 61 is set to perform SH correction processing, the MPU 62 performs Log conversion processing, the MPU 63 performs MTF correction processing, the MPU 64 performs gamma correction processing, and the MPU 65 performs binarization processing.

  The intermediate buffer memory 13 is subjected to SH correction processing, the intermediate buffer memory 14 is subjected to Log conversion processing, the intermediate buffer memory 15 is subjected to MTF correction processing, and the intermediate buffer memory 15 is subjected to MTF correction processing. The memory 16 stores pixel data that has undergone gamma correction processing, and the intermediate buffer memory 17 stores pixel data that has undergone binarization processing.

  FIG. 26 is a flowchart showing the flow of processing performed by the MPUs 61 to 65 in the sixth embodiment. In order to simplify the explanation, the processing in the MPU 61 and the MPU 62 for transferring data is shown in the form of explaining at the same time. Actually, the MPU 61 and the MPU 62 execute processing asynchronously.

  Referring to FIG. 26, the MPU 61 executes the SH correction process (Process A) for each pixel data (Step S111). At this time, the data flow control unit 60 monitors the loads on the MPU 61 and the MPU 62, and compares the load of the SH correction process performed by the MPU 61 with the load of the log conversion process (process B) performed by the MPU 62 (step S112). ) When the SH correction processing load is smaller than the Log conversion processing load, it is determined whether or not there is a storage capacity left in the intermediate buffer memory 13 (step S113). If the memory capacity remains in the intermediate buffer memory 13 (YES in step S113), the pixel data subjected to the SH correction processing executed by the MPU 61 is written in the intermediate buffer memory 13 (step S114). The pixel data stored in the intermediate buffer memory 13 is read by the MPU 62 that performs the next processing log conversion process (step S115), and the log conversion process is performed by the MPU 62 (step S116).

  On the other hand, when the load of the SH correction process is not smaller than the load of the Log conversion process (NO in Step S112), the pixel data after the SH correction process executed by the MPU 61 is directly delivered to the MPU 62, and the Log conversion process is performed by the MPU 62. (Step S116).

  Next, it is determined whether or not all the pixel data for one page has been processed (step S117). If there is unprocessed pixel data, the above processing is repeated and the processing of all the pixel data is completed. If so, it is determined whether or not the pixel data subjected to the SH correction processing executed by the MPU 61 is stored in the intermediate buffer memory 13 (step S118). When pixel data that has undergone SH correction processing is stored in the intermediate buffer memory 13 (NO in step S118), the data flow control unit 60 outputs a control signal that instructs the MPU 61 to perform log conversion processing. In response to receiving this control signal, the MPU 61 loads the log conversion processing program from the ROM in the data flow control unit 60 and executes the log conversion processing (steps S119 and S120). At this time, the same log conversion processing is performed in parallel in the MPU 61 and the MPU 62.

  The MPU 61 reads the pixel data from the intermediate buffer memory 13 (step S119), executes the log conversion process (step S120), and then stores the pixel data after the log conversion process in the intermediate buffer memory 14 (step S121).

  In parallel with the log conversion processing performed by the MPU 61, the pixel data is read from the intermediate buffer memory 13 by the MPU 62 (step S122), and after the log conversion processing is performed (step S123), the pixel data after the log conversion processing is stored in the intermediate buffer. It is written in the memory 14 (step S124).

  In this way, the same log conversion processing is executed in parallel by the MPU 61 and the MPU 62, and this parallel processing is repeated until there is no pixel data stored in the intermediate buffer memory 13.

  FIG. 27 is a diagram for explaining data transfer between the MPU 61 and the MPU 62 when the load on the MPU 61 is equal to or larger than the load on the MPU 62. Referring to the figure, the pixel data subjected to the SH correction process by MPU 61 is directly transferred to MPU 62 without being stored in intermediate buffer memory 13. This is because the MPU 61 has a larger load, and when the MPU 61 finishes processing one pixel data, the MPU 62 ends the processing and is in a waiting state.

  FIG. 28 is a diagram for explaining data transfer between MPU 1 and MPU 2 when the load on MPU 61 is smaller than the load on MPU 62. Pixel data that has been subjected to SH correction processing by the MPU 1 is stored in the intermediate buffer memory 13 without being directly delivered to the MPU 62. By doing in this way, MPU61 which performs SH correction process with small load can perform SH correction process, without synchronizing with the process of MPU62.

  FIG. 29 is a diagram for explaining processing executed by the MPU 61 and the MPU 62 and a flow of pixel data when the SH correction processing is completed in the MPU 61 and pixel data after the SH correction processing is stored in the intermediate buffer memory 13. FIG. Referring to the drawing, as described above, when the SH correction process is completed in MPU 61 and pixel data after the SH correction process is stored in intermediate buffer memory 13, the same Log conversion process is performed in parallel in MPU 61 and MPU 62. And executed. In the MPU 61, data is read from the intermediate buffer memory 13, subjected to log conversion processing, and then the processed pixel data is written into the intermediate buffer memory 14. In the MPU 2, data is read from the intermediate buffer memory 13, subjected to log conversion processing, and then the processed data is delivered to the next MPU.

  As described above, in the data processing device according to the sixth embodiment, the intermediate buffer memories 13 to 17 that store the processed pixel data are provided for the MPUs 61 to 65, and the load on the MPU that executes the subsequent processing is large. In this case, the processed pixel data is stored in the intermediate buffer memories 13 to 17 without being directly transferred to the subsequent processing. If the pixel data is still in the intermediate buffer memories 13 to 17 even if the previous processing is completed for all the pixel data, 2 is added to the pixel data stored in the intermediate buffer memories 13 to 17. Since the subsequent processing is executed in parallel by one MPU, the processing can be completed as quickly as the previous processing, and the data processing speed of the entire data processing apparatus can be increased. Further, since the process can be completed as quickly as the preceding process, new image data, for example, image data of the next page can be input quickly.

  Furthermore, since the intermediate buffer memories 13 to 17 for storing the results of executing the processing in each MPU are provided, it is possible to absorb the difference in processing speed that is different between the MPUs 61 to 65 that execute the processing asynchronously, and Even if the contents of the processing executed by the MPUs 61 to 65 are changed, the type of pixel data stored in the intermediate buffer memories 13 to 17 does not change, so the contents of the processing executed by the MPUs 61 to 65 are easily changed. be able to.

  The MPU described above may be replaced with a plurality of devices. In addition, the processing performed in the data flow control unit, the status register and each MPU described above, for example, the processing procedure shown in FIGS. 3, 10, 14, 18, and 22 for the data flow control unit, and the MPU The processing procedures shown in FIGS. 6, 11, 15, 19, 23, and 26 can be described by a program that causes a computer to execute the processing procedures. When the data flow control unit, the status register, and the program executed by each MPU are described by a program for causing a computer to execute the invention, the invention can be understood as a computer-readable recording medium on which the program is recorded. .

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram which shows the outline of the data processor in 1st Embodiment. It is a figure for demonstrating the procedure of delivery of pixel data between MPU which performs the process of a front | former stage, and MPU which performs the process of a back | latter stage. It is a flowchart which shows the flow of the process performed in the data flow control part 9 in 1st Embodiment. It is a figure for demonstrating the address of the pixel data processed with MPU, and its difference. It is a figure for demonstrating the pixel data used for a MTF correction process. It is a flowchart which shows the flow of the process performed by MPU2-6 in 1st Embodiment. It is a 1st block diagram which shows the process performed by MPU2-6 when MPU with a heavy load is detected in the data flow control part 9. FIG. It is a 2nd block diagram which shows the process performed by MPU2-6 when MPU with a heavy load is detected in the data flow control part 9. FIG. It is a block diagram which shows the outline of the data processor in 2nd Embodiment. It is a flowchart which shows the flow of the process performed in the data flow control part 20 in 2nd Embodiment. It is a flowchart which shows the flow of the process performed by MPU26 in 2nd Embodiment. It is a block diagram which shows the process performed by MPU21-26 when MPU with a heavy load is detected in the data flow control part 20 in 2nd Embodiment. It is a block diagram which shows the outline of the data processor in 3rd Embodiment. It is a flowchart which shows the flow of the process performed in the data flow control part 30 in 3rd Embodiment. It is a flowchart which shows the flow of the process performed by MPU31-35 in 3rd Embodiment. It is a block diagram which shows the content of the process performed by MPU31-35 when MPU with a heavy load is detected in the data flow control part 30 in 3rd Embodiment. It is a block diagram which shows the outline of the data processor in 4th Embodiment. It is a flowchart which shows the flow of the process performed in the data flow control part 40 in 4th Embodiment. It is a flowchart which shows the flow of the process performed by MPU46 in 4th Embodiment. It is a block diagram which shows the process performed by MPU46 when MPU with a heavy load is detected in the data flow control part 40 in 4th Embodiment. It is a block diagram which shows the outline of the data processor in 5th Embodiment. It is a flowchart which shows the flow of the process performed in the data flow control part 50 in 5th Embodiment. It is a flowchart which shows the flow of the process performed by MPU51-56 in 5th Embodiment. It is a block diagram which shows the process performed by MPU51-56 when MPU with a heavy load is detected in the data flow control part 50 in 5th Embodiment. It is a block diagram which shows the outline of the data processor in 6th Embodiment. It is a flowchart for demonstrating the process and data delivery which are performed by MPU61-65 in 6th Embodiment. It is a block diagram for demonstrating delivery of data when the load of MPU61 in 6th Embodiment is equal to or larger than the load of MPU62. It is a block diagram for demonstrating delivery of data when the load of MPU61 in 6th Embodiment is smaller than the load of MPU62. Processing performed by the MPU 61 and the MPU 62 and data transfer when the SH correction processing-completed pixel data is stored in the intermediate buffer memory 13 after the SH correction processing is completed in the MPU 61 in the sixth embodiment will be described. It is a block diagram for. It is a block diagram which shows the outline of the conventional data processor. It is a block diagram for demonstrating the asynchronous process performed with a some process block.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Image input device, 2-6 MPU, 8 Image output device, 9 Data flow control part, 10 Status register, 11 Input buffer memory, 12 Output buffer memory, 13 Image data bus, 14, 15 System bus

Claims (6)

A data processing system for performing a series of processes asynchronously on a plurality of input data input serially,
A plurality of processing units for executing each of the plurality of processes;
The plurality of processes include an attribute determination process for detecting an attribute for each of the plurality of input data,
A data processing system comprising: an operation control unit that switches processing to be executed by the plurality of processing units according to the attribute detected for each of the plurality of input data by the attribute discrimination processing. The operation control means includes a prediction means for predicting a load of the plurality of processes,
The processing unit that executes the immediately preceding process immediately before the load process for which the load is predicted to be large by the predicting unit switches the process to be executed so as to execute the two processes of the immediately preceding process and the load process. The data processing system according to claim 1. The operation control means includes a prediction means for predicting a load of the plurality of processes,
The processing unit that executes the immediately following process immediately after the load process that is predicted to have a large load by the predicting unit switches the process to be executed so as to execute the two processes of the load process and the immediately following process. The data processing system according to claim 1. The plurality of processing units includes at least one preliminary processing unit that is larger than the number of the plurality of processes and that does not execute any of the plurality of processes before the process is switched by the operation control unit.
The operation control means includes a prediction means for predicting a load of the plurality of processes, and the preliminary processing unit switches a process to be executed so as to execute a load process in which the load is predicted to be large by the prediction means. The data processing system of claim 1, wherein A storage unit that stores a result of processing performed by each of the plurality of processing units;
The operation control means includes a prediction means for predicting loads of the plurality of processes, and a processing unit that executes a process subsequent to the load process predicted to have a large load by the prediction means executes the load process. The data processing system according to claim 1, wherein the processing to be executed is switched.   The plurality of processing units deliver the input data after executing the self processing to a processing unit that executes processing immediately after self processing executed by the self among the plurality of processing. The data processing system according to claim 1.

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