JP2005167506A - Buffer control device and control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid the steady deterioration of transmission quality regarding a buffer control device and a control device for passing an ATM cell to an STM network as a row of frames. <P>SOLUTION: The buffer control device comprises a writing means for cyclically writing cell content to the storage region of a buffer memory individually corresponding to the destination information of a cell that is given successively via the ATM network, and a reading means for reading the content in the storage region for passing to the STM network as an STM signal. The writing means is composed by setting a succeeding storage region to be written to a storage region in which the separation becomes the range, when the separation between the storage region for writing at the storage region corresponding to the destination information and the storage region read by a reading means is within a prescribed range for each destination information. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a buffer control device and a control device that take in a cell given from an ATM network and deliver the content of the cell to a STM network as a sequence of frames arranged in a time slot corresponding to the destination of the cell.

  In recent years, second-generation mobile communication systems are in a tight situation due to a significant increase in the number of subscribers, and therefore migration and integration to IMT2000 and the like have been promoted. In addition, in a third generation mobile communication system such as IMT2000, an ATM exchange system suitable for realizing an integrated exchange and transmission of not only a voice system but also various data systems is applied instead of the STM exchange system. Thus, an inter-network interface between these STM network and ATM network is achieved.

FIG. 5 is a diagram illustrating a configuration example of a third generation mobile communication system.
In the figure, single or plural terminals 20-1 to 20-n are located in any one of radio zones 22-1 to 22-N individually formed by radio base stations 21-1 to 21-N. The radio base stations 21-1 to 21-N are connected to the base station control station 24 via communication links 23-1 to 23-N, respectively. The base station control station 24 is connected to the Internet 41 and the public telephone network 42 via a core network 30 including the following elements.
A mobile switch 31 that is connected to the base station control station 24 via a communication link and to which the ATM switching system is applied.
A gateway switch 32 that corresponds to the upper level of the mobile switch 31 and that uses the ATM switching system and is connected to the Internet 41 described above.
CLAD (Cell Assembler and Disassembler) 33 connected to a specific route of the gateway exchange 32 and a public telephone network 42 which is an STM network
In the following, for the matters common to the terminals 20-1 to 20-n, the subscript “c” indicating that it can correspond to any of the subscript numbers “1” to “n” is denoted by “20”. A supplementary character “C” which means that it can correspond to any one of the suffix numbers “1” to “N” for items common to the radio base stations 21-1 to 21-N. Is added to the code “21”.

  In the mobile communication system having such a configuration, the radio base station 21-C forming the radio zone 22-C in which the terminal 20-c is located controls the channel control related to the call generated in the terminal 20-c. Under the leadership of the station 24. The mobile switch 31 performs call processing for the corresponding call by coordinating with such a base station control station 24, and the gateway switch 32 switches the call by appropriately coordinating with the mobile switch 31 and the CLAD 33. I do.

In the process of these call processing and gateway exchange, the CLAD 33 performs the following processing.
A signal delivered from the public telephone network 42 as a frame sequence (hereinafter referred to as “STM signal”) has user data arranged in a predetermined format for each time slot corresponding to a predetermined destination, and CLAD 33 Each user data is converted into a cell string compliant with ATM advanced layer 1 (hereinafter referred to as “AAL1”) and transferred to the gateway exchange 32 (the ATM exchange system is applied as described above).
A cell sequence that is delivered from the gateway exchange 32 and that conforms to the above-described AAL1 is also converted into an STM signal and delivered to the public telephone network 42 as an STM signal.

Further, the STM signal delivered to the public telephone network 42 is generated as follows by the cell receiving unit 33R, the buffer memory 33B and the frame transmitting unit 33T which are provided in the CLAD 33 and connected in cascade as shown in FIG. .
In the following, the multiplicity of such an STM signal is “2048”, and the size of the storage area of the buffer memory 33B is 524288 (= 256 frames × 2048) bytes as shown in FIG. .

The gateway exchange 32 sequentially outputs cells compliant with AAL1 (hereinafter simply referred to as “cells”) at a constant cycle.
Each time such a cell is given, the cell receiving unit 33R specifies the time slot of the destination of the STM line based on the header information of the cell, and the hour for each time slot in the storage area of the buffer memory 33B. User data is cyclically written in the storage area indicated by the write address (FIG. 7 (1)) assigned in the order of the series.

  The frame transmission unit 33T includes, in the storage area of the buffer memory 33B, all of the frames indicated by the read pointer (FIG. 7 (2)) cyclically given under area management and included in the frame indicated as the STM signal. The contents of the storage area corresponding to the time slot are read at a constant speed (FIG. 7 (3)), and these contents are sequentially converted into STM signals and delivered to the public telephone network.

The size of the storage area of the buffer memory 33B is set in advance to a value that satisfies the following conditions.
The “cell interval fluctuation” is large enough to be compensated for within the quality guaranteed under the ATM switching system applied to the gateway switch 32 and the mobile switch 31.
-For voice-related speech signals, the average value T of the time that elapses between the time when the contents of any storage area are written and the time when they are read is shortened to the extent that the reduction in real time due to transmission delay is allowed. .

Note that such an average value T is a cell arrival time fluctuation (hereinafter referred to as “fluctuation guarantee time”) τ seconds at which desired transmission quality is guaranteed in an ATM network, and a frequency of a frame generated as an STM signal. For example, when the fluctuation guarantee time τ is 10 milliseconds and the frame frequency f is 8 kilohertz, the time series in the STM network It is a time (= 10 milliseconds) for 80 (= 10 × 10 ⁻³ × 8 × 10 ³ ) frames successively connected.

Therefore, for example, even when a subsequent cell arrives with a delay of 10 milliseconds, an abnormal overflow or underflow does not occur in the difference between the write address and the read address of the buffer memory 33B. The frame transmitting unit 33T can transmit all of the cells that arrived late in this way.
In addition, measures against cell loss or reversal of cell arrival order in the ATM network are included in the header of each cell by a method compliant with Fast algorithm specified in ITU-TI363.1 APPENDIX III. This is realized by monitoring the sequence number SC (Sequence Counter).

That is, the cell receiving unit 33R performs the following process when the link of the call that has occurred is established.
Discard the first received cell and store the SC at the same time.
Confirm that the SC of the second and subsequent received cells is increased by 1 from the SC of the first cell, and the user data is stored in the storage area indicated by the write address in the storage area of the buffer memory 33B. Is stored.
-Further, for subsequent cells, user data is stored in a storage area indicated by a write address subsequent to the address of the storage area in which the user data included in the preceding cell is stored in the storage area of the buffer memory 33B. And two SCs for which writing has been completed in advance are held.
• If cells are lost or the order of arrival of cells is reversed and the retained SC increment is greater than or equal to “2”, invalidate a number of cells equal to that increment and invalidate them. In addition to generating dummy data in place of the cell, the user data of the subsequent cell is stored in the storage area of the buffer memory 33B subsequent to the storage area in which the dummy data is stored.

Therefore, if the fluctuation of the received cell is such that the deterioration of the transmission quality is allowed, all the user data included in the received valid cell is delivered to the public telephone network 42 as a sequence of valid frames, and When cell loss in the ATM network or reversal of cell arrival order occurs, an invalid STM frame is temporarily transmitted, but subsequently recovered to a normal state.
JP-A-9-168277 (summary) Japanese Patent Laid-Open No. 10-200549 (summary) JP 2000-183914 A (summary) JP 2001-16261 A (summary)

By the way, in the above-described conventional example, the cell sequence given by the gateway exchange 32 is used for a voice call signal or data call transmission information in a system such as a third generation mobile communication system. The present invention is not limited, and may correspond to the following various signals that are appropriately transmitted based on the call processing procedure.
A DTMF (Dual Tone Multi Frequency) signal (register signal) that indicates the dial number specified by the terminal 20-c and conforms to the signal system of the public telephone network 42
-Announcements and ringback tones sent to the public telephone network 42. Further, any of the signals given as a row of such cells is provided in the mobile switching device 31 and is operated by individual hardware (asynchronously operated). (Hereinafter referred to as “sound source”) and appropriately switched based on the above-described call processing procedure.

That is, the cell interval given from these sound sources to the cell receiving unit 33R via the mobile switch 31 and the gateway switch 32 changes only immediately after the sound source is switched, and is almost until the time when the sound source is switched again. In order to be constant, as shown in FIGS. 8 (a) and 8 (b), such cell row fluctuations are not single-shot.
Therefore, the deterioration of the transmission quality due to the fluctuation continues to exceed the allowable limit, and is likely to cause an underrun or an overrun in the addressing of the buffer memory 33B along with the steady increase of the transmission delay. It was.

  In addition, as a prior art relevant to this invention, there exists a technique disclosed by patent document 1 thru | or patent document 4 as stated above. However, although these prior arts can absorb a single fluctuation through the buffer memory, or can mitigate the deterioration of transmission quality due to the fluctuation, the above-mentioned non-single fluctuations are avoided. The resulting deterioration in transmission quality could not be alleviated.

  It is an object of the present invention to provide a buffer control device and a control device in which steady deterioration of transmission quality due to non-single fluctuations is avoided without greatly changing the configuration.

  In the first invention, the writing means cyclically writes the contents of the cells in the storage areas individually corresponding to the destination information of the cells sequentially given via the ATM network, among the storage areas of the buffer memory. The reading means reads the contents of the storage area of the buffer memory and delivers it as an STM signal to the STM network. Here, for each destination information, the writing means provides a predetermined range (for example, via an ATM network) between the storage area where writing is performed in the storage area corresponding to the destination information and the storage area read by the reading means. If the result of the determination is false, this gap is the range of the fluctuation that is the target of subsequent writing. To the storage area.

  That is, in the storage area of the buffer memory, a storage area in which cells including common destination information are sequentially written has a phase of the cell described above due to switching of hardware that outputs such cells. Even in the case where the shift is significantly larger than the range, the distance from the storage area read by the reading means is set to the storage area within the above-described fluctuation range.

Therefore, the deterioration of the transmission quality due to the hardware switching described above is reduced, and it is avoided that the transmission quality is constantly deteriorated.
In the second invention, the writing means cyclically writes the contents of the cell in the storage area of the buffer memory individually corresponding to the destination information of the cells sequentially given via the ATM network. The reading means reads the contents of the storage area of the buffer memory and delivers it as an STM signal to the STM network. Here, for each destination information, the writing means integrates the distance between the storage area where writing is performed in the storage area corresponding to the destination information and the storage area read by the reading means, and the cell is given via the ATM network. When the absolute value of the result of the integration exceeds the threshold value that is suitable for the fluctuation distribution allowed to accompany, the storage area that is the target of subsequent writing is set as the storage area that is the range of the fluctuation. To do.

That is, in the storage area of the buffer memory, the storage area in which cells including common destination information are sequentially written has its phase shifted due to switching of hardware that outputs such cells, and is restored. Even if it is not, the distance from the storage area read by the reading means is set to the storage area within the above-described fluctuation range.
Therefore, the deterioration of the transmission quality due to the hardware switching described above is reduced, and it is avoided that the transmission quality is constantly deteriorated.

  In the third invention, the storage means is provided with different storage areas corresponding to a plurality of destinations. The writing means cyclically writes each data included in the receiving cell in the storage area corresponding to the destination of the cell in the order of a predetermined address. The reading means is means for reading data written in the storage means, and sequentially reads out data corresponding to a plurality of destinations as a unit. The changing means includes a write address for data corresponding to each destination when writing by the writing means is included in a standard address range for each of a plurality of destinations defined with reference to the read address by the reading means. When the state not included is continued, the write address for the data corresponding to each destination of the writing means is individually changed to an address within the standard address range.

That is, in the storage area of the storage means, the storage area in which cells including common destination information are sequentially written has fluctuations exceeding a predetermined range due to switching of hardware that outputs these cells. Is continuously set, the distance from the storage area read by the reading means is set to the storage area that is within the above-described fluctuation range.
Therefore, the deterioration of the transmission quality is reduced, and it is avoided that the transmission quality is constantly deteriorated.

  In another invention, the contents of the cell are cyclically written in a column of the storage area individually corresponding to the destination information of the cells sequentially given via the ATM network in the storage area of the buffer memory. Of the storage areas of the buffer memory, the contents of the storage areas individually corresponding to all of the destination information that can be included in the cell are read out and transferred to the line of the STM network corresponding to these destination information. Further, for each destination information, a distance between a storage area where writing is performed on a column of storage areas corresponding to the destination information and a storage area which is subsequently read out is accompanied by a cell given via the ATM network. When it is determined whether or not the fluctuation range is acceptable, and the result of the determination is false, the storage area that is the target of subsequent writing is initially set in the storage area in which the gap is the fluctuation range. It becomes.

  That is, in the storage area of the buffer memory, a storage area in which cells including common destination information are sequentially written has a phase of the cell described above due to switching of hardware that outputs such cells. Even in the case where the shift is significantly larger than the range, the distance from the storage area read by the reading means is set to the storage area within the above-described fluctuation range.

Therefore, the deterioration of the transmission quality due to the hardware switching described above is reduced, and it is avoided that the transmission quality is constantly deteriorated.
Further, in another invention, the contents of the cell are cyclically written in a column of the storage area corresponding individually to the destination information of the cells sequentially given via the ATM network among the storage areas of the buffer memory. Of the storage areas of the buffer memory, the contents of the storage areas individually corresponding to all of the destination information that can be included in the cell are read out and transferred to the line of the STM network corresponding to these destination information. Further, for each destination information, the distance between the storage area in which writing is performed on the storage area column corresponding to the destination information and the storage area to be subsequently read out is integrated, and the cell is given via the ATM network. When the absolute value of the result of the integration exceeds the threshold value adapted to the fluctuation distribution allowed to accompany, the storage area in which the distance is the fluctuation range is referred to as “the storage area to be written subsequently”. Is initialized.

That is, in the storage area of the buffer memory, the storage area in which cells including common destination information are sequentially written has its phase shifted due to switching of hardware that outputs such cells, and is restored. Even if it is not, the distance from the storage area to be read out later is set to the storage area within the above-described fluctuation range.
Therefore, the deterioration of the transmission quality due to the hardware switching described above is reduced, and it is avoided that the transmission quality is constantly deteriorated.

As described above, according to the present invention, even when the phase of an arriving cell is significantly shifted beyond the range of fluctuation allowed to accompany the cell, the degradation of transmission quality is reduced, and the transmission is performed. It is avoided that the quality is constantly degraded.
Further, even when the phase of the arriving cell is shifted and is not restored, the degradation of the transmission quality is reduced, and the steady degradation of the transmission quality is avoided.

  Therefore, in the communication system to which these inventions are applied, the interface between the ATM network and the STM network is realized in a form adapted to the hardware configuration that is the source of the above-described fluctuation, and the transmission quality is good. Secured.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing an embodiment of the present invention.
In this embodiment, a CLAD 11 is provided in place of the CLAD 33 shown in FIG.
In addition, such a CLAD 11 is provided with a cell phase monitoring unit 11M in addition to the cell receiving unit 11R instead of the cell receiving unit 33R shown in FIG. 5, and the first and second inputs of the cell phase monitoring unit 11M. Are connected to the monitoring outputs of the cell receiver 11R and the frame transmitter 33T, respectively, and the output of the cell phase monitor 11M is connected to the control input of the cell receiver 11R.

FIG. 2 is an operation flowchart of this embodiment.
FIG. 3 is a diagram (1) for explaining the operation of the present embodiment.
FIG. 4 is a diagram (2) for explaining the operation of the present embodiment.
The operation of this embodiment will be described below with reference to FIGS.
The cell phase monitoring city 11M has a write address (hereinafter, the value is assumed to be “Pw”) and a read address (hereinafter, the value is “Pw”) held by the cell reception city 11R and the frame transmission unit 33T. Is assumed to be “Pr”), and at the time of start-up, the following processing is performed.
The initial value of the write address Pw for each time slot is equal to the sum of the read address Pr common to each time slot given to the buffer memory 33B by the frame transmission unit 33T and the average value T proportional to the above-described fluctuation guarantee time τ. Set the value. Thereafter, the write address for the received cell is sequentially updated to the subsequent address.
-The value of “phase change detection parameter” described later is initialized to “0”.

Furthermore, each time the read address Pr described above is set or updated, the cell phase monitoring unit 11M updates the latest read address Pr, the aforementioned product (= τ · f), and the storage area of the buffer memory 33B. Buffer memory 33B as the following three areas (standard area A, late arrival warning area B, and early arrival warning area C) determined on the basis of the number S and the predetermined value δ (τ · f>δ> 0) Know the storage area. Note that these areas shift as the read address changes.
- Of the storage area of the "standard area A" buffer memory 33B, the lower limit address Pw represented by the following formula (1) ^- a first storage area indicated by the upper limit address Pw ⁺ in represented by the following formula (2) It is sandwiched between the second storage areas shown and includes these first and second storage areas (FIG. 3 (1)).
Pw ⁻ = MOD (Pr + τ · f−δ, S) (1)
Pw ⁺ = MOD (Pr + τ · f + δ, S) (2)
Although Pw ⁺ and Pw ⁻ are defined as ± δ centered on (Pr + τ · f), they can be + δ, −δ ′, etc. in a laterally asymmetric manner.
“Late arrival warning area B” The direction adjacent to this “standard area A” in the storage area of the buffer memory 33B and the address decreases from the lower limit address Pw ⁻ described above (underflow corresponding to the decrease in address is (Fig. 3 (2)).
"Early arrival warning area C" The direction adjacent to this "standard area A" in the storage area of the buffer memory 33B and the address increases from the above-mentioned upper limit address Pw ⁺ (overflow according to the increase in the address is allowed) (Fig. 3 (3)).

In addition, the cell phase monitoring unit 11M performs the following process each time a cell for each slot is written in the buffer memory 33B by the cell receiving city 11R (see FIG. 2).
First, of the “standard area A”, “late arrival warning area B”, and “early arrival warning area C” described above, the storage area (hereinafter referred to as “current write area”) indicated by the write address Pw for the slot. ) Identifies the area to which it belongs.

If the “current write area” belongs to the “late arrival warning area B” (FIG. 3 (a)), the “phase change detection parameter” is decremented (FIG. 2 (1)), and continuous generation described later is performed. The number of times is set to “0” (FIG. 2 (2)).
If the “current write area” belongs to the “early arrival warning area C” (FIG. 3B), the “phase change detection parameter” is incremented (FIG. 2C), and a continuous operation described later is performed. The number of occurrences is set to “0” (FIG. 2 (4)).

If the “current writing area” belongs to “standard area A” (FIG. 3 (c)), the number of consecutive occurrences, which is the number of times such a state has occurred continuously, is counted (FIG. 2 ( 5)), it is determined whether or not the result of the count is “2”, and if the result of this determination is true, the absolute value of the “phase change detection parameter” is decremented (FIG. 2 (6)). )).
Through the above processing, it is determined whether or not the absolute value of the “phase change detection parameter” exceeds the predetermined threshold th. If the determination result is true, the modulo S expressed by the following equation (3) is used. The write address for the slot is initialized to Pw which is the result of the above operation (FIG. 2 (7)), and the value of the write address is given to the cell receiving unit 11R.
Pw = Pr + τ · f = Pr + T (3)
That is, among the storage areas of the buffer memory 33B, the value of the write address of the storage area in which cells including a common destination are sequentially written has non-single fluctuations in the cell due to the switching of the sound source described above. Even if it occurs, it is quickly initialized to a value indicating “standard area A” that is determined relative to the storage area indicated by the write address Pw described above.

Therefore, according to the present embodiment, steady deterioration in transmission quality due to such non-single fluctuations can be avoided with high accuracy.
Hereinafter, a process for avoiding the steady deterioration of transmission quality due to the non-single fluctuation described above will be specifically described.
Here, the size of “standard area A” is set to a value corresponding to ± 4 milliseconds with respect to the current value of the write address, and the above-described threshold th is set to “3”. To do.

The phase change detection parameter does not change even if a single fluctuation of about 3 milliseconds occurs, but if a single fluctuation exceeding 4 milliseconds occurs, it is incremented or decremented once, and then Promptly recovers to “0” (FIG. 4A).
However, due to the sound source switching (ATM path switching) described above, subsequent cells arrive 8 ms later (early), and all subsequent cells similarly arrive 8 ms later (early). In this case, the “late arrival warning area B (early arrival warning area C)” is written three times in succession. Accordingly, the cell write address is initialized as described above, and buffer underrun (buffer overrun) occurs three times prior to the initialization (FIGS. 4B to 4D).

For example, when the fluctuation guarantee time τ is 5 milliseconds, a cell with a single fluctuation of about 8 milliseconds is read out after being written to the buffer memory 33B and converted into a frame. (FIG. 4 (e)), it is handed over to the public telephone network 42 which is an STM network.
Furthermore, since the cell that arrived with a delay of 8 milliseconds is overwritten in the storage area to be read out of the storage area of the buffer memory 33B, the top 3 (= 8-5) milliseconds Minutes are not transmitted, but, for example, 2.75 milliseconds written in the storage area subsequent to the storage area indicated by the read address is delivered to the public telephone network 42 which is an STM network. Therefore, the deterioration of transmission quality is suppressed to the extent that data of 3 milliseconds is lost in rare cases.

In the above-described embodiment, the present invention relates to a public telephone network, which is an STM network, in a cell network provided from a gateway switch 32 to which an ATM switching method is applied in a core network constituting a third generation mobile communication system. This is applied to CLAD 11 which is handed over to 42 as a sequence of frames.
However, when such a CLAD 11 is provided with a circuit-switched mobile switch in the above-described core network, for example, a cell column provided by the base station controller 24 is used as a frame column for the mobile switch. May be applied to deliver.

Further, the present invention is not limited to the above-described third generation mobile communication system, but can be applied to various inter-network interfaces between the ATM network and the STM network.
Furthermore, in the above-described embodiment, the above-described sound source is provided as dedicated hardware that asynchronously generates a sequence of cells corresponding to a DTMF signal or a ringback tone.
However, the signal generated by such a sound source is handed over to the public telephone network 42 as a sequence of frames, and as long as it conforms to the signal system applied to the public telephone network 42, not only the call signal but any register signal. Or a line signal (signaling signal).

In the above-described embodiment, the specific configuration of the buffer memory 33B is not shown.
However, such a buffer memory 33B has the cell speed inputted to the cell receiving unit 11R and the multiplicity of user data read by the frame transmitting unit 33T and delivered to the public telephone network 42 as a sequence of frames. Can be configured as a combination of various memories as long as the cycle time and the storage capacity conforming to the above are satisfied and the requirements related to cost, mounting, maintenance and operation are satisfied.

  Further, in the above-described embodiment, the storage area of the buffer memory 33B is divided into a set of storage areas individually corresponding to destination information that can be included in the cell to be written, and the storage area included in each set Thus, writing is performed cyclically, and reading is included in each of these sets, and is performed in parallel on a plurality of storage areas (equal to the multiplicity of the STM network) indicated by a common read address. It has been broken.

However, the addressing and configuration of the buffer memory 33B may be any as long as writing and reading necessary for realizing processing equivalent to the processing described above are possible.
In the above-described embodiment, the “phase change detection parameter” is obtained as an integral value of the distance of the “current writing area” with respect to the “standard area A”, and the absolute value of the “phase change detection parameter” exceeds the threshold th. If the write address has been initialized.

However, the present invention is not limited to such a configuration. For example, when there is a possibility that the phase of a cell that arrives in response to the sound source switching described above exceeds the limit of “normally occurring fluctuations”, “ The write address may be quickly initialized when it is identified that the “current write area” does not belong to the “standard area A”.
Further, the lower limit address Pw ⁻ and the upper limit address Pw ⁺ indicating both ends of “standard area A” in the storage area of the buffer memory 33B are known values S, δ suitable for the configuration of the mobile switch 31 and the gateway switch 32. , Ε, and write address Pw are obtained as a result of the arithmetic operation of modulo S defined as equations (1) and (2).

However, in these lower limit address Pw ⁻ and upper limit address Pw ⁺ , changes in the distribution of fluctuations that are allowed to accompany the cell are ignored depending on the characteristics of the mobile switch 31 and the gateway switch 32 or other environmental changes. If it is too large to be possible, it may be updated as appropriate to a value suitable for the fluctuation distribution.
Further, the present invention is not limited to the above-described embodiment, and various embodiments can be made within the scope of the present invention, and any improvement may be applied to all or part of the constituent devices. .

Hereinafter, the techniques disclosed as the above-described embodiments are arranged hierarchically and multifacetedly and listed as additional notes.
(Additional remark 1) The writing means which writes the contents of the cell cyclically in the storage area individually corresponding to the destination information of the cell sequentially given through the ATM network among the storage areas of the buffer memory,
Read means for reading the contents of the storage area of the buffer memory and delivering it as an STM signal to the STM network,
The writing means includes
For each piece of the destination information, it is determined whether or not the distance between the storage area in the storage area corresponding to the destination information and the storage area read by the reading means is within a predetermined range, and the determination result is false. A buffer control device characterized in that, at a given time, a storage area that is a target of subsequent writing is set to a storage area in which this distance is the range.
(Additional remark 2) The writing means which writes the contents of the cell cyclically in the storage area corresponding individually to the destination information of the cell sequentially given through the ATM network among the storage areas of the buffer memory,
Read means for reading the contents of the storage area of the buffer memory and delivering it as an STM signal to the STM network,
The writing means includes
For each of the destination information, the distance between the storage area to be written in the storage area corresponding to the destination information and the storage area to be read by the reading means is integrated, and this accompanies the cell given through the ATM network. When the absolute value of the result of integration exceeds the threshold value that matches the allowable fluctuation distribution, the storage area that is the target of subsequent writing is set to the storage area that is the range of the fluctuation. A buffer controller.
(Supplementary Note 3) The contents of the cell are cyclically written in the storage area column individually corresponding to the destination information of the cells sequentially given via the ATM network among the storage areas of the buffer memory,
Of the storage area of the buffer memory, the contents of the storage area individually corresponding to all of the destination information that can be included in the cell are read, and delivered to the line of the STM network corresponding to these destination information,
For each destination information, a distance between a storage area where writing is performed on a column of storage areas corresponding to the destination information and a storage area which is subsequently read out is accompanied by a cell given via the ATM network. It is determined whether or not the fluctuation range is acceptable, and when the result of the determination is false, the storage area that is the target of subsequent writing is set to the storage area in which this gap is the fluctuation range. A characteristic buffer control method.
(Additional remark 4) In the storage area of the buffer memory, the contents of the cell are cyclically written in the storage area column individually corresponding to the destination information of the cells sequentially given through the ATM network,
Of the storage area of the buffer memory, the contents of the storage area individually corresponding to all of the destination information that can be included in the cell are read, and delivered to the line of the STM network corresponding to these destination information,
For each of the destination information, the difference between the storage area in which writing is performed on the storage area column corresponding to the destination information and the storage area to be read subsequently is integrated, and the cell is given via the ATM network. When the absolute value of the result of the integration exceeds the threshold value suitable for the fluctuation distribution allowed to accompany, the storage area that is the target of subsequent writing is set to the storage area in which the distance is the fluctuation range. And a buffer control method.
(Supplementary Note 5) Storage means including different storage areas corresponding to a plurality of destinations;
Writing means for cyclically writing each data included in the received cell to the storage area corresponding to the destination of the cell in order of a predetermined address;
Means for reading out data written in the storage means, and means for sequentially reading out data corresponding to a plurality of destinations as a unit;
Whether a write address for data corresponding to each destination when writing by the writing unit is included in a standard address range for each of the plurality of destinations defined on the basis of a read address by the reading unit And a changing means for individually changing a write address for data corresponding to each destination of the writing means to an address within a standard address range when a state not included is continued. Control device.

It is a figure which shows embodiment of this invention. It is an operation | movement flowchart of this embodiment. It is a figure (1) explaining operation | movement of this embodiment. It is FIG. (2) explaining operation | movement of this embodiment. It is a figure which shows the structural example of the 3rd generation mobile communication system. It is a figure which shows the detailed structure of a buffer memory. It is a figure explaining the writing and reading of the buffer memory in a prior art example. It is a figure explaining the subject of a prior art example.

Explanation of symbols

11, 33 CLAD
11R, 33R Cell receiving unit 11M Cell phase monitoring unit 20 Terminal 21 Wireless base station 22 Wireless zone 23 Communication link 24 Base station control station 30 Core network 31 Mobile switching unit 32 Gateway switching unit 33B Buffer memory 33T Frame transmission unit 41 Internet 42 Public telephone network

Claims (3)

A writing means for cyclically writing the contents of the cell in a storage area individually corresponding to the destination information of the cells sequentially given via the ATM network in the storage area of the buffer memory;
Read means for reading the contents of the storage area of the buffer memory and delivering it as an STM signal to the STM network,
The writing means includes
For each piece of the destination information, it is determined whether or not the distance between the storage area in the storage area corresponding to the destination information and the storage area read by the reading means is within a predetermined range, and the determination result is false. A buffer control device characterized in that, at a given time, a storage area that is a target of subsequent writing is set to a storage area in which this distance is the range. A writing means for cyclically writing the contents of the cell in a storage area individually corresponding to the destination information of the cells sequentially given via the ATM network in the storage area of the buffer memory;
Read means for reading the contents of the storage area of the buffer memory and delivering it as an STM signal to the STM network,
The writing means includes
For each of the destination information, the distance between the storage area to be written in the storage area corresponding to the destination information and the storage area to be read by the reading means is integrated, and this accompanies the cell given through the ATM network. When the absolute value of the result of integration exceeds the threshold value that matches the allowable fluctuation distribution, the storage area that is the target of subsequent writing is set to the storage area that is the range of the fluctuation. A buffer controller. Storage means having different storage areas corresponding to a plurality of destinations;
Writing means for cyclically writing each data included in the received cell to the storage area corresponding to the destination of the cell in order of a predetermined address;
Means for reading out data written in the storage means, and means for sequentially reading out data corresponding to a plurality of destinations as a unit;
Whether a write address for data corresponding to each destination when writing by the writing unit is included in a standard address range for each of the plurality of destinations defined on the basis of a read address by the reading unit And a changing means for individually changing a write address for data corresponding to each destination of the writing means to an address within a standard address range when a state not included is continued. Control device.

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