JP2005166730A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress plane channeling at the time of ion implantation without changing a crystal plane direction of a wafer itself. <P>SOLUTION: At the time of ion implantation into the semiconductor wafer W1, a tilting angle θ with respect to a (100)-plane is set to 0° or above and a twisting angle δ with respect to the <011>-direction is set within a range of 45°±5°. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly suitable for application to a tilt angle and twist angle setting method during ion implantation.

In a conventional semiconductor device, a silicon wafer having a crystal plane orientation (100) plane as a main surface is used. When ion implantation is performed on such a silicon wafer, the ion implantation direction is changed to prevent channeling. Inclining about 7 ° from the vertical direction of the wafer is performed.
In addition, for example, in Patent Document 1, in order to prevent surface channeling and to perform ion implantation perpendicular to the silicon wafer surface, each of two surfaces orthogonal to the (100) plane is 3.5 degrees or more. A method is disclosed in which a plane perpendicular to the crystal plane orientation forming an angle is used as one main surface of a silicon wafer.
JP 7-172990 A

However, in the method in which the ion implantation direction is tilted by about 7 ° from the vertical direction of the wafer, for example, when ions having a light mass such as B ⁺ are implanted, the impurity concentration at the peak position decreases in the depth direction of the silicon wafer. The impurity concentration in the deepest part increases in a trailing manner. For this reason, there has been a problem that the impurity concentration distribution in the depth direction of the silicon wafer becomes slow, and the variation in electrical characteristics of the semiconductor device becomes large. In addition, there is a problem that the variation in the in-plane distribution of the impurity concentration of the silicon wafer increases.

In addition, the method disclosed in Patent Document 1 has a problem that it is necessary to cut a silicon wafer obliquely from a silicon ingot, which makes it difficult to control the cutting angle and complicates the management of crystal plane orientation.
Accordingly, an object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device that can suppress surface channeling during ion implantation without changing the crystal plane orientation of the wafer itself.

In order to solve the above-described problem, according to the semiconductor device of one embodiment of the present invention, the tilt angle with respect to the (100) plane is 0 ° or more and the twist angle is 45 ° ± 5 ° with respect to the <011> direction. Impurities are ion-implanted within the range.
Thereby, even when ion implantation is performed on a semiconductor wafer having a crystal plane orientation (100) plane as a main surface, it is possible to suppress plane channeling. For this reason, it is possible to suppress a decrease in the impurity concentration at the peak position, and it is possible to prevent the impurity concentration in the deepest part from rising in a trailing manner, and to reduce the impurity concentration in the depth direction of the silicon wafer. The distribution can be sharpened, the variation in the in-plane distribution of the impurity concentration can be reduced, and the variation in the electrical characteristics of the semiconductor device can be reduced without using a special semiconductor wafer. .

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a step of forming a mask pattern on a wafer having a (100) plane as a main surface, and a tilt angle with respect to the wafer main surface of 0 ° or more, And a step of ion-implanting impurities into the wafer on which the mask pattern is formed under the condition that a twist angle with respect to the orientation flat is within a range of 45 ° ± 5 °.
As a result, the impurity concentration distribution in the depth direction of the silicon wafer can be sharpened, and variations in the in-plane distribution of the impurity concentration can be reduced. A semiconductor device can be used without using a special semiconductor wafer. The variation in electrical characteristics can be reduced.

Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view showing a method for setting a tilt angle and a twist angle during ion implantation according to the first embodiment of the present invention.
In FIG. 1, a semiconductor wafer W1 is configured to have a (100) plane as a main surface, and an orientation flat OR is formed along the <011> direction. As the semiconductor wafer W1, for example, a material having a crystal structure such as a diamond lattice or a zinc blende lattice can be used, and can be applied to Si, Ga, SiGa, GaAs, and the like. Further, a notch may be provided instead of the orientation flat OR.

When ion implantation of the semiconductor wafer W1 is performed, the tilt angle θ (incident angle from the vertical direction of the semiconductor wafer W1) with respect to the (100) plane is 0 ° or more, and the twist angle δ (incident angle) with respect to the <011> direction. Can be set within a range of 45 ° ± 5 °.
Thereby, even when ion implantation is performed on the semiconductor wafer W1 having the crystal plane orientation (100) plane as a main surface, it is possible to suppress the plane channeling. For this reason, it is possible to suppress a decrease in the impurity concentration at the peak position, and it is possible to prevent the impurity concentration in the deepest portion from rising in a trailing manner, and to reduce the impurity in the depth direction of the semiconductor wafer W1. Concentration distribution can be sharpened, variation in in-plane distribution of impurity concentration can be reduced, and variation in electrical characteristics of semiconductor devices can be reduced without using a special semiconductor wafer W1. Can do.

  FIG. 2 is a diagram showing the impurity concentration with respect to the implantation depth using the twist angle as a parameter according to the second embodiment of the present invention. In FIG. 2, boron B is implanted into a silicon wafer having a crystal plane orientation (100) under conditions of an implantation energy of 180 KeV and a dose of 1E14, and the impurity concentration in the depth direction is determined by SIMS (Secondary Ion Mass Spectrometry: secondary ions. (Mass spectrometry) shows the measurement results.

In FIG. 2, as shown in region A, the impurity concentration at the peak position is decreased under the conditions of tilt angle = 7 ° and twist angle = 0 °, whereas tilt angle = 7 ° and twist angle = It can be seen that the decrease in the impurity concentration at the peak position is suppressed under the condition of 45 °.
Further, as shown in the region B, when the tilt angle is 7 ° and the twist angle is 0 °, the impurity concentration in the deepest part is rising like a tail, whereas the tilt angle is 7 ° and the twist angle. It can be seen that under the condition of = 45 °, the impurity concentration in the deepest part is suppressed from rising in a trailing shape.

  FIG. 3 is a diagram showing an in-plane distribution of impurity concentration according to the third embodiment of the present invention. FIG. 3 shows a case where boron B is implanted into a silicon wafer having a plane orientation (100) under the conditions of implantation energy 180 KeV and dose 1E14. In FIG. 3A, tilt angle = 7 °, twist angle. In FIG. 3B, the tilt angle was set to 7 ° and the twist angle was set to 45 °.

  As a result, in the silicon wafer W3 in FIG. 3B, the in-plane distribution of the impurity concentration is uniform compared to the silicon wafer W2 in FIG. 3A, and the twist angle at the time of ion implantation is 45 °. By setting, the in-plane distribution of the impurity concentration can be improved.

The perspective view which shows the ion implantation method which concerns on 1st Embodiment of this invention. The figure which shows the impurity concentration with respect to the implantation depth which concerns on 2nd Embodiment of this invention. The figure which shows the in-plane distribution of the impurity concentration which concerns on 3rd Embodiment of this invention.

Explanation of symbols

  W1 semiconductor wafer, W2, W3 silicon wafer

Claims (2)

  A semiconductor device wherein impurities are ion-implanted within a tilt angle of 0 ° or more with respect to a (100) plane and a twist angle of 45 ° ± 5 ° with respect to the <011> direction. Forming a mask pattern on a wafer having a (100) plane as a main surface;
And a step of ion-implanting impurities into the wafer on which the mask pattern is formed under a condition in which a tilt angle with respect to the main surface of the wafer is 0 ° or more and a twist angle with respect to the orientation flat is within a range of 45 ° ± 5 °. A method for manufacturing a semiconductor device.

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