JP2005159383A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device having an interlayer insulating film made to assure large coupling capacitance between a controlling gate and a floating gate, while assuring electric field moderating effect and leak prevention function. <P>SOLUTION: In the nonvolatile semiconductor memory device using a memory cell having a silicon substrate 11, a floating gate 14 formed on the substrate 11 through a tunnel insulating film 13, and a control gate 16 formed on the floating gate 14 through an interlayer insulating film 15, the interlayer insulating film 15 is composed of a silicone oxide film 15a which makes contact with the floating gate 14, a first silicon nitride film 15b which is formed on the silicon oxide film 15a by the LPCVD method, and a second silicon nitride film 15c which is formed on the first silicon nitride film 15b by the JVD method and has a trap density lower than the first silicon nitride film 15b. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device having a memory cell having a stacked gate structure.

  Conventionally, a nonvolatile semiconductor memory device using a memory cell structure in which a floating gate is formed on a semiconductor substrate via a tunnel insulating film and a control gate is stacked thereon via an interlayer insulating film is known. ing. As the interlayer insulating film of this memory cell, a so-called ONO (Oxide-Nitride-Oxide) structure of silicon oxide film / silicon nitride film / silicon oxide film is usually used. 4A and 4B show cross sections in two orthogonal directions of such a memory cell structure. In a normal flash memory, control gates of a plurality of memory cells are continuously arranged to form a word line, and FIG. 4A is a cross section in a direction parallel to the word line direction.

  An element isolation insulating film 2 is formed on the p-type silicon substrate 1, and a floating gate 4 is formed in the element region surrounded by the element isolation insulating film 2 via the tunnel insulating film 3. An ONO film 5 in which a silicon oxide film 5a, a silicon nitride film 5b, and a silicon oxide film 5c are laminated is formed as an interlayer insulating film on the floating gate 4, and a control gate 6 is further formed thereon. Source and drain diffusion layers 7 and 8 are formed on the control gate 6 in a self-aligning manner.

  The ONO film 5 functions to prevent the accumulated charge of the floating gate 4 from being released due to leakage during the write operation of the memory cell, and it is necessary to confine the charge in the floating gate 4 for a long period of time. Sex is required. In a normal flash memory, electrons are held in the floating gate. In the electron holding state, a relatively weak electric field (self-electric field) generated by the electrons is applied to the ONO film 5.

  If the silicon oxide film 5a on the floating gate 4 side of the ONO film 5 has a thickness of 5 to 6 nm, it exhibits a Fowler-Nordheim type tunnel current conduction mechanism, and the current flowing in a low electric field is extremely small. Further, the barrier height of the silicon oxide film 5a with respect to silicon is as high as 3.2 eV. Therefore, if there is no defect in the silicon oxide film 5a and there is no electric field concentration effect due to the two-dimensional shape of the floating gate 4, the silicon oxide film 5a alone should be able to hold the electrons of the floating gate 4 for a sufficiently long time. is there. However, in reality, an ONO film is used because of defects and a two-dimensional electric field concentration effect.

  The two-dimensional electric field concentration effect is representative of the electric field concentration at the edge portion obtained by patterning the floating gate 4 as indicated by a broken line A in FIG. There is also electric field concentration due to unevenness formed on the surface of the floating gate 4 when the silicon oxide film 5a is formed by thermal oxidation. The silicon nitride film 5b of the ONO film 5 includes many trap levels, and acts to relax the electric field by trapping even when current flows due to electric field concentration, so that the charge from the oxide film 5a surrounding the floating gate is reduced. Suppress leaks. A similar mechanism works when there is a defect in the oxide film 5a. This is the reason why the silicon nitride film 5b is used.

  By the way, when the memory cell is operating or when the floating gate holds electrons, the control gate 6 is positively biased. It is known that a large leakage current flows in the silicon nitride film due to hole conduction through the trap level. Therefore, if the control gate 6 is formed directly on the silicon nitride film 5b, holes are injected from the control gate 6 and insulation resistance cannot be sufficiently maintained. In order to suppress the hole injection from the control gate 6, the upper silicon oxide film 5c is provided.

  In order to exert the above-described functions of electric field relaxation and leakage prevention, the ONO film 5 requires a thickness of 5 to 6 nm for the upper and lower silicon oxide films 5a and 5c. The silicon nitride film 5b is about 10 nm (5 nm in terms of oxide film). Therefore, the ONO film 5 has an effective oxide film thickness of 15 to 16 nm.

  The above-described interlayer insulating film having the ONO structure has the following problems. First, in order to enable operation of the memory cell at a low voltage, it is desirable that the coupling capacitance between the control gate and the floating gate is large, and for that purpose, the ONO film is desirably as thin as possible. If each film thickness is reduced to the limit, the total thickness can be reduced to about 14 nm in terms of oxide film, but it is difficult to reduce the thickness further. Second, in the ONO film, the bird's beak B enters between the floating gate 4 and the control gate 6 from the side as shown in FIG. This bird's beak reduces the coupling capacitance between the control gate 6 and the floating gate 4. In particular, when the silicon oxide film 5a immediately above the floating gate is formed by CVD, the denseness is inferior to that of the thermal oxide film, so that the oxygen in the film diffuses quickly and a large bird's beak enters. When trying to obtain a good quality silicon oxide film at a low process temperature, a silicon oxide film formed by CVD may be used rather than thermal oxidation. In such a case, the entry of bird's beaks becomes a problem.

  The present invention has been made in view of the above circumstances, and has an interlayer insulating film capable of securing a large coupling capacitance between the control gate and the floating gate while ensuring an electric field relaxation effect and a leakage prevention function. An object of the present invention is to provide a nonvolatile semiconductor memory device.

  A first nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate, a floating gate formed on the semiconductor substrate via a tunnel insulating film, and an interlayer insulating film formed on the floating gate. In a nonvolatile semiconductor memory device using a memory cell having a control gate, the interlayer insulating film includes a silicon oxide film in contact with the floating gate and a first silicon formed on the silicon oxide film by a low pressure CVD method. The semiconductor device includes a nitride film and a second silicon nitride film having a trap density lower than that of the first silicon nitride film formed on the first silicon nitride film.

In the first nonvolatile semiconductor memory device, preferably, the second silicon nitride film conveys active Si and N obtained by plasma decomposition of a gas containing at least a silane-based gas and nitrogen to the substrate surface. It is assumed that it was deposited by this. In the first nonvolatile semiconductor memory device, preferably, the first silicon nitride film has a hydrogen content of 10 ²¹ / cm ³ or more, and the second silicon nitride film has a hydrogen content of 10 ^19. / Cm ³ or less.

  A second nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate, a floating gate formed on the semiconductor substrate via a tunnel insulating film, and an interlayer insulating film formed on the floating gate. In a nonvolatile semiconductor memory device using a memory cell having a control gate, the interlayer insulating film includes a silicon oxide film in contact with the floating gate and a silicon nitride film deposited on the silicon oxide film by a low pressure CVD method. And a silicon nitride film having a lower trap density.

A third nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate, a floating gate formed on the semiconductor substrate via a tunnel insulating film, and an interlayer insulating film formed on the floating gate. In a nonvolatile semiconductor memory device using a memory cell having a control gate, the interlayer insulating film has a silicon oxide film in contact with the floating gate, and a hydrogen content of 10 ¹⁹ / deposited on the silicon oxide film. and a silicon nitride film having a size of cm ³ or less.

  In the second or third nonvolatile semiconductor memory device, preferably, the silicon nitride film transports active Si and N obtained by plasma decomposition of a gas containing at least a silane-based gas and nitrogen to the substrate surface. It is assumed that it was deposited by this.

  A fourth nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate, a floating gate formed on the semiconductor substrate via a tunnel insulating film, and an interlayer insulating film formed on the floating gate. In a nonvolatile semiconductor memory device using a memory cell having a control gate, the interlayer insulating film is a silicon having a lower trap density than a silicon nitride film formed by a low pressure CVD method as a layer in contact with at least one of the floating gate and the control gate It has a nitride film.

A fifth nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate, a floating gate formed on the semiconductor substrate via a tunnel insulating film, and an interlayer insulating film formed on the floating gate. In a nonvolatile semiconductor memory device using a memory cell having a control gate, the interlayer insulating film is a silicon having a hydrogen content of 10 ¹⁹ / cm ³ or less as a layer in contact with at least one of the floating gate and the control gate It has a nitride film.

  In the fourth or fifth nonvolatile semiconductor memory device, preferably, the silicon nitride film transports at least active Si and N obtained by plasma decomposition of a gas containing silane-based gas and nitrogen to the substrate surface. It is assumed that it was deposited by this. In the fourth or fifth nonvolatile semiconductor memory device, specifically, (1) the silicon nitride film is provided in two layers in contact with both the floating gate and the control gate, and between these two layers. (2) The silicon nitride film is provided in two layers in contact with both the floating gate and the control gate, and the silicon oxide film and the low pressure CVD method are provided between the two layers. (3) The silicon nitride film is provided only on the side in contact with the floating gate, on which a silicon oxide film, a silicon nitride film by a low pressure CVD method, and a silicon oxide film are provided. It is assumed that a laminated film of films is formed.

  According to the present invention, by using a silicon nitride film whose trap state density is sufficiently lower than that of a normal LPCVD silicon nitride film in the interlayer insulating film, the electric field relaxation effect and the leakage reduction effect are exhibited while being effective. It becomes possible to secure a large coupling capacitance between the control gate and the floating gate by making the oxide film thickness smaller than before. In addition, when such a silicon nitride film is used as the layer in contact with the control gate or the floating gate, bird's beak intrusion in the post-oxidation process is suppressed, so that a large coupling capacitance between the control gate and the floating gate can be secured. Become.

  According to the present invention, by using a silicon nitride film having a trap state density sufficiently lower than that of a silicon nitride film formed by a normal LPCVD method in an interlayer insulating film of a nonvolatile memory cell having a stacked gate structure, electric field relaxation is achieved. It is possible to secure a large coupling capacitance between the control gate and the floating gate by making the effective oxide film thickness smaller than before while exhibiting the effect and the effect of reducing the leakage.

Embodiments of the present invention will be described below with reference to the drawings.

  Embodiment 1 FIGS. 1A and 1B are cross-sectional views in two orthogonal directions showing a memory cell structure of a nonvolatile semiconductor memory device according to Embodiment 1 of the present invention. An element isolation insulating film 12 is formed on a p-type silicon substrate 11, and a floating gate 14 made of a polycrystalline silicon film is formed in an element region surrounded by the element isolation insulating film 12 via a tunnel insulating film 13. The tunnel insulating film 13 is a silicon oxide film. A control gate 16 made of a polycrystalline silicon film is laminated on the floating gate 14 via an interlayer insulating film 15. Source and drain diffusion layers 17 and 18 are formed on the substrate in self-alignment with the control gate 16.

  The interlayer insulating film 15 includes a silicon oxide film 15a in contact with the floating gate 14 and two layers of silicon nitride films 15b and 15c formed thereon. The first silicon nitride film 15b is a film formed by a normal low pressure (LP) CVD method, and the second silicon nitride film 15c is a first silicon film formed by a JVD (Jet Vapor Deposition) method. Compared with the nitride film 15b, the trap state density is sufficiently low, and the leakage current in the low electric field region is small.

Specifically, the silicon oxide film 15a is a thermal oxide film obtained by thermally oxidizing the floating gate 14, or a silicon oxide film formed by LPCVD. The first silicon nitride film 15b is formed by LPCVD using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₄ ) as source gases. The second silicon nitride film 15c is activated by plasma decomposition of a silane-based gas (for example, SiH ₄ ) supplied with a carrier gas such as He and a nitrogen-containing gas (for example, N ₂ ) with microwave power. Si and N are produced and deposited by JVD which feeds the substrate surface located in the chamber. It has already been reported that a silicon nitride film having a low trap level density can be obtained by this JVD method (see, for example, Applied Surfaces Science 117/118 (1997) 259-267).

Here, the hydrogen content of the first silicon nitride film 15b deposited by the LPCVD method is 10 ²¹ / cm ³ or more, whereas the hydrogen content of the second silicon nitride film 15c deposited by the JVD method. Is 10 ¹⁹ / cm ³ or less. This difference in hydrogen content correlates with the magnitude of the trap level density of both, and if reduced, the silicon nitride film deposited by the JVD method with a low hydrogen content has a low trap level density, Low leakage current in low electric field region. Note that a silicon nitride film formed by another deposition method may be used as long as a silicon nitride film deposited by the JVD method has a low hydrogen content and has a low trap level density.

  Next, the reason why such a structure of the interlayer insulating film 15 is used and the preferable film thickness of each part will be specifically described below. In the silicon nitride single layer film 15c deposited by the JVD method, although not as much as the silicon nitride film deposited by the LPCVD method, a Frenkel-Poole type current flows in a low electric field region. It is difficult to use as. Also, the silicon nitride film has a lower barrier height against silicon than the silicon oxide film, and is insufficient as a barrier against electron emission from the floating gate. Therefore, for example, a silicon oxide film 15a is required as an interlayer insulating film immediately above the floating gate. In order to maintain sufficient insulation resistance, the silicon oxide film 15a requires a film thickness of about 5 to 6 nm.

  The first silicon nitride film 15b by the LPCVD method is necessary for the electric field relaxation effect and leakage prevention. That is, the silicon nitride film 15b has a high trap density and Frenkel-Poole type electric conduction characteristics. The Frenkel-Poole type electric conduction has a small current in a high electric field region, and a film including a trap makes it difficult for a current to flow because a carrier is trapped even if an initial current flows. For this reason, the silicon nitride film 15b suppresses an increase in leakage current due to electric field concentration at the two-dimensional edge portion of the floating gate 14. In order to exhibit a sufficient electric field relaxation effect, the thickness of the silicon nitride film 15b is preferably 6 nm or more, and in order to ensure a large coupling capacity, it is preferably 10 nm or less. Specifically, it is about 8 nm.

  The second silicon nitride film 15c by the JVD method functions to suppress hole injection from the control gate 16. In other words, the LPCVD silicon nitride film 15b easily allows a Frenkel-Poole type hole current to flow, and when this is in direct contact with the control gate 6, the control gate 16 is operated in a positive bias mode as described above. A large leak current flows due to hole injection from 16. The second silicon nitride film 15c formed by the JVD method has a very low trap density, and hole injection from the control gate 16 is effectively suppressed. In order to exert this function, the second silicon nitride film 15c preferably has a thickness of 6 nm or more, and preferably 10 nm or less in order to ensure a large coupling capacity.

  Specifically, for example, the silicon oxide film 15a is 6 nm, the silicon nitride films 15a and 15b are each 6 nm (3 nm in terms of oxide film), and the effective oxide film thickness of the interlayer insulating film 15 is 12 nm. Therefore, the thickness can be reduced as compared with the conventional ONO structure, and a sufficient electric field relaxation effect can be obtained. Further, since the uppermost layer of the interlayer insulating film 15 is the silicon nitride film 15c, it is possible to suppress the entry of bird's beaks when post-oxidation is performed.

[Second Embodiment] FIG. 2 shows a memory cell structure according to a second embodiment of the present invention, corresponding to FIG. In this embodiment, the interlayer insulating film 15 includes a silicon oxide film 15a and a silicon nitride film 15c having a low trap density and a hydrogen content of 10 ¹⁹ / cm ³ or less by the JVD method from the floating gate 14 side. Formed by layers.

  In the first embodiment, in order to be able to withstand use in a high electric field, a silicon nitride film 15b by LPCVD showing Frenkel-Poole type conduction is interposed in the center of the interlayer insulating film 15. However, this silicon nitride film 15b is not necessarily required when not operating in a high electric field. That is, as shown in FIG. 2, in order to block defects in the lowermost silicon oxide film 15a, a two-layer structure of a silicon oxide film 15a and a silicon nitride film 15c having a low trap density by the JVD method is used. it can.

  In the case of a silicon nitride film having many traps by normal LPCVD, the effect of using a silicon nitride film due to a large amount of holes injected from the control gate cannot be expected with only the two-layer structure of silicon oxide film / silicon nitride film. If a silicon nitride film formed by the JVD method is used, there is almost no hole conduction, so that a sufficient effect can be obtained even with a two-layer structure.

[Embodiment 3] In order to prevent bird's beak intrusion into the interlayer insulating film due to post-oxidation, directly above the floating gate (that is, the lowermost layer of the interlayer insulating film) or directly below the control gate (that is, the uppermost layer of the interlayer insulating film). In addition, a silicon nitride film having a hydrogen content of 10 ¹⁹ / cm ³ or less by a JVD method is interposed with a very thin film thickness of about 3 nm. If a film having a high trap density by the ordinary LPCVD method is used as this silicon nitride film, the threshold value of the memory cell becomes unstable due to trapping and discharging of charges in the film, but the trap density deposited by the JVD method is If a low silicon nitride film is used, instability will not occur.

  FIGS. 3A to 3D show only the interlayer insulating film structure according to the third embodiment. FIG. 3A shows an example in which a silicon nitride film 15d by the JVD method is interposed as a layer in contact with the floating gate 14 in the structure of the interlayer insulating film 15 in FIG. A similar silicon nitride film 15c is provided as a layer in contact with the control gate 16, and an interlayer insulating film 15 is formed with the silicon oxide film 15a interposed between the nitride films 15c and 15d.

  FIG. 3B shows an example in which a silicon nitride film 15d by the JVD method is interposed as a layer in contact with the floating gate 14 similarly to the structure of the interlayer insulating film 15 in FIG. Also in this case, a similar silicon nitride film 15c is provided as a layer in contact with the control gate 16, and a laminated film of a silicon oxide film 15a and a silicon nitride film 15b formed by LPCVD is interposed between the nitride films 15c and 15d. I am letting.

  FIG. 3C shows an example in which a silicon nitride film 15d by the JVD method is interposed as a layer in contact with the floating gate 14 in the same manner as the interlayer insulating film 150 having a normal ONO structure. That is, a laminated film 150 of a silicon oxide film, a silicon nitride film formed by LPCVD, and a silicon oxide film is further stacked on the silicon nitride film 15d.

  FIG. 3D shows an example in which silicon nitride films 15d and 15e are formed by a JVD method as a layer in contact with the floating gate 14 and the control gate 16 in addition to the normal ONO structure interlayer insulating film 150. That is, the silicon nitride film 15e is further overlaid on the interlayer insulating film 150 having the ONO structure shown in FIG. The same effect can be obtained by this embodiment.

1 shows a memory cell structure according to a first embodiment of the present invention. 4 shows a memory cell structure according to a second embodiment of the present invention. 5 shows an interlayer insulating film structure of a memory cell according to Embodiment 3 of the present invention. 1 shows a memory cell structure of a conventional nonvolatile memory.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Silicon substrate, 12 ... Element isolation insulating film, 13 ... Tunnel insulating film, 14 ... Floating gate, 15 ... Interlayer insulating film, 15a ... Silicon oxide film, 15b ... First silicon nitride film, 15c ... second silicon nitride film, 16 ... control gate, 17, 18 ... source and drain diffusion layers.

Claims (6)

Nonvolatile semiconductor memory using a memory cell having a semiconductor substrate, a floating gate formed on the semiconductor substrate via a tunnel insulating film, and a control gate formed on the floating gate via an interlayer insulating film In the device
The interlayer insulating film is
A nonvolatile semiconductor memory device comprising a silicon nitride film having a trap density lower than that of a silicon nitride film formed by a low pressure CVD method as a layer in contact with at least one of the floating gate and the control gate. Nonvolatile semiconductor memory using a memory cell having a semiconductor substrate, a floating gate formed on the semiconductor substrate via a tunnel insulating film, and a control gate formed on the floating gate via an interlayer insulating film In the device
The interlayer insulating film is
A nonvolatile semiconductor memory device having a silicon nitride film having a hydrogen content of 10 ¹⁹ / cm ³ or less as a layer in contact with at least one of the floating gate and the control gate. 2. The silicon nitride film is deposited by transferring active Si and N obtained by plasma decomposition of a gas containing at least a silane-based gas and nitrogen to the substrate surface. Or the nonvolatile semiconductor memory device according to 2; 3. The non-volatile device according to claim 1, wherein the silicon nitride film is provided in two layers in contact with both the floating gate and the control gate, and a silicon oxide film is interposed between the two layers. Semiconductor memory device. The silicon nitride film is provided in two layers in contact with both the floating gate and the control gate, and a laminated film of a silicon oxide film and a silicon nitride film formed by a low pressure CVD method is interposed between the two layers. The nonvolatile semiconductor memory device according to claim 1. The silicon nitride film is provided only on a side in contact with the floating gate, and a silicon oxide film, a laminated film of a silicon nitride film and a silicon oxide film formed by a low pressure CVD method is formed thereon. 3. The nonvolatile semiconductor memory device according to 1 or 2.

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