JP2005159001A - Semiconductor element with schottky barrier - Google Patents
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本発明は、順方向電力損失が小さく且つショットキ障壁を有するフリップチップ構造の小型の半導体素子に属する。 The present invention belongs to a small-sized semiconductor device having a flip-chip structure having a small forward power loss and a Schottky barrier.
情報化社会の急速な進歩に伴い、小型化・軽量化が進む情報通信機器及び携帯機器には、更に高効率化及び低ノイズ化が要求されている。また、多種多様化の機能が要求される携帯端末機器では、基板への実装密度が年々高くなる状況から、小型で軽量化され放熱性能を向上した電子部品が求められている。このため、従来の樹脂モールド型よりも高密度実装が可能なフリップチップやチップサイズパッケージの開発が進んでいる。
アノード電極とカソード電極をチップの同一面に素子構造を形成するショットキバリアダイオードのフリップチップ化が図られている。また、カソード電極をアノード電極の片側に配置するサイドアノード構造（Side-Anode structure）と、カソード電極をアノード電極の両側に配置するセンターアノード構造（Center-Anode structure）のフリップチップ型ショットキバリアダイオードが提案されている。下記特許文献１は、半導体基板の中央側にアノード電極を配置したショットキバリアダイオード（センターアノード構造）を開示し、下記特許文献２は、半導体基板(5)の一方の側面側に変位してアノード電極を配置したショットキバリアダイオード（サイドアノード構造）を開示する。
With the rapid progress of the information society, information communication devices and portable devices that are becoming smaller and lighter are required to have higher efficiency and lower noise. Further, in portable terminal devices that require various functions, electronic components that are small in size and light in weight and improved in heat dissipation performance are required because the density of mounting on a substrate increases year by year. For this reason, development of flip chips and chip size packages capable of mounting at higher density than conventional resin molds is advancing.
A flip chip of Schottky barrier diode in which an anode electrode and a cathode electrode are formed on the same surface of a chip is used. In addition, a flip-chip Schottky barrier diode with a side-anode structure in which the cathode electrode is disposed on one side of the anode electrode and a center-anode structure in which the cathode electrode is disposed on both sides of the anode electrode is provided. Proposed.
図６に示すように、サイドアノード構造のショットキバリアダイオードは、特定の導電型である相対的に不純物濃度の高いＮ+型の第１の半導体領域(1)と、第１の半導体領域(1)の上面に形成され且つ第１の半導体領域(1)よりも相対的に不純物濃度の低い同一の導電型であるＮ-型の第２の半導体領域(2)と、第１の半導体領域(1)と第２の半導体領域(2)とに接触する第３の半導体領域(3)とを備えたシリコン(Si)、砒化ガリウム(GaAs)、窒化ガリウム(GaN)等の半導体基板(5)を有する。第２の半導体領域(2)との接触面にショットキ障壁を形成するタングステン(W)、アルミニウム(Al)、モリブデン(Mo)、ニッケルシリサイド(Ni2Si)等から成るアノード電極である第１の電極(6)が半導体基板(5)の一方の主面に形成される。また、第３の半導体領域(3)と低抵抗性接触するカソード電極である第２の電極(7)が半導体基板(5)の一方の主面に形成される。また、第１の電極(6)の外周縁に沿って第１の電極(6)を包囲するＰ型半導体領域からなる第４の半導体領域(4)が平面的に見て環状に形成される。第４の半導体領域(4)は、第１の電極(6)により形成されるショットキバリア電極の周辺耐圧を向上するガードリング領域として機能する。第１の半導体領域(1)よりも不純物濃度が低く設定される第２の半導体領域(2)と、第２の半導体領域(2)の上面に形成されたショットキバリア電極を構成する第１の電極(6)との界面にショットキ障壁が形成される。 As shown in FIG. 6, the Schottky barrier diode having a side anode structure includes an N + type first semiconductor region (1) having a specific conductivity type and a relatively high impurity concentration, and a first semiconductor region (1 ) And an N − -type second semiconductor region (2) of the same conductivity type having a lower impurity concentration than the first semiconductor region (1), and a first semiconductor region ( A semiconductor substrate (5) such as silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), etc., having a first semiconductor region (3) in contact with the first semiconductor region (2). Have A first anode electrode made of tungsten (W), aluminum (Al), molybdenum (Mo), nickel silicide (Ni 2 Si), etc. that forms a Schottky barrier on the contact surface with the second semiconductor region (2). An electrode (6) is formed on one main surface of the semiconductor substrate (5). A second electrode (7), which is a cathode electrode in low resistance contact with the third semiconductor region (3), is formed on one main surface of the semiconductor substrate (5). Further, a fourth semiconductor region (4) made of a P-type semiconductor region surrounding the first electrode (6) is formed in an annular shape when viewed in plan along the outer peripheral edge of the first electrode (6). . The fourth semiconductor region (4) functions as a guard ring region for improving the peripheral breakdown voltage of the Schottky barrier electrode formed by the first electrode (6). A second semiconductor region (2) whose impurity concentration is set lower than that of the first semiconductor region (1) and a first Schottky barrier electrode formed on the upper surface of the second semiconductor region (2) A Schottky barrier is formed at the interface with the electrode (6).
また、図７は、第１の電極(6)の周囲に複数の第２の電極(7)を形成したセンターアノード構造のフリップチップ型ショットキバリアダイオードを示す。図７では、相対的に不純物濃度の高いＮ+半導体領域から成る第３半導体領域(3)は、側面と底面がそれぞれ第２の半導体領域(2)と第１の半導体領域(1)に接する。アノード面とカソード面が近接し距離が短いほど基本的に順方向の損失は少ない。しかしながら、センターアノード構造に形成するとチップが細長くなり、機械的強度を考慮すると最適設計とは言えない。 FIG. 7 shows a flip-chip Schottky barrier diode having a center anode structure in which a plurality of second electrodes (7) are formed around the first electrode (6). In FIG. 7, the side surface and the bottom surface of the third semiconductor region (3) composed of the N + semiconductor region having a relatively high impurity concentration are in contact with the second semiconductor region (2) and the first semiconductor region (1), respectively. . The closer the anode surface and cathode surface are and the shorter the distance, the lower the forward loss. However, if it is formed in the center anode structure, the chip becomes elongated, and it cannot be said that it is an optimum design in consideration of mechanical strength.
図６及び図７では、電流の流れる方向を矢印で示す。半導体基板の一方の主面にアノード電極を形成し、半導体基板の他方の主面に対向してカソード電極を形成したショットキバリアダイオードでは、アノード電極からカソード電極に向かって順方向電流が縦方向に流れるのに対して、フリップチップ型ショットキバリアダイオードでは、図６及び図７の何れの構造でも、アノード（バリア）面からカソード面へ横方向に順方向電流が流れる。このとき、アノード電極とカソード電極とが近接する領域では相対的に大きな電流が流れ、電流集中により電流密度が増加して、順方向の電力損失が大きくなる問題が発生する。 6 and 7, the direction of current flow is indicated by arrows. In a Schottky barrier diode in which an anode electrode is formed on one main surface of a semiconductor substrate and a cathode electrode is formed opposite to the other main surface of the semiconductor substrate, a forward current flows in the vertical direction from the anode electrode to the cathode electrode. In contrast, in the flip-chip Schottky barrier diode, a forward current flows in the lateral direction from the anode (barrier) surface to the cathode surface in any of the structures shown in FIGS. At this time, a relatively large current flows in a region where the anode electrode and the cathode electrode are close to each other, and the current density increases due to current concentration, resulting in a problem that the power loss in the forward direction increases.
中央に配置したアノード電極から両側に配置したカソード電極に電流が分流して流れるセンターアノード構造のショットキバリアダイオードでは、電流密度の増加を比較的良好に抑制でき、順方向電力損失を減少できることが期待された。しかしながら、センターアノード構造のショットキバリアダイオードでは、アノード電極（アノード領域）の両側にカソード電極（カソード領域）を配置するため、半導体基板(5)の横方向長さＬ（図７）が長くなり、素子の平面サイズが増大すると共に、平面形状が横長チップになるため、機械的強度が低下する問題があった。
そこで、本発明は、平面サイズを比較的小さくでき、機械的強度も高く且つ順方向電力損失も小さいショットキ障壁を有する半導体素子を提供することを目的とする。
A Schottky barrier diode with a center anode structure, in which current flows from the centrally arranged anode electrode to the cathode electrodes arranged on both sides, is expected to be able to suppress the increase in current density relatively well and reduce forward power loss. It was done. However, in the Schottky barrier diode having the center anode structure, since the cathode electrode (cathode region) is disposed on both sides of the anode electrode (anode region), the lateral length L (FIG. 7) of the semiconductor substrate (5) is increased. As the planar size of the element increases and the planar shape becomes a horizontally long chip, there is a problem that the mechanical strength decreases.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a Schottky barrier that can have a relatively small planar size, high mechanical strength, and low forward power loss.
本発明によるショットキ障壁を有する半導体素子は、特定の導電型の第１の半導体領域(1)と、第１の半導体領域(1)よりも相対的に不純物濃度の低い同一の導電型の第２の半導体領域(2)とを有する半導体基板(5)と、半導体基板(5)の一方の主面に形成されて、第２の半導体領域(2)との接触面にショットキ障壁を形成する第１の電極(6)と、第１の電極(6)から離間して半導体基板(5)の一方の主面に形成され且つ第２の半導体領域(2)と低抵抗性接触する複数の第２の電極(7)とを備えている。第１の電極(6)は、一方向に延伸する一方の電極領域(8)と、一方向に対して直交する他方向に延伸し且つ一方の電極領域(8)の中央部と交差する中央部を有する他方の電極領域(9)とを備えている。複数の第２の電極(7)の各々は、第１の電極(6)の一方の電極領域(8)と他方の電極領域(9)から等距離離間して第１の電極(6)の一方の電極領域(8)と他方の電極領域(9)との間に配置されているので、第１の電極(6)と第２の電極(7)との間で平面的に見て放射状方向に電流が拡散して流れ、電流集中による電力損失を低減することができる。 A semiconductor device having a Schottky barrier according to the present invention includes a first semiconductor region (1) having a specific conductivity type and a second semiconductor layer having the same conductivity type and having a relatively lower impurity concentration than the first semiconductor region (1). A semiconductor substrate (5) having a second semiconductor region (2) and a Schottky barrier formed on one main surface of the semiconductor substrate (5) to form a contact surface with the second semiconductor region (2). A plurality of first electrodes (6) and a plurality of second electrodes formed on one main surface of the semiconductor substrate (5) apart from the first electrodes (6) and in low-resistance contact with the second semiconductor region (2). 2 electrodes (7). The first electrode (6) has one electrode region (8) extending in one direction and a center extending in the other direction orthogonal to the one direction and intersecting the central portion of the one electrode region (8). And the other electrode region (9) having a portion. Each of the plurality of second electrodes (7) is separated from one electrode region (8) of the first electrode (6) and the other electrode region (9) by an equal distance. Since it is disposed between one electrode region (8) and the other electrode region (9), it is radial when viewed in plan between the first electrode (6) and the second electrode (7). The electric current diffuses in the direction and the power loss due to the current concentration can be reduced.
ショットキ障壁を有する半導体素子を比較的小さい平面サイズで且つ高い機械的強度で形成することができる。 A semiconductor element having a Schottky barrier can be formed with a relatively small planar size and high mechanical strength.
センターアノード構造を有するフリップチップ型ショットキバリアダイオードに適用した本発明によるショットキ障壁を有する半導体素子の実施の形態を図１〜図５について説明する。図１〜図５に示す本発明の実施の形態及び実施例では、図６及び図７に示す従来のショットキバリアダイオードと同一の部分には同一の参照符号を付して、説明を省略する。 An embodiment of a semiconductor device having a Schottky barrier according to the present invention applied to a flip-chip Schottky barrier diode having a center anode structure will be described with reference to FIGS. In the embodiment and example of the present invention shown in FIGS. 1 to 5, the same parts as those of the conventional Schottky barrier diode shown in FIGS.
図１に示す本発明によるショットキバリアダイオードは、基本的に図７に示すショットキバリアダイオードと同一の断面構造を有するが、図７に示す構造とは下記の点で相違する。
［１］ 第１の電極(6)は、一方向に延伸する一方の電極領域(8)と、一方向に対して直交する他方向に延伸する他方の電極領域(9)とを有する。
［２］ 他方の電極領域(9)は、一方の電極領域(8)の中央側で一方の電極領域(8)に交差する。
［３］ 第１の電極(6)の一方の電極領域(8)と他方の電極領域(9)との間に第１の電極(6)の一方の電極領域(8)と他方の電極領域(9)から等距離離間して且つ互いに９０度以下の等角度間隔で複数の第２の電極(7)の各々を配置する。
The Schottky barrier diode according to the present invention shown in FIG. 1 basically has the same cross-sectional structure as the Schottky barrier diode shown in FIG. 7, but differs from the structure shown in FIG. 7 in the following points.
[1] The first electrode (6) has one electrode region (8) extending in one direction and the other electrode region (9) extending in another direction orthogonal to the one direction.
[2] The other electrode region (9) intersects one electrode region (8) on the center side of one electrode region (8).
[3] One electrode region (8) and the other electrode region of the first electrode (6) between one electrode region (8) and the other electrode region (9) of the first electrode (6) Each of the plurality of second electrodes (7) is arranged equidistant from (9) and at equal angular intervals of 90 degrees or less.
第１の電極(6)は、図２又は図３に示すように連続する十字形に形成され、第２の電極(7)は、第１の電極(6)から離間して島状に形成される。図７に示す構造と同様に、第１の電極(6)と第２の電極(7)間に流れる電流の横方向電流通路を構成する第１の半導体領域(1)の比抵抗が小さいため、第１の半導体領域(1)では、順方向電圧降下を比較的小さく抑えることができる。図２及び図３に示すように、第１の電極(6)は、Ｘ軸方向に延伸する一方の電極領域(8)と、Ｘ軸方向に直交するＹ軸方向に延伸する他方の電極領域(9)とを有する十字形状の平面形状を有する。一方の電極領域(8)の長さは、他方の電極領域(9)の幅より大きく、他方の電極領域(9)の長さは、一方の電極領域(8)の幅より大きいため、第１の電極(6)は、一方の電極領域(8)の両端部が他方の電極領域(9)の幅方向に突出して形成された突出部と、他方の電極領域(9)の両端部が一方の電極領域(8)の幅方向に突出して形成された突出部とを有し、図２又は図３のように平面十字形状を有する。第２の半導体領域(2)は、第１の電極(6)と同様に十字形状を有する。即ち、第２の半導体領域(2)は、Ｘ軸方向に延伸する一方の半導体領域(2a)と、Ｘ軸方向に直交するＹ軸方向に延伸する他方の半導体領域(2b)とを有する十字形状の平面形状を有する。一方の半導体領域(2a)の長さは、他方の半導体領域(2b)の幅より大きく、他方の半導体領域(2b)の長さは、一方の半導体領域(2a)の幅より大きいため、第２の半導体領域(2)は、一方の半導体領域(2a)の両端部が他方の半導体領域(2b)の幅方向に突出して形成された突出部と、他方の半導体領域(2b)の両端部が一方の半導体領域(2a)の幅方向に突出して形成された突出部とを有し、図２又は図３のように平面十字形状を有する。第２の半導体領域(2)の一方の半導体領域(2a)及び他方の半導体領域(2b)の幅、長さは、第１の電極(6)の一方の電極領域(8)及び他方の電極領域(9)の幅、長さよりも大きい。従って、図２又は図３のように、第２の半導体領域(2)は第１の電極(6)よりも外側に延伸する。第２の半導体領域(2)に隣接して包囲する第４の半導体領域(4)も中抜きの十字環状形状を有する。 The first electrode (6) is formed in a continuous cross shape as shown in FIG. 2 or FIG. 3, and the second electrode (7) is formed in an island shape apart from the first electrode (6). Is done. Similar to the structure shown in FIG. 7, the specific resistance of the first semiconductor region (1) constituting the lateral current path of the current flowing between the first electrode (6) and the second electrode (7) is small. In the first semiconductor region (1), the forward voltage drop can be kept relatively small. As shown in FIGS. 2 and 3, the first electrode (6) has one electrode region (8) extending in the X-axis direction and the other electrode region extending in the Y-axis direction orthogonal to the X-axis direction. (9) and having a cross-shaped planar shape. The length of one electrode region (8) is larger than the width of the other electrode region (9), and the length of the other electrode region (9) is larger than the width of one electrode region (8). One electrode (6) has both ends of one electrode region (8) protruding in the width direction of the other electrode region (9) and both ends of the other electrode region (9). One electrode region (8) has a protruding portion formed to protrude in the width direction, and has a planar cross shape as shown in FIG. Similar to the first electrode (6), the second semiconductor region (2) has a cross shape. That is, the second semiconductor region (2) is a cross having one semiconductor region (2a) extending in the X-axis direction and the other semiconductor region (2b) extending in the Y-axis direction orthogonal to the X-axis direction. It has a planar shape. The length of one semiconductor region (2a) is larger than the width of the other semiconductor region (2b), and the length of the other semiconductor region (2b) is larger than the width of one semiconductor region (2a). The two semiconductor regions (2) are formed so that both end portions of one semiconductor region (2a) protrude in the width direction of the other semiconductor region (2b) and both end portions of the other semiconductor region (2b). Has a protruding portion formed so as to protrude in the width direction of one of the semiconductor regions (2a), and has a planar cross shape as shown in FIG. The width and length of one semiconductor region (2a) and the other semiconductor region (2b) of the second semiconductor region (2) are the same as those of the one electrode region (8) and the other electrode of the first electrode (6). It is larger than the width and length of the area (9). Therefore, as shown in FIG. 2 or FIG. 3, the second semiconductor region (2) extends outward from the first electrode (6). The fourth semiconductor region (4) surrounding and adjacent to the second semiconductor region (2) also has a hollow cross shape.
半導体基板(5)の外周縁と第２の半導体領域(2)の間に配置に形成される第３の半導体領域(3)は、平面的に見て、半導体基板(5)の角部に配置された４つの幅広部分(3a)と、幅広部分(3a)の間に配置された幅狭部分(3b)とを有する。 The third semiconductor region (3) formed between the outer periphery of the semiconductor substrate (5) and the second semiconductor region (2) is located at the corner of the semiconductor substrate (5) when viewed in plan. It has four wide portions (3a) arranged and a narrow portion (3b) arranged between the wide portions (3a).
図１に示すように、第２の半導体領域(2)上に形成される第１の電極(6)は、平面的に見て第２の半導体領域(2)の内側に十字形状に形成される。第１の電極(6)の外周縁と第２の半導体領域(2)の外周縁との間隔は、第２の半導体領域(2)の全周に亘って略均一である。第２の半導体領域(2)の中央部、一方の電極領域(8)の両端部、他方の電極領域(9)の両端部の上に互いに離間する５つのバンプ電極（突起形状電極）(10)が第１の電極(6)上に形成される。しかしながら、図３の実施の形態に示すように、第１の電極(6)に一致させて、バンプ電極を(10)を十字形状に形成しても良い。第３の半導体領域(3)の４つの幅広部分(3a)の上方に形成される第２の電極(7)は互いに離間して配置され、それぞれの上にはバンプ電極(11)が形成される。 As shown in FIG. 1, the first electrode (6) formed on the second semiconductor region (2) is formed in a cross shape inside the second semiconductor region (2) in plan view. The The distance between the outer periphery of the first electrode (6) and the outer periphery of the second semiconductor region (2) is substantially uniform over the entire periphery of the second semiconductor region (2). Five bump electrodes (protruding electrodes) spaced apart from each other on the center of the second semiconductor region (2), both ends of one electrode region (8), and both ends of the other electrode region (9) (10) ) Is formed on the first electrode (6). However, as shown in the embodiment of FIG. 3, the bump electrode (10) may be formed in a cross shape so as to coincide with the first electrode (6). The second electrodes (7) formed above the four wide portions (3a) of the third semiconductor region (3) are spaced apart from each other, and bump electrodes (11) are formed on each of them. The
本実施の形態によるショットキバリアダイオードでは、以下の作用効果が得られる。
<1> 第１の電極(6)を平面十字形状に形成し、第２の電極(7)を支持する第３の半導体領域(3)の幅広部分(3a)は、第１の電極(6)の突出部分の間に配置されるため、高い機械的強度で且つ比較的小さい正方形の平面サイズで素子を形成できる。
<2> 一方の電極から他方の電極に平面的に見て放射状に拡散して電流を流すことができるので、電流密度の増加及び電流集中による順方向電力損失を低減することができる。
<3> 素子の取り付け向きが９０度回転しても、電極の極性が逆にならず、基板等への実装時に実装ミスを回避できる。
In the Schottky barrier diode according to the present embodiment, the following operational effects can be obtained.
<1> The first electrode (6) is formed into a planar cross shape, and the wide portion (3a) of the third semiconductor region (3) supporting the second electrode (7) is formed by the first electrode (6 ) Between the protruding portions of the element), the device can be formed with high mechanical strength and a relatively small square plane size.
<2> A current can be flowed by diffusing radially from one electrode to the other electrode in a plan view, so that an increase in current density and forward power loss due to current concentration can be reduced.
<3> Even if the mounting direction of the element is rotated 90 degrees, the polarity of the electrodes is not reversed, and mounting errors can be avoided when mounting on a substrate or the like.
本発明の前記実施の形態では、特定の導電型をＮ型として表示したが、その代わりに、第１の半導体領域(1)、第２の半導体領域(2)及び第３の半導体領域(3)をＰ型半導体領域とし、第４の半導体領域(4)をＮ型半導体領域としてもよい。 In the embodiment of the present invention, the specific conductivity type is indicated as N-type, but instead, the first semiconductor region (1), the second semiconductor region (2), and the third semiconductor region (3 ) May be a P-type semiconductor region, and the fourth semiconductor region (4) may be an N-type semiconductor region.
シミュレーションを利用して最適な比率を検討し、電流効率の良いアノード電極とカソード電極との面積比を求めた本発明の実施例を図４及び図５について説明する。
シミュレーションモデル（Simulation model）を図４に示す。奥行き(長さ)を一定とするカソード電極幅：ＫＷをパラメーターとして、２次元的に電流密度を計算し、アノード電極幅：ＡＷを小、中、大として、各幅に対して目標の順方向電圧値ＶFを得た。図５は、シミュレーションにより横軸をアノード幅比＝ＡＷ／（ＡＷ＋ＫＷ）、縦軸をＶF値を一定にしたときの電流密度ＪF（A/cm2）としてアノード幅比と電流密度（Ratio of anode width vs ＪF）との関係を示す。どのアノード幅に対しても効率よく電流を流せるカソードの幅が存在することが図５から判明した。電流値１.０AでＶF≦０.４５Vを目標とした場合、シミュレーションの結果から、最大の電流が得られる最小のチップサイズは１.４mm2であることが確認された。またチップ平面パターンを上下・左右対称にして、実装時にチップの向きが変わっても逆極性を回避できるように設計した。
An embodiment of the present invention in which the optimum ratio is examined using simulation and the area ratio between the anode electrode and the cathode electrode with good current efficiency is obtained will be described with reference to FIGS.
A simulation model is shown in FIG. Cathode electrode width with constant depth (length): KW is a parameter and current density is calculated two-dimensionally. Anode electrode width: AW is small, medium and large. A voltage value V F was obtained. Figure 5 is a simulation by the horizontal axis of the anode width ratio = AW / (AW + KW) , anode width ratio as the current density when the vertical axis was constant V F value J F (A / cm 2) and the current density (Ratio of anode width vs J F ). It has been found from FIG. 5 that there is a width of the cathode that allows current to flow efficiently for any anode width. When targeting a current value of 1.0 A and V F ≦ 0.45 V, it was confirmed from the simulation results that the minimum chip size for obtaining the maximum current was 1.4 mm 2 . In addition, the chip plane pattern is symmetrical up and down and left and right so that the reverse polarity can be avoided even if the orientation of the chip changes during mounting.
また、放熱性を考慮して半田より熱伝導率が大きい銅により厚いポスト状バンプ電極(10)、(11)構造を形成した。また、半田濡れを改善するためにニッケル金メッキを銅ポストの表面に施した。電極のサイズ及び形状は、実装すべき基板の配線パターンに対応して自由に設計することができる。 In consideration of heat dissipation, thick post-shaped bump electrodes (10) and (11) were formed of copper having a thermal conductivity higher than that of solder. In addition, nickel gold plating was applied to the surface of the copper post in order to improve solder wetting. The size and shape of the electrode can be freely designed according to the wiring pattern of the substrate to be mounted.
ショットキバリアダイオードに限定されず、ショットキ障壁を有する電界効果トランジスタ、ゲート回路等他の半導体素子にも本発明を適用することができる。 The present invention is not limited to a Schottky barrier diode, and can be applied to other semiconductor elements such as a field effect transistor having a Schottky barrier and a gate circuit.
(1)・・第１の半導体領域、 (2)・・第２の半導体領域、 (3)・・第３の半導体領域、 (4)・・第４の半導体領域、 (5)・・半導体基板、 (6)・・第１の電極、 (7)・・第２の電極、 (8)・・一方の電極領域、 (9)・・他方の電極領域、 (1) ・ ・ first semiconductor region, (2) ・ ・ second semiconductor region, (3) ・ ・ third semiconductor region, (4) ・ ・ fourth semiconductor region, (5) ・ ・ semiconductor A substrate, (6) .. first electrode, (7) .. second electrode, (8) .. one electrode region, (9) .. other electrode region,
Claims (3)
前記半導体基板の一方の主面に形成されて、前記第２の半導体領域との接触面にショットキ障壁を形成する第１の電極と、
該第１の電極から離間して前記半導体基板の一方の主面に形成され且つ前記第２の半導体領域と低抵抗性接触する複数の第２の電極とを備えたショットキ障壁を有する半導体素子において、
前記第１の電極は、一方向に延伸する一方の電極領域と、前記一方向に対して直交する他方向に延伸し且つ前記一方の電極領域の中央部と交差する中央部を有する他方の電極領域とを備え、
複数の前記第２の電極の各々は、前記第１の電極の一方の電極領域と他方の電極領域から等距離離間して前記第１の電極の一方の電極領域と他方の電極領域との間に配置されていることを特徴とするショットキ障壁を有する半導体素子。 A semiconductor substrate having a first semiconductor region of a specific conductivity type and a second semiconductor region of the same conductivity type having a lower impurity concentration than the first semiconductor region;
A first electrode formed on one main surface of the semiconductor substrate and forming a Schottky barrier on a contact surface with the second semiconductor region;
In a semiconductor device having a Schottky barrier including a plurality of second electrodes formed on one main surface of the semiconductor substrate apart from the first electrode and in low resistance contact with the second semiconductor region ,
The first electrode has one electrode region extending in one direction and the other electrode having a central portion extending in the other direction orthogonal to the one direction and intersecting the central portion of the one electrode region. With areas,
Each of the plurality of second electrodes is equidistant from one electrode region and the other electrode region of the first electrode and between the one electrode region and the other electrode region of the first electrode. A semiconductor device having a Schottky barrier, wherein
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| US8546905B2 (en) | 2008-03-27 | 2013-10-01 | Renesas Electronics Corporation | Semiconductor integrated circuit device and a method of manufacturing the same |
| CN113540242A (en) * | 2020-04-15 | 2021-10-22 | 株式会社东芝 | Semiconductor device with a plurality of semiconductor chips |
| CN113540242B (en) * | 2020-04-15 | 2023-06-27 | 株式会社东芝 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
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