JP2005156197A - Signal processing circuit with data taking-in and check function, and its signal processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing circuit and its processing method which includes data taking-in speeding up data taking-in from an A/D converter to a memory by ensuring the reliability of data. <P>SOLUTION: The method is characterized by data checking conducted when digital data converted from taken-in analog signal to digital signal is taken into a memory. Furthermore, a check bit is added to the digital data taken out of the A/D converter. The circuit also has a DMA capable of taking-in at every block and a check bit addition device for counting at every block and adding a check bit. It may check the continuity in every block and/or data omission in every block. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a signal processing circuit for a digital signal converted from an analog signal and a signal processing method thereof.

  FIG. 1 shows a data capturing unit related to the conventional technique. In a digital signal processing circuit, when data taken in by an A / D converter is taken into a memory, conventionally, each piece of data (a bit) is taken in, and an interruption process is entered each time, so that the taking speed becomes slow. There was a problem. On the other hand, in order to solve the above-mentioned problem, a DMA is provided in the memory of the digital signal processing circuit, and by fetching one block at a time, interrupt processing is performed only once, and the speed can be increased. Since there is a problem in ensuring the reliability of data import, such as missing data in blocks, a check function for ensuring reliability was necessary.

Japanese Patent Application Laid-Open No. 06-180764 JP 05-289715 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a signal processing circuit and a processing method thereof including data fetching that increases data fetching speed from an A / D converter to a memory while ensuring data reliability.

  In order to solve the above-described problems, the present invention is characterized in that a data check is performed when digital data obtained by converting a captured analog signal into a digital signal is loaded into a memory. Further, a check bit is added to the digital data extracted from the A / D converter.

  In addition, according to the present invention, there is a DMA that enables fetching for each block and a check bit adding device that counts and adds a check bit for each block, and the continuity for each block and / or It is characterized by checking data missing for each block. Further, it is characterized in that it is checked whether or not the fetched data is normal.

  In addition, a data identification code is added as a check bit to data composed of a plurality of types of data, and each type of data is stored in a predetermined buffer according to the discrimination result of the identification code. And

  According to the present invention, high-speed and highly reliable data capture can be realized.

  According to the present invention, it is possible to check the continuity for each block, check for missing data for each block, and improve the reliability of fetched data.

  Furthermore, it is possible to check whether or not the captured data is normal.

  In addition, the type of captured data can be distinguished or the captured data can be held by type.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. In addition, although the Example described below is an example regarding the digital signal processing circuit of 2 frequency CW (Continuous Wave) system millimeter wave radar, this invention is not interpreted limitedly to this Example.

A diagram relating to the two-frequency CW system is shown in FIG. The two-frequency CW system is a system that transmits radio waves having two types of frequencies (CF1 and CF2) and obtains the surrounding environment as a signal by reflected waves (F1 and F2) accompanied by Doppler shift.

  First, an outline of a general millimeter wave radar apparatus will be described with reference to FIG.

  The millimeter wave radar 1 is attached in front of the host vehicle 15. The millimeter wave radar 1 includes a transmission control unit 3, and a modulation signal for switching two frequencies is generated and output from the transmission control unit 3. A diagram of a modulation signal for switching between two frequencies is shown in the uppermost part of FIG. The modulation width in the figure is adjusted so that the transmission wave outputs a predetermined frequency.

The modulation signal output from the transmission control unit 3 is supplied to the oscillator 4. The oscillator 4 generates an electromagnetic wave in the millimeter wave band based on the supplied modulation signal, and is transmitted to the front of the host vehicle 15 via the transmission antenna 5.

  The millimeter wave band electromagnetic wave transmitted from the transmission antenna 5 is reflected by a preceding vehicle, a roadside object or the like (hereinafter referred to as a target 6), and is received by the reception antenna 7. The reflected wave received by the receiving antenna 7 is mixed with the transmission wave by the mixer 8, thereby frequency-converting the frequency from the millimeter wave band to the IF (Intermediate Frequency) band.

A beat signal is extracted by mixing of the mixer 8, and the beat signal is amplified by the analog signal processing unit 9. The beat signal is a signal representing a phase difference extracted at the time of superposing signals having two slightly different frequencies. The beat signal amplified by the analog signal processing unit 9 is converted into a digital signal by the A / D converter 10 and taken into the target processing unit 12. In the target processing unit 12, the digital signal is taken into the memory 26 through a direct access memory (hereinafter referred to as DMA) 25, and FFT (Fast
Fourier Transform (Fast Fourier Transform) processing unit 11 performs FFT processing to obtain a target peak. Detailed processing contents of the analog signal processing unit 9, the A / D converter 10, and the FFT processing unit 11 will be described later.

  The target peak obtained by the FFT processing unit 11 is subjected to signal processing by the tracker processing unit 27, and relative speed, distance, and the like (hereinafter referred to as target information) are calculated.

The target information obtained by the target processing unit 12 is transmitted to a host system 14 such as an ACC (Adaptive Cruise Control) control unit or an inter-vehicle distance alarm unit via a communication driver 13 for vehicle control, alarm control for the driver, and the like. Used.

  Next, detailed processing contents of the analog signal processing unit 9 will be described with reference to FIG. In the figure, an internal block of the analog signal processing unit 9 is shown.

  The analog signal processing unit 9 includes a preamplifier unit 16, a DC servo unit 17, a demodulation unit 19, an S / H (Sample & amp / Hold) unit 20, and a secondary amplifier unit 21.

  The beat signal input from the mixer 8 to the analog signal processing unit 9 is amplified by the preamplifier unit 16. The DC servo unit 17 feeds back the output signal of the preamplifier unit 16 to the input terminal of the preamplifier 16 and functions to cancel the DC offset of the beat signal.

  On the signal amplified by the preamplifier unit 16, beat signals (F1, F2) having different phases corresponding to two transmission frequencies (CF1, CF2) modulated at the time of transmission from the transmission antenna 5 are superimposed. Therefore, the signal amplified by the preamplifier unit 16 is demodulated by the demodulator 19.

  The two types of beat signals (F1, F2) demodulated by the demodulator 19 are sampled and held by the S / H unit 20, amplified again by the secondary amplifier unit 21, and then A / D converter 10 Is output.

  Next, in FIG. 5, a waveform diagram for explaining operations of the A / D converter 10 and the FFT processing unit 11 is shown.

(A) in the figure shows the time waveform of the beat signal 22 amplified by the secondary amplifier unit 21, the vertical axis represents signal intensity, and the horizontal axis represents time. The beat signal 22 is sampled by the A / D converter 10 at an A / D sampling frequency Fs [Hz] (A / D sampling period T [s] = 1 / Fs), as shown in FIG. Sample data 23 is obtained (in (b) in the figure, as in (a), the vertical axis represents signal intensity and the horizontal axis represents time).

  The data sampled by the A / D converter 10 is subjected to FFT processing by the FFT processing unit 11 with the FFT sample point N as one block, and as shown in (c) in the figure, Fs / 2 [Hz ] Is the frequency spectrum 24 of the beat signal with the upper frequency limit. In the figure, the vertical axis represents signal intensity and the horizontal axis represents frequency.

  One embodiment of the present invention is an example when applied to the above-described millimeter wave radar device. FIG. 1 shows an embodiment of a signal processing circuit with a data acquisition check function according to the present invention that realizes high speed and high reliability in data acquisition from the A / D converter 10 to the target processing unit 12 inside the apparatus. This will be described with reference to FIG.

  In FIG. 6, the analog signal obtained in the analog signal processing unit by the transmission wave to the target and the reception wave from the target through the antennas 5 and 7 and the mixer 8 is digitized by the A / D converter 10, For the digitized signal, a check bit adding device 2 is used to add a counter value of several bits and a data identification code for each piece of data. A timing chart with the counter value added is shown in FIG. FIG. 1 shows a diagram of one piece of data, and shows a timing chart of the present invention in which a check bit counter and a data identification code are added to what has conventionally been only data bits. At this time, the number of data in one block is N, which is the number of sampling data in the FFT processing. In FIG. 6, when the data is taken into the target processing unit 12, the data check shown in FIG. 7 is performed in the target processing unit.

  FIG. 7 shows a flowchart of the present embodiment, in which three types of checks of Steps 1, 2, and 3 are performed on the acquired block data after A / D conversion.

  In the block boundary check of Step 1, as shown in FIG. 8, the last counter value of the block (x-1th, x is an integer) stored in the ring buffer and the sampling is completed this time. By comparing the head counter values of the blocks (xth), it is checked whether the output data from the A / D converter between the blocks is continuous.

In the sampling skip check in Step 2, as shown in FIG. 9, the (first counter value) of the block (xth) that has been sampled this time is compared with (final counter value + 1), and the difference is 2 ^m (m is It is checked whether the number of additional counters is a multiple of m <n and 2 ⁿ is the number of data in one block).

  In Step 3, since the millimeter wave radar has two buffers F1 and F2, as shown in FIG. 10, the data identification code of the block which has been sampled this time is checked, and F1 and F2 are respectively stored in the F1 and F2 buffers. Check if data is stored.

  In Step 4, if one or more of the data checks in Steps 1, 2, and 3 are determined to be abnormal, an error code is set.

  In Step 5, it is determined whether or not an error code has occurred. If it is determined that an error has occurred, the information is transmitted to the outside.

  If an error is determined in Step 5, in Step 6, an FFT skip request is made to reinitialize the DMA.

  By the above processing, when data fetching fails, it is possible to fetch only error-free data by skipping erroneously fetched one block of data.

The figure showing the outline | summary of this invention. The figure showing an A / D converter, a signal frequency, and a modulation signal waveform. Explanatory drawing of a common millimeter wave radar apparatus. The block diagram of the analog signal processing part of a millimeter wave radar apparatus. The wave form diagram for demonstrating operation | movement of an A / D converter and an FFT process part. The schematic block diagram of the signal processing circuit with a check bit addition apparatus which is one Embodiment of this invention. The figure which shows the signal processing operation | movement flowchart in this invention. The figure explaining the block boundary check which is one of the signal processing operations in this invention. The figure explaining the sampling skip check which is one of the signal processing operations in the present invention. The figure explaining F1, F2 data check which is one of the signal processing operations in this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Millimeter wave radar, 2 ... Check bit addition apparatus, 3 ... Transmission control part, 4 ... Oscillator, 5, 7 ... Antenna, 6 ... Target, 8 ... Mixer, 9 ... Analog signal processing part, 10 ... A / D conversion 11 ... FFT processing unit, 12 ... target processing unit, 13 ... communication driver, 14 ... host system, 15 ... own vehicle, 16 ... preamplifier unit, 17 ... DC servo unit, 19 ... demodulation unit,
20 ... S / H unit, 21 ... secondary amplifier unit, 25 ... DMA unit, 26 ... memory unit having two buffers for storing data, 27 ... tracker processing unit.

Claims (4)

A sensor that outputs an analog signal that changes according to changes in the surrounding environment;
A converter for converting an analog signal from the sensor into a digital signal;
A signal processing circuit for processing a sensor output signal converted into a digital value by the A / D converter, wherein the signal processing circuit includes a memory including a direct memory access (DMA), and a digital captured by the converter A check bit adding device for adding a check bit to the digital data of the signal. By the direct memory access, one block ((a + b) bits × N, a is the data bit width, b is the check bit width, and N is A signal processing circuit which takes in digital data every sampling data number (N = 2 ⁿ , n is an integer). The signal processing circuit according to claim 1,
The signal processing circuit includes a counter that counts every predetermined bit using the check bit added by the check bit adding device. The signal processing circuit according to claim 1,
The signal processing circuit uses a data identification code for a check bit added using the check bit adding device. In any one of Claims 2 thru | or 3,
A signal processing circuit for checking data of the converter fetched by the direct access memory from the added check bit.

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