JP2005151606A - Dc-dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce switching loss of a step-up/down type DC-DC converter transferring power from the low voltage side circuit to the high voltage side circuit or reversely. <P>SOLUTION: When power is transferred from the low voltage side circuit (3) to the high voltage side circuit (2), a second transistor connected to the low voltage side circuit side is turned on/off while turning a first transistor (Q1) connected to the high voltage side circuit side off. A gate control circuit (4) for controlling the second transistor calculates ON time of the second transistor according to a designated transfer power command value (Pr). If the period of a zero-cross detection signal delivered from a zero-cross detection circuit (5) is not shorter than a predetermined value, the second transistor is turned on for the ON time calculated after receiving the zero-cross detection signal. If the period of the zero-cross detection signal is shorter than the predetermined value, the second transistor is turned on for the ON time calculated when a predetermined time elapsed after start of immediately preceding ON. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a step-up / step-down DC-DC converter that transfers electric power between two power supplies or circuits having different voltages from a low voltage side to a high voltage side, or vice versa by an external selection signal.

  For example, in an electric vehicle or a hybrid vehicle, a DC-DC converter is provided in front of an inverter circuit for driving a traveling motor, and the battery voltage (low-voltage side circuit) is boosted by this converter so as to increase the inverter circuit (high-voltage side). Circuit). When the traveling motor is in a regenerative state, the regenerative electric power (high-voltage side circuit) is stepped down by a DC-DC converter to charge the battery (low-voltage side circuit).

  FIG. 2 is a circuit example of the step-up / step-down DC-DC converter 1 used for such a purpose. In the figure, transistors Q1 and Q2 are power MOS transistors for switching, and are connected in series between the input / output terminal N2 of the high voltage side circuit 2 and the ground GND. Free wheel diodes D1 and D2 are connected in antiparallel to the transistors Q1 and Q2, respectively. A reactor L for storing and releasing energy is connected between the input / output terminal N1 of the low-voltage side circuit 3 and the interconnection point N3 of the transistors Q1 and Q2, and between the input / output terminals N1 and N2 and the ground GND, respectively. Smoothing capacitors C1 and C2 are connected.

  The voltage of the low-voltage side circuit 3 is V1, the voltage of the high-voltage side circuit 2 is V2, the current flowing through the reactor L from the low-voltage side circuit 3 toward the interconnection point N3 is IL, and the average from the low-voltage side circuit 3 to the high-voltage side circuit 2 The operation when power is transferred with power (transfer power command value) Pr will be described. The direction in which power is transferred is instructed to the gate control circuit 3 by an external selection signal. In accordance with the instruction, the gate control circuit 3 outputs a signal that is always OFF to the transistor Q1, and outputs a drive pulse for the ON time calculated as follows based on the transfer power command value Pr to the transistor Q2.

  When the transistor Q2 is turned on, a current flows from the low voltage side circuit 3 to the ground GND through the reactor L and the transistor Q2. Reactor current IL flowing through reactor L increases linearly as shown in the time (0 to t0) period (ON period of transistor Q2) of (1) in FIG. When the transistor Q2 is turned OFF at the time t0 when the value of the reactor current IL becomes I0, the electromagnetic energy accumulated in the reactor L during the ON period of the transistor Q2 is released to the high voltage side circuit 2 through the diode D1. . Reactor current IL decreases linearly during time (t0 to t1) (the OFF period of transistor Q2) and becomes zero at time t1.

The average value P1 of the power output from the low voltage side circuit 3 during the time t1 of one cycle is:
^{P1 = (V1 2/2 ·} L) · t0
It becomes. The gate control circuit 4 calculates and controls the value of the ON time t0 of the transistor Q2 so that the value of the average power P1 becomes equal to the transfer power command value Pr. Therefore,
t0 = 2 · L · Pr / V1 ² (1) In other words, the gate control circuit 4 turns on the transistor Q2 after turning it on for the time t0 calculated by the equation (1). Then, after the reactor current IL becomes zero, the operation of turning on the transistor Q2 is repeated again for t0 time. As a result, power equal to the transfer power command value Pr is transferred from the low voltage side circuit 3 to the high voltage side circuit 2.

The zero cross detection circuit 5 detects that the reactor current IL has become zero. The zero cross detection circuit 5 detects the moment when the potential difference between both ends of the reactor L becomes zero, determines that the reactor current IL becomes zero, and notifies the gate control circuit 4 of it.
As described above, when the current flowing through the transistor Q2 performing the switching operation becomes zero, the control for switching the transistor Q2 from OFF to ON (hereinafter referred to as zero-crossing control) is performed from OFF to ON while the current is flowing. There is an advantage that switching loss can be reduced as compared with PWM control for switching.

However, in the case of this zero cross control, when the value of the transfer power command value Pr becomes small, the ON time t0 of the transistor Q2 calculated by the equation (1) becomes short. When the ON time t0 is shortened, as shown in FIGS. 9 (1), (2), and (3), the ON / OFF cycle t1 of the transistor Q2 is also gradually shortened, and the reciprocal frequency is shown in FIG. Increasing gradually. In the zero cross control, when the transistor Q2 shifts from OFF to ON, switching is performed in a state where the current is zero, so that no switching loss occurs. However, switching from ON to OFF is performed in a state where a current flows, so that switching loss occurs. Therefore, when the switching frequency of the transistor Q2 is increased, there is a problem that the switching loss is increased accordingly.
Japanese Patent Application No. 2003-068086

  The present invention has been made to solve such problems of the prior art, and between two power supplies or circuits having different voltages, an external selection signal causes a low voltage from the low voltage side or vice versa. It is an object to reduce switching loss of a switching transistor in a step-up / step-down DC-DC converter that transfers power to the side.

  In order to achieve the above object, the invention according to claim 1 is a step-up / step-down type DC-DC which transfers power between two circuits having different voltages from a low voltage side to a high voltage side or vice versa by an external selection signal. A converter (1) comprising first and second transistors (D1 and D2) connected in series with anti-parallel diodes (D1 and D2) between the input / output terminal (N2) of the high-voltage side circuit (2) and the ground. Q1, Q2), the reactor (L) connected between the interconnection point (N3) of the two transistors and the input / output terminal (N1) of the low-voltage side circuit (3), and the current flowing through the reactor becomes zero And a gate control circuit (4) for controlling the switching operation of the first and second transistors, the gate control circuit comprising the low voltage side High from circuit When power is transferred to the side circuit, the ON / OFF of the second transistor connected to the low voltage side circuit side is controlled with the first transistor connected to the high voltage side circuit turned OFF, When power is transferred from the side circuit to the low voltage side circuit, the ON / OFF of the first transistor is controlled while the second transistor is OFF, and the first transistor is controlled according to the transfer power command value instructed from the outside. The ON time for turning on the first or second transistor is calculated, and the time from when the first or second transistor is turned on until the zero-cross detection signal is received from the zero-cross detection circuit is a predetermined value or more. In this case, the first or second transistor is turned on for the ON time immediately after receiving the zero cross detection signal, and the zero cross detection signal is received. When the predetermined time is less than the predetermined value, the first or second transistor is turned ON for the ON time immediately after the predetermined value time has elapsed from the immediately preceding ON start time. -DC converter.

According to the DC-DC converter having such a configuration, when the transfer power command value decreases to a predetermined value or less, the switching frequency of the first or second transistor becomes constant, so that the switching loss is reduced. There is an effect of preventing further increase.
The invention according to claim 2 is the DC-DC converter according to claim 1, wherein the gate control circuit transfers the power from the low-voltage side circuit to the high-voltage side circuit. When the ON / OFF of the second transistor is controlled with the first transistor turned OFF and power is transferred from the high voltage side circuit to the low voltage side circuit, the first transistor is turned ON with the second transistor turned OFF. / ON is controlled, the ON time for turning on the first or second transistor is calculated according to the transfer power command value instructed from the outside, and the first or second transistor is turned on, and then When the time until the reception of the zero-cross detection signal is equal to or greater than the first predetermined value, the first or second time period from the time of receiving the zero-cross detection signal to the ON time When the time from turning on the transistor and receiving the zero-cross detection signal is less than the first predetermined value and greater than or equal to the second predetermined value, the first cross-section is further received from the time of reception of the zero-cross detection signal. The first or second transistor is turned on for the ON time immediately after the time obtained by multiplying the difference between the predetermined value of the predetermined time and the time until the zero-cross detection signal is received by a constant ratio smaller than 1 and the zero-cross detection signal Is less than the second predetermined value, the difference between the first predetermined value and the second predetermined value is the second predetermined value from the immediately preceding ON start time. The DC-DC converter is characterized in that the first or second transistor is turned on for the ON time immediately after the time obtained by adding a time multiplied by a constant ratio smaller than 1 elapses.

  Even when the transfer power command value Pr is reduced by the DC-DC converter having such a configuration, an increase in switching loss of the first or second transistor is suppressed, so that an increase in switching loss is prevented. Play.

  The invention according to claim 3 is the DC-DC converter according to claim 1 or 2, wherein the time from when the first or second transistor is turned on until the zero-cross detection signal is received. Instead of using DC-, the time from the start of ON of the first or second transistor calculated based on the transfer power command value until the current flowing through the reactor becomes zero is used. It is a DC converter.

  According to the DC-DC converter having such a configuration, the zero cross detection circuit can be eliminated and the circuit can be simplified. Further, an increase in switching loss of the first or second transistor is also prevented.

(First embodiment)
The basic circuit configuration of the step-up / step-down DC-DC converter in the present embodiment is the same as the DC-DC converter 1 in FIG. 2 described in “Background Art”. The only difference is the arithmetic control logic of the gate control circuit 4. Therefore, the circuit configuration will be described with reference to FIG.

  A power MOS transistor or IGBT is used for the transistors Q1 and Q2. The direction in which power is transferred is determined by an external selection signal given to the gate control circuit 4. When power is transferred from the low voltage side circuit 3 to the high voltage side circuit 2, the gate control circuit 4 turns on / off the transistor Q2 while keeping the transistor Q1 off. In this case, the gate control circuit 4 controls the transistor Q2 by calculating the ON time so that the transferred power matches the transfer power command value Pr designated from the outside.

On the other hand, when power is transferred from the high voltage side circuit 2 to the low voltage side circuit 3, the gate control circuit 4 turns the transistor Q1 on and off while keeping the transistor Q2 off. In this case, the gate control circuit 4 controls the transistor Q1 by calculating the ON time so that the transferred power matches the transfer power command value Pr designated from the outside.
Regardless of the direction in which the power is transferred, the arithmetic control logic performed to control the transistor that the gate control circuit 4 performs the ON / OFF operation is the same, so the power is transferred from the low-voltage side circuit 3 to the high-voltage side circuit 2. The case where it does is demonstrated.

Assume that the transistor Q2 is turned on for the time t0 as shown in (1) of FIG. 3 from the initial state (time t = 0) in which the transistors Q1 and Q2 are both OFF and the reactor current IL flowing through the reactor L is zero. If the ON resistance of the transistor Q2 is zero and the time derivative of the reactor current IL is represented by (IL) ′,
V1 = L · (IL) ′
Solving with the initial conditions,
IL = (V1 / L) · t
Therefore, the reactor current IL increases linearly as shown in (2) of FIG. When the value of the reactor current IL at time t0 is I0,
I0 = (V1 / L) · t0
Thus, the ON time t0 of the transistor Q2 is calculated as follows.
t0 = (L / V1) · I0 (2) Formula

When the transistor Q2 is turned off at time t0, the electromagnetic energy accumulated in the reactor L flows into the high voltage side circuit 2 through the diode D1. Assuming that the forward voltage of the diode D1 is zero, the following equation is established after the transistor Q2 is turned off.
V1 = L · (IL) ′ + V2
Solving the above equation under the condition of IL = I0 at time t0,
IL =-((V2-V1) / L) .t + (V2 / L) .t0
Thus, the current IL decreases linearly as shown in (2) of FIG.

If the time when reactor current IL becomes zero is t1, t1 is calculated as follows.
t1 = t0 · V2 / (V2−V1) (3) On the other hand, the energy E1 supplied from the low voltage side circuit 3 during the time (0 to t1) is
E1 = (1/2) · V1 · I0 · t1
Accordingly, the average power P1 during this period is as follows.
P1 = (1/2) · V1 · I0

The gate control circuit 4 calculates and controls the values of the times t0 and t1 so that the average power P1 coincides with the transfer power command value Pr. Therefore,
Pr = (1/2) · V1 · I0 (4) Equation (2) From the equations (2) and (4), the ON time t0 of the transistor Q2 is calculated as follows.
t0 = (2 · L / V1 ² ) · Pr (5) Formula The time t1 of one cycle of ON / OFF of the transistor Q1 is as follows from the formulas (3) and (5).
t1 = (V2 / (V2-V1)) · (2 · L / V1 ² ) · Pr (6)

  Therefore, if the gate control circuit 4 is controlled so that the transistor Q2 is repeatedly turned on for the time t0 calculated by the equation (5) with the period t1 calculated by the equation (6), the low voltage side circuit 3 is switched to the high voltage side. The average value P1 of the power transferred to the circuit 2 comes to coincide with the transfer power command value Pr designated from the outside.

  Here, a little problem is that the period t1 calculated by the equation (6) includes an error, and after the time t1 calculated by the equation (6) from the ON start time of the transistor Q2, the reactor current IL is reduced. This is a point where the value may not be zero. The calculation error is that the resistance when the transistor Q2 is ON is assumed to be zero, the forward voltage drop of the diode D1 is assumed to be zero, the voltage V1 of the low voltage side circuit 3 and the voltage V2 of the high voltage side circuit 2 are constant. It is caused by things that are not limited.

  Switching the transistor Q2 from OFF to ON when the reactor current IL is not zero is not preferable because switching loss increases. In order to cope with this problem, in the DC-DC converter 1 of FIG. 2, the reactor current IL is actually reduced to zero without switching the transistor Q2 from OFF to ON regardless of the cycle t1 calculated by the equation (6). A control method is employed in which the moment of occurrence (hereinafter referred to as “zero cross”) is detected and the switching timing is determined based on the detection signal (hereinafter referred to as “zero cross detection signal”).

  Zero-cross detection is performed by a zero-cross detection circuit 5. The detection may be performed by measuring the value of the reactor current IL and detecting that the absolute value thereof is less than or equal to the minute current value ΔI, but is detected when the potential difference between both ends of the reactor L is less than or equal to the minute voltage value ΔV. It is easier to do. If the transistor Q2 remains OFF even after the reactor current IL becomes zero, no current flows through the reactor L, and the potential difference between both ends of the reactor L becomes zero. Therefore, the moment of zero crossing can be detected by detecting that the potential difference between both ends of the reactor L has become a minute voltage value ΔV or less.

Based on the calculation formula as described above and the zero-cross detection signal sent from the zero-cross detection circuit 5, the gate control circuit 4 controls ON / OFF of the transistor Q2 as follows.
(A) The elapsed time t1 from the moment the transistor Q2 is turned on until the zero cross detection signal is received is equal to or greater than the predetermined value T1.
In this case, the gate control circuit 4 starts immediately after receiving the zero-crossing detection signal and turns on the transistor Q2 for the time t0 calculated by the equation (5).

(B) The elapsed time t1 from the moment the transistor Q2 is turned on until the zero cross detection signal is received is less than the predetermined value T1.
In this case, the gate control circuit 4 turns on the transistor Q2 for the time t0 calculated from the equation (5) starting from the time when the predetermined value T1 has elapsed since the moment the transistor Q2 was turned on. This is equivalent to performing PWM control in which the frequency is equal to the constant value 1 / T1.

  The waveform of the reactor current IL by the control method in the case of (A) is as shown in (1) of FIG. 1, and is the same as each waveform of FIG. 9 described in “Background Art”. When control is performed only by this control method, as described with reference to FIGS. 9 and 10, when the value of the transfer power command value Pr becomes small, the switching frequency of the transistor Q2 becomes high and the switching loss increases. Therefore, in the present embodiment, the control mode (B) is additionally provided in order to suppress an increase in the switching frequency.

  That is, if the time t1 until the zero cross detection signal is received is smaller than the predetermined value T1, the transistor Q2 is not turned on immediately after the zero cross detection signal is received, but is turned on after a predetermined value T1 time has elapsed. I try to let them. When the value of the transfer power command value Pr is reduced by this control, the waveform of the reactor current IL is the current with the cycle remaining at the predetermined value T1, as shown in (2) and (3) of FIG. The waveform becomes longer only during the zero period. The change in frequency with respect to the transfer power in this case is as shown in FIG. When the transfer power command value Pr is equal to or less than a predetermined value, the frequency becomes a constant value 1 / T1, and further increase in switching loss is prevented.

  Next, a processing flow in the gate control circuit 4 for performing the controls (A) and (B) will be described with reference to FIG. In the first step S1, a time t0 for turning on the transistor Q2 is calculated by the equation (5). In step S2, a clock timer T is provided to reset the clock value. In step S3, the transistor Q2 is turned on, and at the same time, the clocking timer T starts counting in step S4.

  In step S5, the timer T waits for the elapse of time t0 while checking whether or not the time t0 has elapsed. After the elapse of time t0, the process proceeds to step S6 and the transistor Q2 is turned off. In the subsequent step S7, it waits for a zero cross detection signal to be sent from the zero cross detection circuit 5. During the waiting time until the zero cross detection signal is received, the ON time t0 of the transistor Q2 of the next cycle is calculated by the equation (5) based on the latest transfer power command value Pr in step S8 and waits.

  When the zero cross detection signal is received, the process proceeds to step S9, and it is checked whether or not the time value T of the time timer T at that time is equal to or greater than the predetermined value T1 described in (A). If it is equal to or greater than the predetermined value T1, the process immediately returns to step S2 and enters the next cycle. The above is the processing flow for performing the above-described control mode (A).

  If the time measured value T of the time measuring timer T is less than the predetermined value T1 in step S9, the process proceeds to step S10. In step S10, the process waits for the time measured value T of the time measuring timer T to be equal to or greater than the predetermined value T1. While waiting, in step S11, the calculation of the ON time t0 of the transistor Q2 in the next cycle based on the latest transfer power command value Pr is repeated. When the measured time T becomes equal to or greater than the predetermined value T1, the process returns to step S2 and proceeds to the next cycle. The control when step S10 is executed is the control mode in the case of (B) described above.

(Second Embodiment)
This embodiment is an embodiment in which a control mode in which the switching frequency increases more gently than the control mode of (A) is added between the control modes of (A) and (B) in the first embodiment. Changes in the waveform of the reactor current IL with respect to the change in the transfer power command value Pr are shown in (1) to (4) of FIG.

  (1) in FIG. 6 is a waveform when the value of the transfer power command value Pr is large, and the same control as the control mode of (A) in the first embodiment is performed, and the waveform is the same as (1) in FIG. It is. (2) and (3) in FIG. 6 are cases where the value of the transfer power command value Pr decreases and the time until the zero cross detection signal is received becomes shorter than the first predetermined value T1. In this case, a time a · (T1−t1) obtained by multiplying the difference between the first predetermined value T1 and the time t1 from when the zero cross detection signal is received until the zero cross detection signal is received by a constant ratio a smaller than 1 Control is performed so that the next cycle starts after only elapses. Since the start of the next cycle is delayed by time a · (T1−t1), the rising slope of the switching frequency becomes slower than in the case of the control mode (A).

  (4) of FIG. 6 is a waveform when the time until the value of the transfer power command value Pr further decreases and the zero cross detection signal is received becomes less than the second predetermined value T2. In this case, a time a · () obtained by multiplying the difference between the first predetermined value T1 and the second predetermined value T2 by a constant ratio a smaller than 1 to the immediately preceding ON start time or the second predetermined value T2. Control is performed so that the next cycle is started immediately after the time (T2 + a · (T1−T2)) added with T1−T2). Accordingly, the switching frequency in this case is a constant value of 1 / (T2 + a · (T1−T2)), and PWM control is performed at this frequency. The change in frequency with respect to the change in transfer power is as shown in FIG.

In summary, the gate control circuit 4 controls ON / OFF of the transistor Q2 as follows.
(A) The elapsed time t1 from when the transistor Q2 is turned on until the zero cross detection signal is received is equal to or longer than the first predetermined value T1.
In the same manner as the control mode in the case of (A) in the first embodiment, the gate control circuit 4 starts immediately after receiving the zero-cross detection signal, and turns on the transistor Q2 for the time t0 calculated by the equation (5). .

(B) The elapsed time t1 from the moment the transistor Q2 is turned on until the zero cross detection signal is received is less than the first predetermined value T1 and greater than or equal to the second predetermined value T2.
Immediately after elapse of time a · (T1−t1) obtained by multiplying the difference between the first predetermined value T1 and the time t1 from when the zero cross detection signal is received to the time t1 until the zero cross detection signal is received by a constant ratio a smaller than 1 The transistor Q2 is turned on for the time t0 calculated from the equation (5).

(C) The elapsed time t1 from when the transistor Q2 is turned on until the zero cross detection signal is received is less than the second predetermined value T2.
The time a · (T1−T2) obtained by multiplying the difference between the first predetermined value T1 and the second predetermined value T2 by a constant ratio a smaller than 1 is added to the second predetermined value T2 from the immediately preceding ON start time. The transistor Q2 is turned on only for the time t0 calculated by the equation (5) starting immediately after the elapsed time (T2 + a · (T1-T2)). The switching frequency is a constant value of 1 / (T2 + a · (T1−T2)).

  The change of the switching frequency in the present embodiment is as shown in FIG. 7, and the increase of the switching frequency with respect to the decrease of the transfer power command value Pr is suppressed, and the maximum frequency is limited to 1 / (T2 + a · (T1−T2)). . Therefore, an effect of preventing an increase in switching loss can be obtained.

  Next, a processing flow in the gate control circuit 4 for controlling the above (A), (B), and (C) will be described with reference to FIG. The processing flow from step S1 to step S9 is a processing flow for implementing the control mode (A), and is the same as the processing flow from step S1 to step S9 in the processing flow of FIG. 5 described in the first embodiment. Description is omitted.

  In step S10, it is checked whether or not the time count T of the time count timer T at that time is equal to or greater than the second predetermined value T2 described in (A). If YES is determined, the process proceeds to step S11, waits for the measured value T to reach time (t1 + a · (T1−t1)), returns to step S2, and enters the next cycle. While waiting for that time, the calculation of the ON time t0 of the transistor Q2 in the next cycle is repeated based on the latest transfer power command value Pr in step S12. The case where steps S11 and S12 are executed corresponds to the control mode (B).

  If it is determined in step S10 that the time count T of the time count timer T at that time is less than the second predetermined value T2, the step waits until the time count T reaches time (T2 + a · (T1−T2)). Return to S2 and enter the next cycle. While waiting for that time, the calculation of the ON time t0 of the transistor Q2 in the next cycle is repeated based on the latest transfer power command value Pr in step S14. The case where steps S13 and S14 are executed corresponds to the control mode (C).

(Modified embodiment)
In the first and second embodiments, the zero-cross detection circuit 5 detects the moment when the reactor current IL becomes zero, and uses the zero-cross detection signal for control. However, as described in the first embodiment, the value of the time t1 until the reactor current IL becomes zero can be calculated by the equation (6) based on the value of the transfer power command value Pr. The value of the time t1 until the zero cross calculated by the equation (6) may include a slight calculation error as described above. However, if a slight increase in switching loss is tolerated, the zero cross detection is performed. Control may be performed using the time t1 calculated by the equation (6) instead of the reception timing of the zero-cross detection signal detected by the circuit 5. In this way, the zero cross detection circuit 5 can be eliminated and the circuit can be simplified.

  When priority is given to switching with the reactor current IL being zero, the time (t1 + Δt) obtained by adding a minute time Δt slightly larger than the estimated calculation error to the time t1 calculated by the equation (6) ( Control may be performed using the time t1 obtained by the equation 6) instead of the time t1. Instead of adding the minute time Δt in this way, a time (t1 · (1 + ΔR)) obtained by multiplying the time t1 calculated by the equation (6) by a numerical value (1 + ΔR) slightly larger than 1 is used instead of the time t1. And may be controlled. By controlling in this way, switching from OFF to ON of the transistor Q2 can be performed in a state of zero current.

It is a reactor current waveform in 1st Embodiment. This is a basic circuit configuration of a DC-DC converter. It is a figure which shows the relationship between the operation | movement of the transistor Q2, and the reactor current waveform in the case of boosting. It is a related figure of transfer electric power and frequency in a 1st embodiment. It is a control flow of the gate control circuit in the first embodiment. It is a reactor current waveform in 2nd Embodiment. It is a related figure of transfer electric power and frequency in a 2nd embodiment. It is a control flow of the gate control circuit in 2nd Embodiment. It is a reactor current waveform in the case of being based on a prior art. It is a related figure of the transfer electric power and frequency in the case of a prior art.

Explanation of symbols

In the drawings, 1 is a DC-DC converter, 2 is a high voltage side circuit, 3 is a low voltage side circuit, 4 is a gate control circuit, 5 is a zero cross detection circuit, D1 and D2 are diodes, GND is grounded, L is a reactor, N1, N2 is an input / output terminal, N3 is an interconnection point, Pr is a transfer power command value, Q1 is a first transistor, and Q2 is a second transistor.

Claims (3)

A step-up / step-down DC-DC converter (1) for transferring electric power between two circuits having different voltages from a low voltage side to a high voltage side or vice versa by an external selection signal. First and second transistors (Q1, Q2) connected in series with anti-parallel diodes (D1, D2), respectively, between the output terminal (N2) and the ground;
A reactor (L) connected between the interconnection point (N3) of the two transistors and the input / output terminal (N1) of the low-voltage side circuit (3);
A zero cross detection circuit (5) for detecting the moment when the current flowing through the reactor becomes zero;
A gate control circuit (4) for controlling the switching operation of the first and second transistors,
When the gate control circuit transfers power from the low-voltage side circuit to the high-voltage side circuit, the second transistor connected to the ground side with the first transistor connected to the high-voltage side circuit side turned off. When the power is transferred from the high voltage side circuit to the low voltage side circuit by controlling the ON / OFF of the transistor, the ON / OFF of the first transistor is controlled with the second transistor turned off. The ON time during which the first or second transistor is turned on is calculated according to the transfer power command value instructed from, and the zero-cross detection signal is received from the zero-cross detection circuit after the first or second transistor is turned on. If the time until the time is equal to or greater than the predetermined value, the first or second transistor is turned on for the ON time immediately after the zero cross detection signal is received. If the time until the zero cross detection signal is received is less than the predetermined value, the first or second transistor is turned on for the ON time immediately after the predetermined time has elapsed from the immediately preceding ON start time. A DC-DC converter characterized by being turned on.   2. The DC-DC converter according to claim 1, wherein, when the gate control circuit transfers power from the low-voltage side circuit to the high-voltage side circuit, the second transistor remains off while the first transistor is turned off. When the power is transferred from the high voltage side circuit to the low voltage side circuit by controlling the ON / OFF of the transistor, the ON / OFF of the first transistor is controlled with the second transistor turned off. The ON time during which the first or second transistor is turned on is calculated according to the transfer power command value instructed from, and the time from when the first or second transistor is turned on until the zero cross detection signal is received is calculated as the first time. If it is equal to or greater than a predetermined value of 1, the first or second transistor is turned on for the ON time immediately after receiving the zero-cross detection signal, and the If the time until the cross detection signal is received is less than the first predetermined value and greater than or equal to the second predetermined value, the first predetermined value and the zero cross are further received from the time of reception of the zero cross detection signal. The time from when the first or second transistor is turned on for the ON time immediately after the time obtained by multiplying the difference from the time until the detection signal is received by a constant ratio smaller than 1 until the zero cross detection signal is received. Is less than the second predetermined value, a constant ratio smaller than 1 is set to the difference between the first predetermined value and the second predetermined value from the immediately preceding ON start time to the second predetermined value. A DC-DC converter characterized in that the first or second transistor is turned on for the ON time immediately after the time obtained by adding the multiplied time has elapsed. 3. The DC-DC converter according to claim 1, wherein the DC-DC converter is based on the transfer power command value instead of the time from when the first or second transistor is turned on until the zero-cross detection signal is received. A DC-DC converter characterized in that the time from the start of ON of the first or second transistor determined by calculation until the current flowing through the reactor becomes zero is used.

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