JP2005150970A - Data receiver, data transmitter, data transmitter/receiver, and data transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data receiver, a data transmitter, a data transmitter/receiver and a data transmission system capable of surely detecting a training header signal for differentiating a lock signal and a training signal being delivered in initialization processing. <P>SOLUTION: Since a training signal detecting section 58 makes a decision roughly whether the signal level of data is higher or lower than a threshold level and identifies the pattern of a training header signal even if training processing is not yet performed by a data transmitter 1, the training header signal can be detected surely even if the signal level of a received training header signal is varied because a margin is provided for the threshold level. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data reception device, a data transmission device, a data transmission / reception device, and a data transmission system, and more specifically, in a ring network in which a plurality of devices are connected in a ring shape, in one direction according to a predetermined protocol. The present invention relates to a data reception device, a data transmission device, a data transmission / reception device, and a data transmission system included in a system for transmitting data to the network.

  2. Description of the Related Art In recent years, when the Internet and image information such as car navigation and ITS (Intelligent Transport Systems) are transmitted in a space such as an automobile, large-capacity and high-speed communication is required. Communication systems for transmitting digital data such as digitized video and audio data, or computer data are being actively studied, and a network that transmits digital data even in spaces such as automobiles has been fully introduced. It is becoming. In this in-vehicle network, for example, a physical topology is a single ring topology, and a plurality of nodes are connected by a single ring topology to form a one-way ring LAN. Or aiming for an integrated connection to information terminal devices. As an information communication protocol used in the ring LAN, there is, for example, Media Oriented Systems Transport (hereinafter referred to as MOST). In this MOST, not only a communication protocol but also a method for constructing a distributed system is mentioned, and data of the MOST network is transmitted with a frame as a basic unit, and the frame is transmitted in one direction to each node one after another.

  By the way, in the case of a ring-type LAN provided in a car or the like, radiation noise may cause malfunction of other electronic devices mounted on the car or the like, and may be affected by radiation noise from other devices. There is also a need for accurate transmission. For this reason, in a conventional ring LAN using MOST, each node is connected by an optical fiber cable to improve noise resistance while preventing generation of electromagnetic waves. On the other hand, some telecommunications using inexpensive cables such as twisted pair wires and coaxial cables enable high-speed data transmission exceeding 20 Mbps while reducing noise and improving noise resistance ( For example, see Patent Document 1.)

  Here, a data transmission system in which each node as described above is connected by an inexpensive cable will be described with reference to the drawings. FIG. 19 is a block diagram showing a configuration of the data transmission system.

  In FIG. 19, the data transmission system includes data transmission apparatuses 100a to 100n and transmission paths 300a to 300n. The data transmission device 100a is set as a clock-synchronized master, and the other data transmission devices 100b to 100n are set as slaves. The data transmission devices 100a to 100n are connected in a ring shape by transmission lines 300a to 300n. Between each of the data transmission devices 100a to 100n, data is transmitted in the direction of the arrow according to the MOST communication protocol.

  Here, in the data transmission system described above, data transmission is usually performed using so-called eight-value mapped digital data. The data transmission by the 8-value mapped digital data is a method of data transmission by assigning signal levels to 8 stages in multi-value transmission in which data of 1 bit or more is assigned to a signal level as one data symbol. (For details, see Patent Document 2). On the other hand, in addition to data transmission using 8-value mapped data, a data transmission method such as data transmission using 4-value mapping or 5-value mapped data is also assumed. With the advent of such various types of data transmission systems, a data transmission system that switches the data transmission system in accordance with the usage situation is required.

  Such switching of the data transmission method is generally performed based on a sequence as shown in FIGS. Hereinafter, the switching of the data transmission method will be described in detail with reference to FIG. 20 and FIG.

  In FIG. 20, the data transmission device 100a, which is a master, generates a lock signal for clock synchronization with other data transmission devices, and transmits the lock signal to the data transmission device 100b. The data transmission device 100b that has received the lock signal reproduces the acquired lock signal and establishes clock synchronization with the data transmission device 100a. Next, the data transmission device 100b generates a lock signal and transmits it to the data transmission device 100c. Thereafter, the data transmission devices 100c to 100n perform the same operation as the data transmission device 100b. Then, the lock signal transmitted from the data transmission device 100n reaches the data transmission device 100a, and the lock signal acquired by the data transmission device 100a that has received the lock signal is reproduced to establish clock synchronization with the data transmission device 100n. Thereby, clock synchronization is established between the data transmission apparatuses 100a to 100n.

  Next, the data transmission device 100a creates a training signal for setting a determination level serving as a reference for data determination, and transmits the training signal to the data transmission device 100b. The training signal transmitted here may be a training signal for 8-level mapping or a training signal for other methods, but here, a training signal for 8-level mapping is transmitted. Shall be.

  The data transmission apparatus 100b that has received the training signal sets a determination level that serves as a reference for data determination for 8-level mapping, using the acquired training signal. Then, the data transmission apparatus 100b creates a training signal for 8-level mapping and transmits it to the next data transmission apparatus 100c. Thereafter, the data transmission devices 100c to 100n perform the same operation as the data transmission device 100b. Then, the training signal transmitted from the data transmission device 100n reaches the data transmission device 100a, and the data transmission device 100a sets a determination level as a reference for data determination for 8-level mapping using the acquired training signal. . As a result, the data transmission apparatuses 100a to 100n in the data transmission system set a determination level that is a reference for data determination for 8-level mapping.

  In FIG. 21, the data transmission device 100a transmits to the data transmission device 100b an identification signal for notifying the other data transmission devices 100b to 100n whether data transmission is to be performed using 8-level mapping or other methods. To do. The data transmission device 100b that has received the identification signal determines which method is used for data transmission based on the received identification signal. Thereafter, the data transmission device 100b generates an identification signal based on the determination result and transmits the identification signal to the data transmission device 100c. Thereafter, the data transmission devices 100c to 100n perform the same operation as the data transmission device 100b. Then, the identification signal transmitted from the data transmission device 100n is received by the data transmission device 100a. Thereby, each data transmission apparatus 100a-100n in a data transmission system recognizes the transmission system of data.

Next, the data transmission apparatus 100a creates a training signal of the data transmission method recognized by each data transmission apparatus and transmits it to the data transmission apparatus 100b. Thereafter, each data transmission apparatus performs the same process as the above-described training process. Thereby, the determination level used as the reference | standard of the data determination of the data transmission system used for communication is set to each data transmission apparatus 100a-100n. Thereafter, data communication is started in the data transmission system.
International Publication No. 02/30079 Pamphlet International Publication No. 02/30077 Pamphlet

  As described above, in the conventional data transmission system, after the synchronization process using the lock signal, the first training process is performed, and the identification process for notifying the data transmission method using the determination level set by the training process. Is done. Data communication is started after the second training process is performed with the training signal for the data transmission method identified in the identification process. That is, the conventional data transmission system requires two training processes. This is because the conventional data transmission system cannot perform the identification process for identifying the data transmission method unless after the training process is performed.

  In order to avoid performing such training processing twice, it is conceivable to perform identification processing for notifying the data transmission method during the clock synchronization processing. For example, a data transmission method in which the data transmission apparatuses 100a to 100n perform data communication using the identification information by performing a clock synchronization process using a lock signal in which the identification information is embedded in advance before the first training process is performed. Can be considered. In this case, the first training process is performed with the training signal for the data transmission method indicated by the identification information, and the data communication in the data transmission system is started.

  For example, two types of patterns are considered as the lock signal in which the identification information is embedded. The first lock signal is a signal in which one cycle is composed of 8 symbols, and signal levels “+1” and “−1” are alternately repeated in each symbol. The second lock signal is composed of 8 symbols in one cycle, and the signal level “+1” and “−1” is alternately repeated for each symbol, and the fifth symbol is the signal level “+7” and 6 symbols. This is a signal whose eye has a signal level “−7”. If such two types of patterns of the lock signal can be distinguished by the data transmission device on the receiving side, the identification processing can be performed during the clock synchronization processing.

  FIG. 22 is an example of a transmission waveform of a lock signal, a training header signal, a training signal, and transmission data transmitted between the data transmission apparatuses 100a to 100n. In the transmission waveform shown in FIG. 22, a training header signal for distinguishing between a lock signal and a training signal is added. The training header signal is composed of three symbols, and is a signal in which the same signal level “+7” is continuous in order to distinguish it from other signals. The lock signal is the second lock signal described above.

  Generally, in order to cancel the overall signal level change (voltage change) when transmitting from the transmission side with respect to the transmission waveform, the received symbol value is determined by the difference value with respect to the previous symbol value. However, each data transmission apparatus is in a state in which the determination level is not set when distinguishing two types of patterns that the lock signal has. That is, each data transmission device cannot make a detailed determination of the data signal level. Therefore, each data transmission apparatus needs to distinguish between the first and second lock signals by roughly determining whether the data signal level is larger or smaller than the threshold value. Specifically, the difference value “14” between the signal levels “+7” and “−7” is roughly determined to be a large value, and the difference value “2” between the signal levels “+2” and “−2” is roughly determined to be a small value. It is necessary to set a threshold value that can be used to identify the pattern of the lock signal.

  However, in each data transmission device, it is necessary to distinguish between the lock signal and the training header signal when the determination level is not set. For example, in the case of the transmission waveform shown in FIG. 22, the difference value “2” between the signal levels “+2” and “−2” included in the lock signal and the difference value “0” between the continuous signal levels “+7” included in the training header signal. "Must be distinguished. In this case, a threshold value (for example, “1”) that can distinguish between the difference values “2” and “0” is set to identify the training header signal, and the threshold value for identifying the lock signal pattern described above is used. Margin is reduced. Here, when the data transmission environment is bad, such as the state of the transmission lines 300a to 300n provided between the data transmission devices 100a to 100n is bad, the signal level of the received training header signal may fluctuate. That is, since the difference value with respect to the training header signal fluctuates from “0”, the threshold value for distinguishing from the lock signal may be exceeded, and the training header signal may not be detected. In this case, since the data transmission apparatus cannot detect the training signal, the determination level cannot be set, and data communication between the data transmission apparatuses cannot be performed. In the above description, the example in which the identification information is embedded in the lock signal has been described. However, when using a lock signal having a section in which the adjacent symbols have a minimum difference value in the mapping method, the same problem occurs. Can occur.

  Therefore, an object of the present invention is to provide a data receiving device, a data transmitting device, a data transmitting / receiving device, and a data transmission capable of reliably detecting a training header signal for distinguishing between a lock signal and a training signal transmitted in an initialization process. Is to provide a system.

  In order to achieve the above object, the present invention employs the following configuration. Note that the reference numerals in parentheses, step numbers, and the like indicate correspondence with the embodiments described later in order to help understanding of the present invention, and do not limit the scope of the present invention.

  The data reception device (5) of the present invention is connected to another data transmission device (1) via a transmission line (80), and maps each symbol of transmission data to one of a plurality of signal levels (eight values). Then, the transmitted transmission signal is received. During the initial operation, the data receiving apparatus includes a training signal in which at least a plurality of signal levels of the transmission signal are formed in a known variation pattern and a header signal (training header signal) added to the head of the training signal. (S19, S59). The data receiving apparatus includes a difference calculating unit (54) that calculates a difference value (dd) between a signal level corresponding to a symbol in the received transmission signal and a signal level of the immediately preceding symbol with respect to the symbol in the order received, and a difference calculating unit A magnitude determination unit (581, 711) that distinguishes the absolute value of the difference value calculated by each using a large or small binary value with respect to a predetermined threshold, and a plurality of results (582) that the magnitude determination unit differentiates into binary values. A training signal detector (58) for detecting reception of the training signal or header signal by detecting (583) a match with at least a part (584) of the variation pattern of the training signal or header signal.

  As an example, in the training signal detection unit, the absolute value of the difference value with respect to at least a part of the numerical sequence (582) that is distinguished into two values by the magnitude determination unit and arranged in the order of reception and the variation pattern of the header signal is large. Alternatively, a predetermined number of header patterns (584) described in advance in small binary values are compared (583), and when both match, reception of the header signal is detected. The header signal variation pattern may be generated by alternately mapping a predetermined number of times to the maximum and minimum levels of a plurality of signal levels and then continuously mapping the same signal level a predetermined number of times (FIG. 4). ). In this case, the header pattern is described at least once after the large one of the binary values is described a predetermined number of times (FIG. 15B).

  As another example, when the fluctuation pattern of the header signal is alternately mapped to the maximum and minimum levels among a plurality of signal levels a predetermined number of times and then continuously mapped to the same signal level a predetermined number of times, The training signal detection unit detects reception of the header signal when the magnitude determination unit discriminates from binary to small after the magnitude determination unit discriminates at least a plurality of times from binary magnitude.

  During the initial operation, the header signal and the training signal are formed with a first variation pattern in which a plurality of signal levels are known, and a first lock signal including a clock component for establishing synchronization with another data transmission device May be transmitted continuously after being transmitted from another data transmission apparatus (S16, S57). In this case, the data reception device reproduces the clock component of the first lock signal and establishes synchronization with other data transmission devices, and a plurality of results determined by the magnitude determination unit as binary. And a lock signal identifying unit (71) for identifying the first lock signal by detecting coincidence with at least a part of the first variation pattern. Specifically, the first variation pattern has a minimum difference value among a plurality of signal levels and a mapping in which the positive and negative are alternately repeated for a predetermined number of times, and then the maximum and minimum levels among the plurality of signal levels. A pattern that is mapped once is generated repeatedly (FIG. 6). In this case, the variation pattern of the header signal is generated by alternately mapping the maximum and minimum levels among a plurality of signal levels a predetermined number of times and then continuously mapping the same signal level a predetermined number of times. Detects the reception of the header signal when the magnitude determination unit discriminates between binary values small after the magnitude determination unit distinguishes between binary values at least four times in succession.

  In addition, during the initial operation, the header signal and the training signal are formed with a first variation pattern in which a plurality of signal levels are known, and include a first clock component for establishing synchronization with other data transmission apparatuses. A second lock signal that is formed with a lock signal or a second variation pattern different from the first variation pattern and includes a clock component may be transmitted continuously after being transmitted from another data transmission apparatus. In this case, the data reception device reproduces the clock component of the first or second lock signal and establishes synchronization with other data transmission devices, and a plurality of results determined by the magnitude determination unit as binary values. And a lock signal identifying unit that identifies the first or second lock signal by detecting a match with at least a part of the first and second variation patterns. Specifically, the first variation pattern has a minimum difference value among a plurality of signal levels and a mapping in which the positive and negative are alternately repeated for a predetermined number of times, and then the maximum and minimum levels among the plurality of signal levels. The pattern that is mapped once is generated repeatedly (FIG. 6), and the second variation pattern is generated by continuously generating a mapping in which the difference value is the minimum among the plurality of signal levels and the sign is alternated ( FIG. 5). In this case, the variation pattern of the header signal is generated by alternately mapping the maximum and minimum levels among a plurality of signal levels a predetermined number of times and then continuously mapping the same signal level a predetermined number of times. Detects the reception of the header signal when the magnitude determination unit discriminates between binary values small after the magnitude determination unit distinguishes between binary values at least four times in succession.

  In addition, using the training signal, a determination level setting unit (57) for setting each determination level for distinguishing and determining the difference values calculated by the difference calculation unit, and the difference value calculated by the difference calculation unit The difference value determination unit (54) that determines and distinguishes based on the determination level set by the determination level setting unit, and the determination result output by the difference value determination unit is reverse-mapped to transmit data transmitted as a transmission signal. An inverse mapping unit (55) for decoding symbols may be further provided. In addition, when the training signal is transmitted for a predetermined time from the transmission of the header signal (fixed length), the data reception device is set by the determination level setting unit in response to the training signal detection unit detecting reception of the header signal. A teacher signal generation unit (59) that outputs a teacher signal (MS) that specifies a determination level to be transmitted to the determination level setting unit, and a counter (585) that counts a predetermined time during which the training signal is transmitted. The determination level setting unit detects the end of the training signal based on the count by the counter (S22, S61), and sets the final determination level.

  For example, the transmission data is a signal having a data format defined by MOST (Media Oriented Systems Transport).

  The data transmission device (6) of the present invention is connected to another data transmission device via a transmission line, and transmits a transmission signal in which each symbol of transmission data is mapped to one of a plurality of signal levels. The data transmission device transmits a first lock signal that transmits a first lock signal in which a plurality of signal levels are formed in a known first variation pattern and includes a clock component for establishing synchronization with another data transmission device. Section (671), a header signal transmission section (673) for transmitting a header signal formed with a third variation pattern having a plurality of signal levels different from the first variation pattern, and a fourth signal with a plurality of known signal levels. A training signal transmission unit (674) for transmitting a training signal formed with a variation pattern, a transmission data signal transmission unit (61-66) for transmitting a transmission data signal to which transmission data is mapped, and a predetermined time during initial operation A control unit (676) that selects a first lock signal to be transmitted to another data transmission device based on a condition, and the first lock signal selected by the control unit as other data A transmission unit (675, 63 to 66) that sequentially transmits the header signal, the training signal, and the transmission data signal to the other data transmission device after transmitting to the transmission device. The signal levels are alternately mapped to the maximum and minimum levels a predetermined number of times, and then mapped to the same signal level a predetermined number of times.

  For example, in the first variation pattern, a mapping in which the difference value is minimum among a plurality of signal levels and the positive and negative are alternately repeated for a predetermined number of times and then mapped once to the maximum and minimum levels among the plurality of signal levels. The generated pattern is generated repeatedly.

  Further, a second lock signal transmission unit (672) may be provided that transmits a second lock signal including a clock component in which a plurality of signal levels are formed in a second variation pattern different from the first variation pattern. . In this case, the control unit selects one of the first and second lock signals to be transmitted to another data transmission apparatus based on a predetermined condition, and the transmission unit selects the first and second lock signals selected by the control unit. Is transmitted to the other data transmission apparatus, and then sequentially transmitted to the other data transmission apparatus in the order of the header signal, the training signal, and the transmission data signal. For example, in the first variation pattern, a mapping in which the difference value is minimum among a plurality of signal levels and the positive and negative are alternately repeated for a predetermined number of times and then mapped once to the maximum and minimum levels among the plurality of signal levels. The second variation pattern is generated by continuously generating a mapping in which the difference value between adjacent symbols among the plurality of signal levels is the smallest and the sign is alternated.

  The control unit may further control the timing at which the transmission unit switches each signal transmitted to another data transmission apparatus. In this case, when synchronization with another data transmission apparatus is established (S18), the control unit controls the transmission unit to transmit a header signal (S19). When the header signal and the training signal are each of a fixed length, the control unit transmits the header signal to another data transmission device (S19), and transmits a transmission data signal after a predetermined time has elapsed (S22) (S23). ) So that the transmitter is controlled.

  For example, the transmission data is a signal having a data format defined by MOST.

  The data transmitting / receiving apparatus (1) of the present invention is connected to other data transmission apparatuses in a ring shape via a transmission line, and transmits / receives a transmission signal in which each symbol of transmission data is mapped to one of a plurality of signal levels. At the time of initial operation, the data transmitting / receiving apparatus receives a test signal including a training signal in which at least a plurality of signal levels of the transmission signal are formed with known variation patterns and a header signal provided at the head of the training signal. A test signal transmission unit (67) for transmitting to the data transmission device, and a difference value between the signal level corresponding to the symbol in the transmission signal received from the other data transmission device and the signal level of the immediately preceding symbol with respect to the symbol A difference calculation unit that calculates in order, a magnitude determination unit that distinguishes the absolute value of the difference value calculated by the difference calculation unit by a large or small binary value with respect to a predetermined threshold value, and a plurality that the size determination unit differentiates into binary values By matching the results of the test and at least part of the variation pattern of the training signal or header signal. And a training signal detector for detecting the reception of a grayed signal or header signal.

  For example, the test signal transmission unit alternately maps the fluctuation pattern of the header signal to the maximum and minimum levels among a plurality of signal levels a predetermined number of times and then continuously maps the same signal level a predetermined number of times. In this case, the training signal detection unit detects reception of the header signal when the magnitude determination unit discriminates the binary value from small to binary after the magnitude determination unit distinguishes the binary value at least a plurality of times continuously.

  The test signal transmitter includes a header after transmitting a first lock signal having a plurality of signal levels formed in a known first variation pattern and including a clock component for establishing synchronization with another data transmission apparatus. The signal and the training signal may be transmitted continuously. In this case, the data transmission / reception device regenerates a transmission data signal transmission unit that transmits a transmission data signal in which transmission data is mapped to another data transmission device, and a clock component of the first lock signal received from the other data transmission device. The first lock signal is detected by detecting coincidence between the clock recovery unit that establishes synchronization with the data transmission device, the plurality of results that the magnitude determination unit distinguishes into binary, and at least a part of the first variation pattern Calculated by the lock signal identifying unit for identifying the difference, the determination level setting unit for setting the determination level for distinguishing and determining the difference value calculated by the difference calculating unit using the training signal, and the difference calculating unit, respectively. The difference value determination unit and the difference value determination unit output the difference values determined based on the determination levels set by the determination level setting unit. And an inverse mapping unit for decoding a symbol of the transmission data transmitted in the transmission signal by inverse mapping the constant results, further comprising.

  In addition, the test signal transmission unit includes a first lock signal having a plurality of signal levels formed in a known first variation pattern and including a clock component for establishing synchronization with another data transmission device, or a first variation. The header signal and the training signal may be transmitted continuously after transmitting the second lock signal formed with a second variation pattern different from the pattern and including the clock component. In this case, the data transmission / reception device includes a transmission data signal transmission unit that transmits a transmission data signal in which transmission data is mapped to another data transmission device, and a clock component of the first or second lock signal received from the other data transmission device. , And a synchronization between the plurality of results distinguished by the magnitude determination unit and at least a part of the first and second variation patterns are detected. Determination level setting for setting a determination level for distinguishing and determining the difference value calculated by the difference calculation unit using the lock signal identification unit for identifying the first or second lock signal and the training signal Difference values determined by the difference calculation unit and the difference calculation unit based on the determination level set by the determination level setting unit. And parts, and an inverse mapping unit for decoding a symbol of the transmission data difference value determination unit is transmitted in the transmission signal by inverse mapping the judgment result output, further comprising.

  As an example, when the master is a master that transmits a transmission signal synchronized with a reference clock held by the own device to another data transmission device, the test signal transmission unit establishes the first or second lock after the synchronization with the reference clock is established. The signal is transmitted to another data transmission device (S16), and after the clock recovery unit establishes synchronization with the other data transmission device (S18), the header signal and the training signal are transmitted (S19), and the transmission data signal is transmitted. The unit sets the determination level using the training signal received from the other data transmission apparatus (S20) by the determination level setting unit (S21), and then transmits the transmission data signal (S23).

  As another example, when another data transmission device is a clock synchronization master and the own device is a slave, the test signal transmission unit receives the first or second received from the other data transmission device by the clock reproduction unit (S52). After establishing synchronization with another data transmission device using the lock signal (S53), the same signal as the received first or second lock signal is selected (S55, S56) and transmitted (S57), and the training signal After the detection unit detects reception of the header signal from the other data transmission device (S58), the header signal and the training signal are transmitted (S59). The transmission data signal transmission unit has the determination level setting unit of the other data transmission device. After setting the determination level using the training signal received from (S60), the transmission data signal is transmitted (S62).

  In addition, the test signal transmission unit may transmit the training signal for a predetermined time from the transmission of the header signal. In this case, the data transmitting / receiving apparatus further includes a counter that counts a predetermined time during which the training signal is transmitted in response to the reception of the header signal by the training signal detection unit (S20, S58). The setting unit detects the end of the training signal received from another data transmission device based on the count by the counter (S22, S61), sets a final determination level, and the transmission data signal transmission unit determines the determination level. After the setting unit sets the final determination level, the transmission data signal is transmitted.

  For example, the transmission data is a signal having a data format defined by MOST.

  The data transmission system of the present invention includes a plurality of data transmission apparatuses connected in a ring shape via a transmission line, and each data transmission apparatus maps each symbol of transmission data to one of a plurality of signal levels. Send and receive transmission signals. At the time of each initial operation, the data transmission device receives a test signal including a training signal in which at least a plurality of signal levels of the transmission signal are formed in a known variation pattern and a header signal added to the head of the training signal. Calculates the difference between the test signal transmitter to be transmitted to another data transmission device, the signal level corresponding to the symbol in the transmission signal received from the other data transmission device, and the signal level of the immediately preceding symbol for that symbol in the order received. A difference calculation unit, a magnitude determination unit that distinguishes the absolute value of the difference value calculated by the difference calculation unit by a large or small binary value with respect to a predetermined threshold, and a plurality of results that the magnitude determination unit differentiates into binary values And training by detecting a match with at least part of the variation pattern of the training signal or header signal And a training signal detector for detecting the reception of a signal or header signal.

  The test signal transmission unit may map the header signal variation pattern alternately to the maximum and minimum levels of a plurality of signal levels a predetermined number of times and then continuously map the same signal level a predetermined number of times. Absent. In this case, the training signal detection unit detects reception of the header signal when the magnitude determination unit discriminates the binary value from small to binary after the magnitude determination unit distinguishes the binary value at least a plurality of times continuously.

  The test signal transmission unit transmits a first lock signal having a plurality of signal levels formed in a known first variation pattern and including a clock component for establishing synchronization with the data transmission apparatus, and then transmits a header signal. Alternatively, the training signal may be transmitted continuously. In this case, the data transmission device reproduces the clock component of the transmission data signal transmission unit that transmits the transmission data signal to which the transmission data is mapped to the other data transmission device, and the first lock signal received from the other data transmission device. The first lock is detected by detecting the coincidence between the clock recovery unit that establishes synchronization with the data transmission device, the plurality of results distinguished by the magnitude determination unit and the at least part of the first variation pattern A lock signal identifying unit that identifies a signal, a determination level setting unit that sets a determination level for distinguishing and determining a difference value calculated by the difference calculating unit using a training signal, and a difference calculating unit A difference value determination unit and a difference value determination unit are provided for distinguishing and determining the determined difference values based on the determination levels set by the determination level setting unit. And an inverse mapping unit determination result by reverse mapping to decode the symbols of the transmission data transmitted by a transmission signal which further comprises.

  As an example, a test signal transmitter of a data transmission device set as a master that sends a transmission signal synchronized with a held reference clock to another data transmission device among a plurality of data transmission devices is synchronized with the reference clock. After that, the first lock signal is transmitted to the other data transmission device, and after the clock recovery unit establishes synchronization with the other data transmission device, the header signal and the training signal are transmitted, and the data transmission set as the master is performed. The transmission data signal transmission unit of the device transmits the transmission data signal after the determination level setting unit sets the determination level using the training signal received from another data transmission device.

  As another example, among a plurality of data transmission devices, the test signal transmission unit of a data transmission device set as a slave with the other data transmission device as a master for clock synchronization is received by the clock recovery unit from the other data transmission device. After establishing synchronization with another data transmission device using the first lock signal, the same signal as the received first lock signal is selected and transmitted, and the training signal detection unit receives a header signal from the other data transmission device. After transmitting the header signal and the training signal, the transmission data signal transmission unit of the data transmission device set as the slave uses the training signal received from the other data transmission device by the determination level setting unit. After each determination level is set, a transmission data signal is transmitted.

  Further, the test signal transmission unit includes a first lock signal or a first fluctuation pattern including a clock component for establishing synchronization with the data transmission device, wherein a plurality of signal levels are formed with a known first fluctuation pattern. The header signal and the training signal may be transmitted continuously after transmitting the second lock signal formed with a different second variation pattern and including the clock component. In this case, the data transmission device includes a transmission data signal transmission unit that transmits a transmission data signal to which each transmission data is mapped to another data transmission device, and a clock of the first or second lock signal received from the other data transmission device. Detects a match between a clock recovery unit that reproduces components and establishes synchronization with the data transmission device, a plurality of results that the magnitude determination unit differentiates into binary, and at least a part of the first and second variation patterns A determination level for setting a determination level for distinguishing and determining the difference value calculated by the difference calculation unit by using the training signal and the lock signal identification unit for identifying the first or second lock signal The difference determined by the setting unit and the difference calculation unit based on the determination level set by the determination level setting unit. Value determination unit, and an inverse mapping unit for decoding a symbol of the transmission data difference value determination unit is transmitted to the determination result output by the reverse mapping to transmission signals, further comprising.

  As an example, a test signal transmitter of a data transmission device set as a master that sends a transmission signal synchronized with a held reference clock to another data transmission device among a plurality of data transmission devices is synchronized with the reference clock. After that, the first or second lock signal is transmitted to another data transmission device, and after the clock recovery unit establishes synchronization with the other data transmission device, the header signal and the training signal are transmitted and set to the master. The transmission data signal transmission unit of the data transmission device transmits the transmission data signal after the determination level setting unit sets the determination level using the training signal received from the other data transmission device.

  As another example, among a plurality of data transmission devices, the test signal transmission unit of a data transmission device set as a slave with the other data transmission device as a master for clock synchronization is received by the clock recovery unit from the other data transmission device. After establishing synchronization with the other data transmission device using the first or second lock signal, the same signal as the received first or second lock signal is selected and transmitted, and the training signal detection unit After detecting the reception of the header signal from the data transmission device, the header signal and the training signal are transmitted, and the transmission data signal transmission unit of the data transmission device set as the slave receives the determination level setting unit from the other data transmission device After the determination level is set using the training signal, the transmission data signal is transmitted.

  For example, the transmission data is a signal having a data format defined by MOST.

  According to the data receiving apparatus of the present invention, it is possible to reliably detect a header signal or a training signal for distinguishing between a lock signal and a training signal transmitted in an initial operation. This is because the header signal can be identified by a rough determination whether the absolute value of the difference value for each data signal level is larger or smaller than the threshold value even before the data reception device is in the training process, Even if the difference value with respect to the received header signal fluctuates, a margin can be formed with respect to the threshold value, so that the header signal can be reliably detected.

  In addition, the training signal detection unit compares the header pattern with a numerical sequence that is distinguished into two values by the magnitude determination unit and arranged in a predetermined order in order of reception, and detects the reception of the header signal when both match. By comprising, the effect mentioned above can be acquired easily.

  When the fluctuation pattern of the header signal is alternately mapped to the maximum and minimum levels among a plurality of signal levels a predetermined number of times and then continuously mapped to the same signal level a predetermined number of times, the training signal detection unit Detecting the reception of the header signal easily and reliably by detecting that the magnitude determination unit distinguishes the binary value small after the magnitude determination unit distinguishes the binary value at least a plurality of times continuously. Can do.

  When two types of lock signals are sent before the header signal, the header signal can be reliably detected while identifying the type of the lock signal.

  Furthermore, when the training signal is transmitted for a predetermined time from the transmission of the header signal, the final determination level can be determined according to the end of the training signal.

  According to the data transmitting apparatus of the present invention, it is possible to transmit a test signal that can reliably detect the header signal by the above-described data receiving apparatus.

  When the header signal is transmitted after synchronization with another data transmission apparatus is established, the training process can be started after the clock synchronization process with the other data transmission apparatus is completed. Furthermore, when each of the header signal and the training signal has a fixed length, the training process can be terminated by time control, and data communication can be started.

  According to the data transmitting / receiving apparatus and data transmission system of the present invention, the effects of the data receiving apparatus and the data transmitting apparatus described above can be obtained similarly.

  A data transmission system according to an embodiment of the present invention will be described with reference to FIG. The data transmission system includes a plurality of data transmission devices, and a transmission / reception unit including a transmission unit and a reception unit is configured in each of the data transmission devices. These are examples in which the data reception device, data transmission device, and data transmission / reception device of the present invention are used. When only the data reception device or data transmission device is configured, only the reception unit or transmission unit needs to be configured. FIG. 1 is a block diagram showing the configuration of the data transmission system.

  In FIG. 1, the data transmission system forms a unidirectional ring LAN by connecting a plurality of nodes in a ring topology with a physical topology as a ring topology. Hereinafter, as an example of the data transmission system, each node is configured by six stages of data transmission apparatuses 1a to 1f, connected in a ring shape by transmission lines 80a to 80f, respectively, and transmitted data is transmitted through the transmission lines 80a to 80f. A system that is transmitted in one direction through the network will be described. Each of the data transmission devices 1a to 1f performs processing based on the data transmitted through the data transmission system and outputs the result to the data transmission system (for example, an audio device, a navigation device, or an information terminal device). 10a to 10f are connected. In addition, as a form of general hardware, each data transmission apparatus 1a-1f and connection apparatus 10a-10f are comprised integrally.

  As an information communication protocol used in the data transmission system, for example, there is Media Oriented Systems Transport (hereinafter referred to as MOST). Data transmitted using the MOST as a communication protocol is transmitted using a frame as a basic unit, and the frames are transmitted in one direction between the data transmission apparatuses 1 one after another. That is, the data transmission device 1a outputs data to the data transmission device 1b via the transmission path 80a. Further, the data transmission device 1b outputs data to the data transmission device 1c via the transmission path 80b. The data transmission device 1c outputs data to the data transmission device 1d via the transmission path 80c. Further, the data transmission device 1d outputs data to the data transmission device 1e via the transmission path 80d. The data transmission device 1e outputs data to the data transmission device 1f via the transmission path 80e. Then, the data transmission device 1f outputs data to the data transmission device 1a via the transmission path 80f. Inexpensive cables such as twisted pair wires and coaxial cables are used for the transmission lines 80a to 80f, and the data transmission apparatuses 1 perform electrical communication with each other. Here, when the data transmission system is turned on, the data transmission device 1a is a master that transmits data using its own clock, and the other data transmission devices 1b to 1f have a frequency set to the clock generated by the master. Slave to lock.

  Next, the configuration of the data transmission device 1 will be described with reference to FIG. FIG. 2 is a functional block diagram showing the configuration of the data transmission apparatus 1. The plurality of data transmission apparatuses 1a to 1f described above have the same configuration, and are collectively referred to as the data transmission apparatus 1.

  In FIG. 2, the data transmission device 1 includes a controller 2, a microcomputer (MPU) 3, and a transmission / reception unit 4. Hereinafter, description will be given using MOST as an example of a communication protocol used in the data transmission system.

  The controller 2 is connected to a connection device 10 that performs processing based on data transmitted through the data transmission system and outputs the result to the data transmission system. Then, as one of the functions, the controller 2 converts the data from the connected device 10 into a protocol defined by MOST and outputs the digital data TX to the transmission / reception unit 4. The controller 2 receives the digital data RX output from the transmission / reception unit 4 and transmits the data to the connected device 10 connected thereto.

  The MPU 3 controls the controller 2, the transmission / reception unit 4, and the connection device 10 based on each transmission mode of the data transmission device 1. For example, the MPU 3 has a reset function of the data transmission device 1, transmission method control (switching of 8-value / 4-value mapping, etc.), power control (switching of energy saving mode), master / slave selection processing, scramble transmission function, etc. Control.

  The transmission / reception unit 4 is typically configured by an LSI, and includes a reception unit 5, a transmission unit 6, and a clock control unit 7. The receiving unit 5 receives an electrical signal from another data transmission apparatus 1 that is input from the transmission path 80, converts the electrical signal into a digital signal RX, and outputs the digital signal RX to the controller 2. The receiving unit 5 reproduces the clock component included in the electric signal and outputs it to the clock control unit 7. The transmission unit 6 converts the digital data TX output from the controller 2 into an electrical signal based on the clock of the clock control unit 7, and outputs it to the other data transmission device 1 via the transmission path 80.

  The clock control unit 7 controls the system clock of the data transmission device 1. For example, a clock used in the transmission / reception unit 4 is output based on a clock used in the preceding data transmission apparatus 1 reproduced by the reception unit 5 or a clock of the controller 2. Specifically, when the data transmission device 1 is a master, the clock control unit 7 outputs a clock reproduced by a transmission side PLL (Phase Locked Loop), and when it is a slave, the clock control unit 7 outputs a clock reproduced by the reception side PLL. Output.

  The transmission unit 6 includes a selector 61, an S / P (serial / parallel) conversion unit 62, a mapping unit 63, a roll-off filter 64, a DAC (digital / analog converter) 65, a differential driver 66, and a test signal generation unit 67. have. The transmission unit 6 converts the digital data TX output from the controller 2 into an analog electric signal having a signal level obtained by multilevel mapping (for example, 8-level mapping or 4-level mapping), and outputs the analog electrical signal to the transmission path 80. In order to make the description more specific, a case will be described in which the transmission unit 6 converts the digital data TX into an analog electric signal that is eight-value mapped and outputs it. Details of the analog electric signal will be described later.

  The selector 61 selects data (for example, digital data TX or digital data RX) to be transmitted from the transmission unit 6 based on the clock controlled by the clock control unit 7 and outputs the data to the S / P conversion unit 62.

  The S / P converter 62 converts the serial digital data output from the selector 61 into parallel data of every 2 bits in order to perform multi-value transmission. The mapping unit 63 maps the 2-bit parallel data converted by the S / P conversion unit 62 to any of the eight-valued symbols based on the system clock, and outputs it to the roll-off filter 64. In this mapping, in order to perform clock recovery in another data transmission apparatus 1 arranged on the receiving side, parallel data for each 2 bits is alternately assigned to the upper 4 symbols and the lower 4 symbols among the 8-level symbols. . Further, in order to exclude the influence of fluctuations and differences in DC components between transmission and reception, mapping is performed based on the difference from the previous value. The mapping unit 63 maps the test signal TS output from the test signal generation unit 67 to the roll-off filter 64 as it is or after mapping it to any of the eight-valued symbols based on the system clock. Whether the mapping unit 63 maps the test signal TS may be determined according to the test signal TS output from the test signal generation unit 67.

  As described above, in the 8-level mapping method, reception is possible regardless of the variation or difference in the DC component between the data transmission apparatuses 1, and therefore, based on the previous symbol value and the parallel data (transmission data) every 2 bits. Thus, the transmission symbol value is determined (mapped). The transmission symbol value is one of eight signal levels “+7”, “+5”, “+3”, “+1”, “−1”, “−3”, “−5”, and “−7”. It is prescribed to map to. For example, when the previous symbol value is “−1” and the transmission data “00” is mapped, the transmission symbol value is “+7”, and the difference value from the previous symbol value is “+8”. The transmission symbol value is mapped so that its polarity is alternated with respect to the polarity of the previous symbol value. Further, mapping is performed so that transmission data is uniquely determined with respect to a difference value from the previous symbol value.

  The roll-off filter 64 is a waveform shaping filter for suppressing band limitation and intersymbol interference of an electric signal to be transmitted. For example, the roll-off filter 64 is configured with an FIR filter.

  The DAC 65 converts the signal band-limited by the roll-off filter 64 into an analog signal. The differential driver 66 amplifies the intensity of the analog signal output from the DAC 65, converts it to a differential signal, and sends it to the transmission line 80. The differential driver 66 transmits an electrical signal to be sent to one side (plus side) conductor of the transmission path 80 with respect to a set of two conductors included in the transmission path 80, and a signal opposite in polarity to the electrical signal. Transmit to the other side (minus side) of the transmission line 80. As a result, the positive and negative electric signals are transmitted as one pair to the transmission line 80, so that the mutual electric signal cancels each other's electric signal changes, and the radiation noise from the transmission line 80 and Electric influence from the outside can be reduced.

  The test signal generator 67 generates a test signal TS in order to perform initialization in cooperation with another data transmission apparatus 1 during initialization processing such as when the power is turned on. The test signal TS includes a clock reproduction signal (hereinafter referred to as a lock signal) for establishing synchronization on the receiving side, a training header signal (for example, the maximum or minimum signal level is continued for a predetermined period), and the receiving side. The training signal for setting the determination level used as the reference | standard of data determination between the other data transmission apparatuses 1 arrange | positioned in FIG. The training signal is a known data pattern between the data transmission apparatuses 1 and includes all the transmission symbol values. The test signal TS generated by the test signal generator 67 is sent to the mapping unit 63. Details of the transmission waveform of the test signal TS will be described later.

  The reception unit 5 includes a clock recovery unit 50, a differential receiver 51, an ADC (analog / digital converter) 52, a roll-off filter 53, a difference calculation unit 54, an inverse mapping unit 55, and a P / S (parallel / serial) conversion unit. 56, a determination level setting unit 57, a training signal detection unit 58, a teacher signal generation unit 59, a pattern identification unit 71, and a determination unit 72.

  The differential receiver 51 converts the differential signal input from the transmission path 80 into a voltage signal and outputs the voltage signal to the ADC 52. As described above, the plus and minus electrical signals are transmitted as one pair with respect to a set of two conductors included in the transmission line 80, and the differential receiver 51 is connected to the plus and minus sides. Since the signal is judged from the difference between the two, it is effective against an external electrical influence. The ADC 52 converts the voltage signal output from the differential receiver 51 into a digital signal.

  The roll-off filter 53 is a waveform shaping FIR filter that removes noise from the digital signal output from the ADC 52. In combination with the above-described transmission-side roll-off filter 64, the roll-off filter 53 realizes a roll-off characteristic without intersymbol interference. . The difference calculator 54 calculates a difference value dd between the received symbol value output from the roll-off filter 53 and the previous symbol value based on the data symbol timing detected by the clock recovery unit 50 described later. Then, the difference calculation unit 54 performs data determination for each difference value dd based on the determination level set by the determination level setting unit 57, and outputs the determination value to the inverse mapping unit 55. In this way, by determining the received symbol value by the difference value dd with respect to the previous symbol value, it is possible to cancel the DC voltage difference between devices when transmitting from the transmission side to the data transmission device 1 on the reception side.

  Based on the data symbol timing detected by the clock recovery unit 50, the inverse mapping unit 55 decodes the data before mapping by the mapping unit 63 on the transmission side using the determination value. By the inverse mapping process in the inverse mapping unit 55, the determination value is converted into parallel data. The P / S conversion unit 56 converts the parallel data converted by the inverse mapping unit 55 into serial digital data RX and outputs the serial digital data RX to the controller 2.

  The clock recovery unit 50 recovers the clock of the transmission line by reproducing the clock component of the signal received from the transmission line 80 output from the ADC 52, and sets the data symbol timing that becomes the maximum or minimum point of the transmission waveform described above. To detect. The clock regenerated by the clock regenerating unit 50 is used as a clock for the entire receiving unit 5. The clock regenerated by the clock regenerating unit 50 is output to the clock control unit 7 and used as a reference clock input for the receiving PLL.

  The determination level setting unit 57 sets a determination level for determining a threshold value of the difference value dd for the difference value dd calculated by the difference calculation unit 54. The training signal detection unit 58 detects a training header signal included in the test signal TS transmitted from the other data transmission apparatus 1, and detects a training signal received subsequent to the training header signal. A detailed configuration of the training signal detection unit 58 will be described later. When the training signal detection unit 58 detects the training header signal, the teacher signal generation unit 59 has the same data pattern as the training signal received subsequent to the training header signal and is synchronized with the training signal MS Is output to the determination level setting unit 57. Then, the determination level setting unit 57 calculates the determination level based on the difference value dd calculated for the teacher signal MS and the training signal.

  The pattern identification unit 71 and the determination unit 72 pattern-identify information embedded in the lock signal transmitted from the data transmission apparatus connected in the previous stage, and determine the information based on the identification result. Specifically, the pattern identifying unit 71 identifies the pattern of the transmitted lock signal based on the combination of the magnitudes of the absolute values of the difference values. Then, the determination unit 72 determines whether the transmitted lock signal is the first lock signal or the second lock signal based on the identification result output from the pattern identification unit 71, and the determination result is generated as a test signal. To the unit 67. For example, the information embedded in the lock signal can notify the data transmission method (8-value / 4-value mapping).

  Next, an example of the structure of the test signal generator 67 and the transmission waveform of the test signal TS output from the data transmission device 1 will be described with reference to FIGS. FIG. 3 is a block diagram showing a configuration of the test signal generator 67, and FIGS. 4 to 10 are diagrams for explaining examples of transmission waveforms of the test signal TS.

  In FIG. 3, the test signal generator 67 includes a first lock signal generator 671, a second lock signal generator 672, a training header signal generator 673, a training signal generator 674, a selector 675, and a switching instruction unit 676. ing. The test signal generator 67 transmits data (data symbols) indicating respective signals in order to send the test signal TS composed of the lock signal, the training header signal, and the training signal shown in FIG. 4 to the subsequent data transmission apparatus. Is output to the mapping unit 63.

  First lock signal generator 671 outputs data for generating a first lock signal as shown in FIG. 5 to selector 675. FIG. 5 is a graph showing a transmission waveform of the first lock signal output from the data transmission apparatus 1. The first lock signal is a signal used when each data transmission device 1 establishes clock synchronization, and information notifying the data transmission method to each data transmission device 1 is embedded. For example, the first lock signal notifies the lower data transmission apparatus 1 that communication is performed using 8-value mapped data. The first lock signal is a signal in which one cycle is composed of 8 symbols, and signal levels “+1” and “−1” are alternately repeated in each symbol.

  Second lock signal generator 672 outputs data for generating a second lock signal as shown in FIG. 6 to selector 675. FIG. 6 is a graph showing a transmission waveform of the second lock signal output from the data transmission apparatus 1. Similar to the first lock signal, the second lock signal is also a signal used when each data transmission device 1 takes clock synchronization, and information for notifying the data transmission method to each data transmission device 1 is embedded. It is. For example, the second lock signal notifies the lower data transmission apparatus 1 that communication is performed using the four-value mapped data. The second lock signal is composed of 8 symbols in one cycle, and signal levels “+1” and “−1” are alternately repeated in each symbol, the 7th symbol is the signal level “+7”, and the 8th symbol is The signal has a signal level “−7”.

  The training header signal generator 673 outputs data for generating a training header signal as shown in FIG. 4 to the selector 675. The training header signal is a signal that is disposed between the lock signal and the training signal and is provided to distinguish both. The training header signal is composed of 12 symbols, and the signal levels “−7” and “+7” are alternately repeated in the 1st to 9th symbols, and the 10th to 12th symbols have the signal level “+7”. The signal becomes constant at.

  The training signal generator 674 outputs data for generating a training signal as shown in FIG. 7 to the selector 675. FIG. 7 is a graph showing the transmission waveform of the training signal output from the data transmission apparatus 1. The training signal is a signal for causing the data transmission apparatus 1 at the subsequent stage to set a determination level for quaternary mapping or to set a determination level for octet mapping. The training signal generation unit 674 creates a training signal for quaternary mapping or quaternary mapping in accordance with an instruction from the MPU 3 when the own device is a master, and determines when the own device is a slave. According to an instruction from the unit 72, a training signal for quaternary mapping or quaternary mapping is created. FIG. 7 shows a training signal for 8-level mapping. For example, the training signal is generated by performing S / P conversion on an M sequence (x17 + x3 + 1: initial value is 11000000000000) and performing 8-value mapping. The training signal is transmitted for 65536 symbols (216 symbols), and the transmitted training signal has a fixed length.

  The selector 675 selects any one of the first lock signal, the second lock signal, the training header signal, and the training signal according to the instruction from the switching instruction unit 676 and outputs the selected signal to the mapping unit 63. The order of selection when outputting the test signal TS is the order of the second lock signal, the training header signal, and the training signal. These are mapped without breaking the law of alternately mapping the upper and lower symbols without interruption. Is output to the unit 63. The switching instruction unit 676 determines the type of signal selected by the selector 675 in response to an instruction from the determination unit 72 or the MPU 3.

  With reference to FIGS. 8-10, the transmission waveform pattern output without a 2nd lock signal and a training header signal interrupting is demonstrated. The training header signal is transmitted after clock synchronization is established using the lock signal. Specifically, when the own device is the master, after the clock synchronization of the own node is established, the lock signal is switched to the training header signal and output to the subsequent data transmission device. Also, when the own device is a slave, in response to receiving and detecting the training header signal from the preceding data transmission device, the lock signal is switched to the training header signal and output to the subsequent data transmission device (each detailed operation) Will be described later). That is, the lock signal is not a fixed length, and in particular in the case of the second lock signal, a plurality of patterns are generated at the connection portion with the training header signal. Note that the connection portion between the training header signal and the training signal has a fixed pattern because both have a fixed length.

  For example, when the signal level up to the final symbol of the second lock signal is “+1” → “−1” → “+7”, the difference value up to the signal level “−7” of the start symbol of the training header signal is “2”. → "8" → "14" (the state of FIG. 8). When the signal level up to the final symbol of the second lock signal is “+7” → “−7” → “+1”, the difference value up to the signal level “−7” of the start symbol of the training header signal is “14”. → "8" → "8" (the state of FIG. 9). Further, when the signal level up to the final symbol of the second lock signal is “+1” → “−1” → “+1”, the difference value up to the signal level “−7” of the start symbol of the training header signal is “2”. → "2" → "8" (the state of FIG. 10).

  Next, the structure of the pattern identification unit 71 will be described with reference to FIGS. 11 is a block diagram showing the configuration of the pattern identification unit 71, and FIG. 12 is a diagram showing the difference value dd output from the difference calculation unit 54 and the data stored in the first ROM 714 and the second ROM 717. FIG. 13 is a diagram for explaining the operation of the shift register 712.

  In FIG. 11, the pattern identification unit 71 includes a size determination unit 711, a shift register 712, a first comparator 713, a first ROM 714, a first counter 715, a second comparator 716, a second ROM 717, and a second counter 718. Yes.

  As described above, the difference calculation unit 54 reads the symbol value of the digital signal output from the ADC 52 based on the clock reproduced by the clock reproduction unit 50, and the value of the read symbol and the value of the symbol read immediately before. And the difference value dd is output to the magnitude determination unit 711. More specifically, since the signal level “+1” and “−1” are alternately repeated for each symbol in the first lock signal shown in FIG. The difference value dd shown in a) is output. On the other hand, the second lock signal shown in FIG. 6 has signal levels “+1”, “−1”, “+1”, “−1”, “+7”, “−7”, “+1”, “−1”. Therefore, the difference calculation unit 54 outputs the difference value dd shown in FIG.

  The magnitude determination unit 711 determines whether or not the absolute value of the difference value dd output from the difference calculation unit 54 is greater than a predetermined threshold value. More specifically, for example, when the threshold value is 5 and the difference value dd shown in FIG. 12A is input, the magnitude determination unit 711 determines the absolute value of the input difference value dd. Data “S” indicating that the value is “smaller than the threshold” is output to the shift register 712. On the other hand, when the difference value dd shown in FIG. 12B is input, the magnitude determination unit 711 indicates that the difference value dd is “+2” and “−2” “is smaller than the threshold”. Data “S” is output to the shift register 712, and data “L” indicating that “the difference value dd is“ +8 ”and“ −14 ”is“ greater than the threshold ”is output to the shift register 712. Typically, the size determination unit 711 outputs data “0” in the case of data “S”, and outputs data “1” in the case of data “L”.

  The shift register 712 stores data of a predetermined number of bits, and every time 1 bit of new data is input from the size determination unit 711, the data is erased by 1 bit from the oldest (FIFO method) Update the data. More specifically, as shown in FIG. 13, in this embodiment, the shift register 712 can store 8-bit data. Then, as illustrated in FIGS. 13A to 13C, when a bit indicating data “S” is newly input, the shift register 712 indicates data “S” which is the oldest data. The bits are discarded, and the area storing other bits is sequentially advanced.

  FIG. 12C shows data stored in the first ROM 714. The first ROM 714 stores data for detecting that the lock signal received by the data transmission device 1 is the first lock signal. As shown in FIG. 12C, the first ROM 714 stores 8-bit data “S” in series.

  Each time 1-bit data is input to the shift register 712, the first comparator 713 determines whether the data stored in the shift register 712 matches the data stored in the first ROM 714. . If the two data match, the first comparator 713 outputs data “1” indicating that the data match to the first counter 715. On the other hand, if the two data do not match, the first comparator 713 outputs data “0” indicating that they do not match to the first counter 715.

  The first counter 715 counts the number of data “1” output from the first comparator 713, and when the count reaches a predetermined number (for example, 16), outputs the fact to the determination unit 72.

  FIG. 12D shows data stored in the second ROM 717. The second ROM 717 stores data for detecting that the lock signal received by the data transmission device 1 is the second lock signal. As shown in FIG. 12D, the second ROM 717 stores 8-bit data, the fifth and seventh data “X”, the sixth data “L”, and the other data “S”. Note that the data “X” indicates that the data in the shift register 712 for determining a match may be “S” or “L”. This is because, as shown in FIG. 12B, the absolute value of the difference value before and after the difference value “−14” is “8”, and the data “L” or “S” depends on the setting of the threshold value. This value can change fluidly. When the threshold value is set so that the absolute value “8” of such a difference value is always determined to one of the data “L” and “S”, the absolute value “2” or “ 14 "margin is reduced. Therefore, it is not appropriate to use the difference value “+8” for the size determination, and the data “X” is stored in the second ROM 717 to be excluded from the determination.

  Each time 1-bit data is input to the shift register 712, the second comparator 716 determines whether the data stored in the shift register 712 matches the data stored in the second ROM 717. . If the two data match, the second comparator 716 outputs data “1” indicating that the data match to the second counter 718. On the other hand, if the two data do not match, the second comparator 716 outputs data “0” indicating that they do not match to the second counter 718.

  The second counter 718 counts the number of data “1” output from the second comparator 716, and when the count reaches a predetermined number (for example, 16), outputs that fact to the determination unit 72.

  Based on the output result output from either the first counter 715 or the second counter 718, the determination unit 72 determines whether the lock signal transmitted from the previous data transmission device is the first lock signal or the second lock signal. Determine whether it is a lock signal. That is, the determination unit 72 determines a data transmission method (eight-value / four-value mapping) for performing communication based on information embedded in the lock signal.

  Here, the reason why the difference value dd shown in FIG. 12A or FIG. 12B is not input to the shift register 712 as it is will be described. In the data transmission system according to the present embodiment, data is input to the shift register 712 before the training signal is transmitted to each data transmission device 1. That is, in each data transmission apparatus 1, training processing is not performed, and the data determination level is not set. As a result, each data transmission device 1 cannot make a detailed determination of the data signal level. Therefore, the data transmission device 1 according to the present embodiment identifies the first lock signal and the second lock signal by roughly determining whether the absolute value of the difference value for each signal level is larger or smaller than the threshold value. Yes.

  Next, the structure of the training signal detector 58 will be described with reference to FIGS. 14 is a block diagram showing the configuration of the training signal detector 58, FIG. 15 is a diagram showing data output from the difference calculator 54 and data stored in the ROM 584, and FIG. FIG. 10 is a diagram for explaining the operation of a shift register 582.

  In FIG. 14, the training signal detection unit 58 includes a magnitude determination unit 581, a shift register 582, a comparator 583, a ROM 584, and a counter 585.

  As described above, the difference calculation unit 54 reads the symbol value of the digital signal output from the ADC 52 based on the clock reproduced by the clock reproduction unit 50, and the value of the read symbol and the value of the symbol read immediately before. And the difference value dd is output to the magnitude determination unit 581. More specifically, since the signal level “+1” and “−1” are alternately repeated for each symbol in the first lock signal shown in FIG. Output the data shown in a). On the other hand, since the training header signal shown in FIG. 4 changes to signal levels “+7”, “−7”, “+7”, “−7”, “+7”, and “+7”, the difference calculation unit 54 Outputs the data shown in FIG.

  Similar to the size determination unit 711, the size determination unit 581 determines whether or not the absolute value of the difference value dd output from the difference calculation unit 54 is greater than a predetermined threshold value. More specifically, for example, when the threshold value is 5 and the data shown in FIG. 15A is input, the magnitude determination unit 581 determines that the difference value dd is “−14” and “+14”. The data “L” indicating “greater than the threshold” is output to the shift register 582 for the portion “”, and the data “L” indicating “below the threshold” for the portion where the absolute value of the difference value dd is “0”. Is output to the shift register 582. Typically, the size determination unit 581 outputs data “0” in the case of data “S”, and outputs data “1” in the case of data “L”.

  Like the shift register 712, the shift register 582 accumulates data of a predetermined number of bits, and erases data by one bit from the oldest one each time new data is input from the size determination unit 581. (FIFO method) to update internal data. More specifically, as shown in FIG. 16, in this embodiment, the shift register 582 can store 5-bit data. Then, as shown in FIGS. 16A to 16C, when a bit indicating data “L” or “S” is newly input, the shift register 582 receives the data “ The bit indicating “L” is discarded, and the area storing other bits is sequentially raised.

  FIG. 15B shows data stored in the ROM 584. The ROM 584 stores data for detecting that the signal received by the data transmission device 1 is a training header signal. As shown in FIG. 15B, the ROM 584 stores data of 5 bits, the data “S” is stored fifth, and the data “L” is stored in series.

  Each time 1-bit data is input to the shift register 582, the comparator 583 determines whether the data stored in the shift register 582 matches the data stored in the ROM 584. If the two data match, the comparator 583 outputs data “1” indicating that the data match to the counter 585, the teacher signal generation unit 59, and the MPU 3. On the other hand, when the two data do not match, the comparator 583 outputs data “0” indicating that they do not match to the counter 585 and the teacher signal generation unit 59.

  The counter 585 starts counting in response to the input of data “1” output from the comparator 583. The counter 585 detects the end of reception of the training signal having a fixed length by counting, and outputs the fact to the determination level setting unit 57 when reception of the training signal is completed. For example, the counter 585 detects the end of the training signal by counting 65536 symbols included in the training signal.

  Here, the reason why the difference value dd shown in FIG. 15A is not inputted as it is to the shift register 582 will be described. In the data transmission system according to the present embodiment, data is input to the shift register 582 before the training signal is transmitted to each data transmission device 1. That is, in each data transmission apparatus 1, training processing is not performed, and the data determination level is not set. As a result, each data transmission device 1 cannot make a detailed determination of the data signal level. Therefore, the data transmission apparatus 1 according to the present embodiment identifies the training header signal by roughly determining whether the absolute value of the difference value for each signal level is larger or smaller than the threshold value. That is, even if the difference value with respect to the received training header signal fluctuates from “0”, the training header signal can be reliably detected because there is a margin with respect to the threshold value.

  Further, the shift register 582 described above can store 5-bit data, and the reason will be described. In order to reliably detect the training header signal, it must be distinguished from the second lock signal. As shown in FIG. 12B, in the second lock signal, the difference value before and after the difference value “−14” is “+8”, and the absolute value “8” of the difference value is used for setting the threshold value. Accordingly, the value can be fluidly changed to data “L” or “S”. In other words, when the magnitude determination unit 581 determines the magnitude of the second lock signal, the data “S” may be input to the shift register 582 after the data “L” continues three times. Therefore, in order to reliably distinguish the training header signal and the second lock signal, it is only necessary to detect a pattern in which the data “S” is input to the shift register 582 after the data “L” continues at least four times. Therefore, the shift register 582 is only required to store at least 5-bit data, and may determine 6-bit or more data.

  Further, the training header signal may not be detected by the method described above. For example, a component that turns on a flag when the difference value dd output from the difference calculation unit 54 continues for a predetermined number of times (for example, four times) or more of an absolute value equal to or greater than a predetermined threshold, and less than the threshold when the flag is on. If a component that detects the absolute value of the difference value dd and detects the training header signal is provided, the same effect can be obtained.

  Then, in response to receiving data “1” from the comparator 583, the teacher signal generation unit 59 outputs the teacher signal MS synchronized with the training signal to the determination level setting unit 57. The determination level setting unit 57 receives the difference value dd calculated for the training signal by the difference calculation unit 54, and the determination level setting unit 57 uses the input difference value dd and the teacher signal MS to perform the above determination. Start level setting. Then, the determination level setting unit 57 ends the setting of the determination level when the counter 585 outputs that the reception of the training signal is completed.

  Next, an initialization operation until the data transmission system starts data communication will be described with reference to FIGS. 17 and 18. FIG. 17 and FIG. 18 are flowcharts showing initialization operations performed by the data transmission apparatus 1 set as a master and a slave in the data transmission system, respectively. As shown in FIG. 1, when the data transmission device 1a is a master and the other data transmission devices 1b to 1n are slaves and only the respective components are shown, a to n are assigned to the respective reference numerals. To distinguish. Moreover, when naming each component generically, it shall describe, without providing a to n to a reference code.

  In FIG. 17, the power of the data transmission system is turned on when all the data transmission devices 1a to 1n connected to the data transmission system are turned on (steps S11 and S51). In addition, about the process of said step S11 and S51, the process etc. which the reset state of the data transmission system was cancelled | released besides the power supply of the whole system may be sufficient.

  Next, the MPU 3a of the master data transmission device 1a determines a data transmission method for data communication in the data transmission system (step S12). Here, in order to make the description more specific, it is assumed that the MPU 3a determines one of 4-value mapping and 8-value mapping as the data transmission method. Next, the master data transmission device 1a determines whether or not the data transmission method determined in step S12 is quaternary mapping in its own MPU 3a (step S13). Then, the MPU 3a advances the process to the next step S14 when it is 8-value mapping, and advances the process to the next step S15 when it is quaternary mapping.

  In step S14, the master data transmission device 1a selects the first lock signal in which information indicating that communication using 8-value mapped data is started is embedded, and the process proceeds to the next step S16. Hereinafter, the operation performed in the data transmission device 1a in step S14 will be described in detail.

  When starting communication using 8-value mapped data, the MPU 3a notifies the switching instruction unit 676a of the test signal generation unit 67a to that effect. In response to this notification, the switching instruction unit 676a controls the selector 675a to output the first lock signal output from the first lock signal generation unit 671a. As a result, the test signal generator 67a selects the first lock signal.

  On the other hand, in step S15, the master data transmission device 1a selects the second lock signal in which information indicating that communication using four-value mapped data is started is embedded, and the process proceeds to the next step S16. Hereinafter, the operation performed in the data transmission device 1a in step S15 will be described in detail.

  When starting communication using 4-value mapped data, the MPU 3a notifies the switching instruction unit 676a of the test signal generation unit 67a to that effect. In response to this notification, the switching instruction unit 676a controls the selector 675a to output the second lock signal output from the second lock signal generation unit 672a. As a result, the test signal generator 67a selects the second lock signal.

  In step S16, the master data transmission device 1a establishes synchronization with the reference clock of its own device, and then transmits the lock signal selected in step S14 or S15 using the clock with which synchronization is established. Specifically, the lock signal output from the selector 675a is subjected to mapping processing by the mapping unit 63a, subjected to predetermined processing between the roll-off filter 64a and the differential driver 66a, and then sent to the subsequent data transmission device 1b. Is sent.

  On the other hand, the slave data transmission device 1b waits for the reception of the lock signal transmitted from the preceding data transmission device 1a after the process of step S51 (step S52). When the data transmission device 1b receives the lock signal transmitted from the master data transmission device 1a, the process proceeds to the next step S53.

  In step S53, the slave data transmission device 1b performs clock synchronization processing using the received lock signal. Next, the data transmission device 1b determines whether or not the received lock signal is the first lock signal (step S54). If the data transmission device 1b is the first lock signal, the process proceeds to the next step S55, and if it is not the first lock signal, the process proceeds to the next step S56. Hereinafter, processing performed in the slave data transmission apparatus 1b in steps S53 and S54 will be described in detail.

  The lock signal transmitted from the data transmission device 1a in the previous stage is subjected to predetermined processing by the differential receiver 51b and the ADC 52b of the data transmission device 1b, and is output to the clock recovery unit 50b and the roll-off filter 53b. The clock recovery unit 50 recovers a clock component included in the received lock signal. By establishing this clock as a reception clock used by the reception unit 5 and the clock control unit 7, the clock synchronization processing in step S53 is performed.

  On the other hand, the roll-off filter 53b performs a predetermined process and outputs a lock signal to the difference calculation unit 54b. The difference calculation unit 54b calculates a difference value dd between the symbols of the lock signal based on the clock reproduced by the clock reproduction unit 50b, and outputs the difference value dd to the pattern identification unit 71b and the training signal detection unit 58b. .

  The size determination unit 711b of the pattern identification unit 71b determines whether or not the absolute value of each difference value dd output from the difference calculation unit 54b is larger than the above-described threshold value, and outputs the determination result to the shift register 712b. To do. Specifically, when the threshold value is 5, the magnitude determination unit 711b outputs data “S” eight times as a determination result for the difference value dd illustrated in FIG. Further, the magnitude determination unit 711b outputs the data “S” four times as the determination result for the difference value dd shown in FIG. 12B, then outputs the data “L” three times, and then the data “S”. Output once. In response to these, one of the two types of determination results is output to the shift register 712b bit by bit.

  The first comparator 713b compares the data indicating the first lock signal stored in the first ROM 714b with the data stored in the shift register 712b every time one bit of data is input, and if they match, Data “1” is output to the first counter 715b. Similarly, the second comparator 716b compares the data indicating the second lock signal stored in the second ROM 717b with the data stored in the shift register 712b every time one bit of data is input, and they match. If so, the data “1” is output to the second counter 718b.

  The first counter 715b counts the number of data “1” output from the first comparator 713b. The second counter 718b counts the number of data “1” output from the second comparator 716b. Then, when the number of counted data “1” reaches a predetermined number, both counters notify the determination unit 72b to that effect.

  The determination unit 72b determines which counter has received the notification. Then, when the notification is received from the first counter 715b, the determination unit 72b determines that the first lock signal has been received, and recognizes that communication using 8-value mapped data is performed in the data transmission system. On the other hand, when the notification is received from the second counter 718b, the determination unit 72b determines that the second lock signal has been received, and recognizes that communication using 4-value mapped data is performed in the data transmission system. Then, the determination unit 72b notifies the recognition result to each component in the data transmission device 1b such as the test signal generation unit 67b and the MPU 3b. The same difference value dd is output to the training signal detection unit 58b. However, since the lock signal is not confused with the training header signal as described above, the training signal detection unit 58b receives the lock signal. Does not detect the training header signal.

  In step S55, the test signal generator 67b selects the first lock signal, and proceeds to the next step S57. In step S56, the test signal generator 67b selects the second lock signal, and advances the process to the next step S57. The processes performed in steps S55 and S56 are the same as steps S14 and S15 except that the instruction from the MPU 3a is changed to the notification from the determination unit 72b, and thus detailed description thereof is omitted.

  In step S57, the lock signal selected by the test signal generation unit 67b is output from the transmission / reception unit 4b of the data transmission device 1b to the subsequent data transmission device 1c. Also in the slave data transmission devices 1c to 1n, the processing of steps S52 to S57 described in the operation of the data transmission device 1b is similarly performed. Then, the data transmission device 1n outputs a lock signal to the master data transmission device 1a.

  The master data transmission device 1a waits for the reception of the lock signal transmitted from the preceding data transmission device 1n after the process of step S16 (step S17). When the data transmission device 1a receives the lock signal transmitted from the preceding data transmission device 1n, the clock synchronization process is performed using the received lock signal (step S18). Since the process in step S18 is the same as the process in step S53, detailed description thereof is omitted. The initialization operation so far completes the clock synchronization processing and the data transmission method notification in the data transmission system.

  In FIG. 18, the master data transmission device 1a outputs a training header signal and a training signal corresponding to the data transmission method determined in step S12 to the subsequent data transmission device 1b (step S19). Hereinafter, the operation performed in the data transmission device 1a in step S19 will be described in detail.

  After confirming the completion of the clock synchronization processing in step S18, the MPU 3a first performs processing for transmitting a training header signal from the data transmission device 1a. The MPU 3a notifies the switching instruction unit 676a of the test signal generation unit 67a that the training header signal is selected. In response to this notification, the switching instruction unit 676a controls the selector 675a to output the training header signal output from the training header signal generation unit 673a. Thereby, the test signal generator 67a selects a training header signal.

  Subsequently, the MPU 3a performs processing for transmitting a training header signal from the data transmission device 1a and performs processing for transmitting a training signal from the data transmission device 1a after a predetermined time has elapsed. As described above, since the training header signal has a fixed length (for example, 12 symbols), switching to the process of transmitting the training signal is automatically performed based on the passage of time. The MPU 3a notifies the switching instruction unit 676a of the test signal generation unit 67a that the training signal is selected. In response to this notification, the switching instruction unit 676a controls the selector 675a to output the training signal output from the training signal generation unit 674a. Thereby, the test signal generator 67a selects a training signal.

  The training header signal and the training signal output from the selector 675a are sequentially mapped by the mapping unit 63a, and subjected to predetermined processing between the roll-off filter 64a and the differential driver 66a, so that the data transmission device 1b at the subsequent stage is performed. Sent to.

  On the other hand, the slave data transmission device 1b waits for the reception of the training header signal transmitted from the preceding data transmission device 1a after the process of step S57 (step S58). When the data transmission apparatus 1b receives the training header signal transmitted from the master data transmission apparatus 1a, the process proceeds to the next step S59. Hereinafter, the process performed in the slave data transmission device 1b in step S58 will be described in detail.

  The training header signal transmitted from the preceding data transmission device 1a is subjected to predetermined processing by the differential receiver 51b, the ADC 52b, and the roll-off filter 53b of the data transmission device 1b, and is output to the difference calculation unit 54b. . The difference calculation unit 54b calculates a difference value dd between each symbol of the training header signal based on the established reception clock, and outputs the difference value dd to the pattern identification unit 71b and the training signal detection unit 58b.

  The magnitude determination unit 581b of the training signal detection unit 58b determines whether or not the absolute value of each difference value dd output from the difference calculation unit 54b is larger than the above-described threshold value, and the determination result is stored in the shift register 582b. Output. Specifically, when the threshold is 5, the magnitude determination unit 581b outputs the data “L” four times as the determination result for the difference value dd shown in FIG. Is output once. In response to this, one of the two types of determination results is output to the shift register 582b bit by bit.

  The comparator 583b compares the data indicating the training header signal stored in the ROM 584b with the data stored in the shift register 582b every time one bit of data is input. Is output to the teacher signal generator 59b, the counter 585b, the MPU 3b, and the like. Then, in response to receiving data “1” from the comparator 583b, the teacher signal generation unit 59b outputs the teacher signal MS synchronized with the training signal to the determination level setting unit 57b. On the other hand, the counter 585b starts counting in response to the input of the data “1” output from the comparator 583b. The same difference value dd is output to the pattern identification unit 71b. However, as described above, the training header signal is not confused with the lock signal, so the pattern identification unit 71b receives the training header signal. During this time, the first or second lock signal is not detected.

  In step S59, the data transmission device 1b outputs the training header signal and the training signal corresponding to the data transmission method notified in step S54 to the subsequent data transmission device 1c, and the process proceeds to the next step S60. The processing performed in step S59 is the same as that in step S19 except that it is performed in response to the input of data “1” output from the comparator 583b by the MPU 3b, and thus detailed description thereof is omitted. Also in the slave data transmission apparatuses 1c to 1n, the processing of the above-described steps S58 and S59 described in the operation of the data transmission apparatus 1b is performed in the same manner. Then, the data transmission device 1n outputs the training header signal and the training signal to the master data transmission device 1a.

  In step S60, the data transmission device 1b sets the determination level, and proceeds to the next step S61. Hereinafter, the operation performed in the data transmission device 1b in step S60 will be described in detail.

  In response to receiving data “1” from the comparator 583b, the teacher signal generation unit 59b outputs a teacher signal MS synchronized with the training signal to the determination level setting unit 57b. The determination level setting unit 57b receives the difference value dd calculated for the training signal by the difference calculation unit 54b, and the determination level setting unit 57b uses the input difference value dd and the teacher signal MS to perform the above determination. Start level setting.

  In step S61, the counter 585b of the data transmission device 1b determines whether or not the count started from the process of step S58 has reached a specified number. For example, the counter 585b detects the end of the training signal by setting the count number corresponding to 65536 symbols included in the training signal to the specified number. If the count of the counter 585b has not reached the specified number, the data transmission device 1b returns the process to step S60 and continues the determination level setting. On the other hand, when the count of the counter 585b reaches the specified number, the data transmission device 1b determines that the reception of the training signal transmitted from the previous data transmission device 1a is completed, and the process proceeds to the next step S62. . In the slave data transmission apparatuses 1c to 1n, the processes in steps S60 and S61 described in the operation of the data transmission apparatus 1b are similarly performed.

  On the other hand, the master data transmission device 1a waits for the reception of the training header signal transmitted from the previous data transmission device 1n after the process of step S19 (step S20). When the data transmission device 1a receives the training header signal transmitted from the data transmission device 1n, the process proceeds to the next step S21. Note that the processing in step S20 is the same as the processing in step S58, and thus detailed description thereof is omitted.

  In step S21, the data transmission device 1a sets the determination level and advances the process to the next step. Next, the counter 585a of the data transmission device 1a determines whether or not the count started from the process of step S20 has reached a specified number. If the count of the counter 585a has not reached the specified number, the data transmission device 1a returns the process to step S21 and continues the determination level setting. On the other hand, when the count of the counter 585a reaches the specified number, the data transmission device 1a determines that reception of the training signal transmitted from the previous data transmission device 1n is completed, and the process proceeds to the next step S23. . In addition, since the process of step S21 and S22 is the same as the process of said step S60 and S61, detailed description is abbreviate | omitted. By the initialization operation so far, the determination level setting process (training process) in the data transmission system is completed.

  Then, the above-described clock synchronization processing, data transmission method notification, and training processing are completed, data communication in the data transmission system is started (steps S23 and S62), and the initialization operation according to the flowchart is completed.

  In this way, it is possible to reliably detect a training header signal for distinguishing between a lock signal and a training signal transmitted in the initialization process. This is because even if the data transmission apparatus is before the training process, the training header signal can be identified by rough determination whether the absolute value of the difference value for each data signal level is larger or smaller than the threshold value. Even if the difference value with respect to the received training header signal fluctuates from “0”, the training header signal can be reliably detected because it has a margin with respect to the threshold value. In the above description, an example in which information is embedded in the lock signal has been described. However, in the mapping method, an interval between adjacent symbols has a minimum difference value (for example, a difference value “−2” or “+2”). Even when using a lock signal having, a training header signal can be reliably detected.

  Note that the training signal detection unit 58 and the pattern identification unit 71 may be configured with some components in common. For example, each of the magnitude determination units 581 and 711 performs the same operation in parallel in the initialization operation of the data transmission apparatus 1. Each shift register 582 and 712 has a different number of bits to be stored, but can be configured with the same number of bits. In this case, the same operation is performed in parallel in the initialization operation of the data transmission apparatus 1. It will be. Therefore, the training signal detection unit 58 and the pattern identification unit 71 can also be realized with a configuration in which the size determination unit and the shift register are common components. In this case, if three comparators for comparing the data stored in the common shift register and the data stored in each of the three ROMs are configured, the same operation as described above can be performed.

  Moreover, although the training signal detection part 58 showed the aspect which detects a training header signal in the description mentioned above, you may detect another signal with the structure of the test signal TS. For example, the training signal detection unit 58 may detect a part of the training signal.

  In the above description, the master data transmission device 1a determines whether or not the data transmission method determined in step S12 is quaternary mapping in the MPU 3a of the master device. If it is, the process proceeds to the next step S14, and if it is quaternary mapping, the process proceeds to the next step S15. Further, the slave data transmission device 1b performs clock synchronization processing using the received lock signal, determines whether or not the received lock signal is the first lock signal, and is the first lock signal, The process proceeds to the next step S55, and if it is not the first lock signal, the process proceeds to the next step S56. However, when the data transmission method is determined in advance, the step of making these determinations is not necessary. In this case, the test signal generator 67 shown in FIG. 3 may include only one of the first lock signal generator 671 and the second lock signal generator 672. In addition, the pattern identification unit 71 and the determination unit 72 shown in FIG. 2 also pattern-identify information embedded in the lock signal transmitted from the data transmission apparatus connected in the previous stage, and the information is based on the identification result. Needless to say, there is no need to have a function to determine

  The data reception device, data transmission device, data transmission / reception device, and data transmission according to the present invention are transmitted between the lock signal and the training signal in the initialization operation in which communication is performed using a multi-value electric signal or the like. It is useful as a device included in a system in which each device is connected by a transmission line in a ring type, etc., and a determination level is set to perform one-way telecommunications and the system, etc. It is.

The block diagram which shows the structure of the data transmission system which concerns on one Embodiment of this invention. Functional block diagram showing the configuration of the data transmission apparatus 1 of FIG. FIG. 2 is a block diagram showing the configuration of the test signal generator 67 of FIG. The figure for demonstrating the example of the transmission waveform of the test signal TS comprised by a lock signal, a training header signal, and a training signal The figure for demonstrating the example of the transmission waveform of a 1st lock signal The figure for demonstrating the example of the transmission waveform of a 2nd lock signal The figure for demonstrating the example of the transmission waveform of a training signal The figure which shows the 1st example of the transmission waveform pattern with which a 2nd lock signal and a training header signal are output without interruption. The figure which shows the 2nd example of the transmission waveform pattern with which a 2nd lock signal and a training header signal are output without a discontinuity. The figure which shows the 3rd example of the transmission waveform pattern output without a 2nd lock signal and a training header signal being interrupted. FIG. 2 is a block diagram showing the configuration of the pattern identification unit 71 in FIG. The figure which showed the difference value dd output from the difference calculation part 54 of FIG. 2, and the data stored in 1st ROM 714 and 2nd ROM 717 of FIG. The figure for demonstrating operation | movement of the shift register 712 of FIG. FIG. 2 is a block diagram showing the configuration of the training signal detector 58 in FIG. The figure which showed the difference value dd output from the difference calculation part 54 of FIG. 2, and the data stored in ROM584 of FIG. FIG. 14 is a diagram for explaining the operation of the shift register 582 in FIG. The flowchart which shows the initialization operation | movement of the first half which the data transmission apparatus 1 set as the master and the slave respectively performs in the data transmission system of FIG. The flowchart which shows the initialization operation | movement of the second half part which the data transmission apparatus 1 set to the master and the slave respectively sets in the data transmission system of FIG. Block diagram showing the configuration of a conventional data transmission system First half sequence diagram showing conventional data transmission method switching method The second half sequence diagram showing the conventional data transmission method switching method The figure which shows an example of the transmission waveform of the lock signal, training header signal, training signal, and transmission data transmitted between the data transmission apparatuses 100a-100n of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Data transmission apparatus 2 ... Controller 3 ... MPU
4. Transmission / reception unit 5 ... Reception unit 50 ... Clock recovery unit 51 ... Differential receiver 52 ... ADC
53 ... Roll-off filter 54 ... Difference calculation unit 55 ... Inverse mapping unit 56 ... P / S conversion unit 57 ... Determination level setting unit 58 ... Training signal detection units 581, 711 ... Size determination units 582, 712 ... Shift register 583 ... Comparison 584 ... ROM
585 ... Counter 59 ... Teacher signal generation unit 6 ... Transmission unit 61, 675 ... Selector 62 ... S / P conversion unit 63 ... Mapping unit 64 ... Roll-off filter 65 ... DAC
66 ... Differential driver 67 ... Test signal generator 671 ... First lock signal generator 672 ... Second lock signal generator 673 ... Training header signal generator 674 ... Training signal generator 676 ... Switching instruction unit 7 ... Clock controller 71 ... Pattern identification unit 713 ... First comparator 714 ... First ROM
715 ... first counter 716 ... second comparator 717 ... second ROM
718 ... second counter 72 ... determination unit 10 ... connected device 80 ... transmission path

Claims (37)

A data receiving device connected to another data transmission device via a transmission line, for receiving a transmission signal transmitted by mapping each symbol of transmission data to one of a plurality of signal levels,
At the time of initial operation, at least a plurality of signal levels of the transmission signal are each formed with a training signal formed with a known variation pattern and a header signal attached to the head of the training signal is transmitted from another data transmission device,
A difference calculation unit that calculates a difference value between a signal level corresponding to a symbol in the received transmission signal and a signal level of a symbol immediately preceding the symbol in the order of reception;
A magnitude determination unit that distinguishes the absolute value of the difference value calculated by the difference calculation unit by a binary value that is large or small with respect to a predetermined threshold value;
The reception of the training signal or the header signal is detected by detecting a match between the plurality of results distinguished by the magnitude determination unit and the at least part of the variation pattern of the training signal or the header signal. A data receiving apparatus comprising a training signal detection unit.   In the training signal detection unit, the absolute value of the difference value with respect to at least part of the variation pattern of the header signal and the numerical sequence that is distinguished into binary values by the magnitude determination unit and arranged in the order of reception, respectively, are large or small. 2. The data receiving apparatus according to claim 1, wherein the predetermined number of header patterns described above are compared with a predetermined number of header patterns and reception of the header signal is detected when both match. The variation pattern of the header signal is generated by alternately mapping the maximum and minimum levels among the plurality of signal levels a predetermined number of times and then continuously mapping the same signal level a predetermined number of times.
3. The data receiving apparatus according to claim 2, wherein the header pattern is described at least once after the large value of the two values is described continuously a predetermined number of times. The variation pattern of the header signal is generated by alternately mapping the maximum and minimum levels among the plurality of signal levels a predetermined number of times, and then continuously mapping the same signal level a predetermined number of times.
The training signal detection unit detects reception of the header signal when the magnitude determination unit discriminates between the binary values after the magnitude determination unit distinguishes the binary values at least several times continuously. The data receiving apparatus according to claim 1, wherein: During the initial operation, the header signal and the training signal are:
After the plurality of signal levels are formed with a known first variation pattern and a first lock signal including a clock component for establishing synchronization with another data transmission device is transmitted from the other data transmission device Sent continuously,
The data receiving device is:
A clock recovery unit for recovering a clock component of the first lock signal to establish synchronization with another data transmission device;
A lock signal identifying unit that identifies the first lock signal by detecting a match between the plurality of results determined by the magnitude determination unit as the binary value and at least a part of the first variation pattern; The data receiving apparatus according to claim 1, wherein: The first variation pattern has a minimum difference value of the plurality of signal levels and a mapping of alternating positive and negative values for a predetermined number of times. Generated by repeating the pattern that is mapped once,
The variation pattern of the header signal is generated by alternately mapping the maximum and minimum levels among the plurality of signal levels a predetermined number of times and then continuously mapping the same signal level a predetermined number of times.
The training signal detection unit detects reception of the header signal when the magnitude determination unit discriminates between the binary values after the magnitude determination unit distinguishes the binary values at least four times continuously. The data receiving device according to claim 5, wherein: During the initial operation, the header signal and the training signal are:
A first lock signal having a plurality of signal levels formed with a known first variation pattern and including a clock component for establishing synchronization with another data transmission device; or a second different from the first variation pattern A second lock signal formed in a variation pattern and including the clock component is continuously transmitted after being transmitted from another data transmission device;
The data receiving device is:
A clock recovery unit for recovering a clock component of the first or second lock signal to establish synchronization with another data transmission device;
Lock signal identification for identifying the first or second lock signal by detecting a match between the plurality of results distinguished by the magnitude determination unit into the binary and at least a part of the first and second variation patterns The data receiving apparatus according to claim 1, further comprising a unit. The first variation pattern has a minimum difference value of the plurality of signal levels and a mapping of alternating positive and negative values for a predetermined number of times. Generated by repeating the pattern that is mapped once,
The second variation pattern is generated by continuously generating a mapping in which the difference value is the smallest among the plurality of signal levels and the positive and negative are alternating,
The variation pattern of the header signal is generated by alternately mapping the maximum and minimum levels among the plurality of signal levels a predetermined number of times and then continuously mapping the same signal level a predetermined number of times.
The training signal detection unit detects reception of the header signal when the magnitude determination unit discriminates between the binary values after the magnitude determination unit distinguishes the binary values at least four times continuously. The data receiving apparatus according to claim 7, wherein: A determination level setting unit that sets a determination level for distinguishing and determining the difference value calculated by the difference calculation unit using the training signal;
A difference value determination unit that distinguishes and determines a difference value calculated by the difference calculation unit based on a determination level set by the determination level setting unit;
The data according to claim 1, further comprising: an inverse mapping unit that inversely maps a determination result output by the difference value determination unit and decodes a symbol of transmission data transmitted by the transmission signal. Receiver device. The training signal is transmitted for a predetermined time from the transmission of the header signal,
The data receiving device is:
A teacher signal generation unit that outputs a teacher signal that specifies a determination level set by the determination level setting unit to the determination level setting unit in response to the training signal detection unit detecting reception of the header signal;
A counter that counts a predetermined time during which the training signal is transmitted;
10. The data receiving apparatus according to claim 9, wherein the determination level setting unit detects the end of the training signal based on the count by the counter and sets the final determination level.   The data reception apparatus according to claim 1, wherein the transmission data is a signal having a data format defined by MOST (Media Oriented Systems Transport). A data transmission device that is connected to another data transmission device via a transmission path and transmits a transmission signal in which each symbol of transmission data is mapped to one of a plurality of signal levels,
A first lock signal sending unit for sending a first lock signal in which the plurality of signal levels are formed in a known first variation pattern and includes a clock component for establishing synchronization with another data transmission device;
A header signal sending section for sending a header signal formed by a third variation pattern in which the plurality of signal levels are different from the first variation pattern;
A training signal sending unit for sending a training signal formed with a fourth variation pattern in which the plurality of signal levels are known;
A transmission data signal sending unit for sending a transmission data signal in which the transmission data is mapped;
A controller that selects the first lock signal to be transmitted to another data transmission device based on a predetermined condition during an initial operation;
A transmission unit that transmits the first lock signal selected by the control unit to another data transmission apparatus, and then sequentially transmits the header signal, the training signal, and the transmission data signal to the other data transmission apparatus in this order. And
The third variation pattern is generated by alternately mapping a predetermined number of times to the maximum and minimum levels of the plurality of signal levels and then continuously mapping the same signal level a predetermined number of times. Data transmission device.   The first variation pattern has a minimum difference value of the plurality of signal levels and a mapping of alternating positive and negative values for a predetermined number of times. The data transmission apparatus according to claim 12, wherein the pattern is generated by repeating the pattern that is mapped once. And a second lock signal transmission unit configured to transmit a second lock signal including the clock component, wherein the plurality of signal levels are formed in a second variation pattern different from the first variation pattern,
The control unit selects one of the first and second lock signals to be transmitted to another data transmission device based on a predetermined condition,
The transmission unit transmits one of the first and second lock signals selected by the control unit to another data transmission device, and then sequentially transmits the header signal, the training signal, and the transmission data signal in this order. The data transmission device according to claim 12, wherein the data transmission device transmits to another data transmission device. The first variation pattern has a minimum difference value of the plurality of signal levels and a mapping of alternating positive and negative values for a predetermined number of times. Generated by repeating the pattern that is mapped once,
15. The second variation pattern is generated by continuously generating a mapping in which a difference value between adjacent symbols of the plurality of signal levels is minimum and the sign is alternated. The data transmission device described in 1. The control unit further controls timing of switching each signal transmitted by the transmission unit to another data transmission device,
The data transmission device according to claim 12 or 14, wherein the control unit controls the transmission unit to transmit the header signal when synchronization with another data transmission device is established. The header signal and the training signal are each of a fixed length,
The control unit according to claim 16, wherein the control unit controls the transmission unit to transmit the transmission data signal after a predetermined time has elapsed after transmitting the header signal to another data transmission apparatus. Data transmission device.   The data transmission apparatus according to claim 12, wherein the transmission data is a signal having a data format defined by MOST (Media Oriented Systems Transport). A data transmitter / receiver for transmitting / receiving a transmission signal connected to another data transmission device via a transmission line in a ring shape and mapping each symbol of transmission data to one of a plurality of signal levels,
In an initial operation, at least a plurality of signal levels of the transmission signal are formed with a known variation pattern, and a test signal including a header signal attached to the head of the training signal is transmitted to another data transmission device. A test signal transmitter for transmitting to
A difference calculating unit that calculates a difference value between a signal level corresponding to a symbol in the transmission signal received from another data transmission device and a signal level of a symbol immediately preceding the symbol in the order of reception;
A magnitude determination unit that distinguishes the absolute value of the difference value calculated by the difference calculation unit by a binary value that is large or small with respect to a predetermined threshold value;
The reception of the training signal or the header signal is detected by detecting a match between the plurality of results distinguished by the magnitude determination unit and the at least part of the variation pattern of the training signal or the header signal. A data transmission / reception device comprising a training signal detection unit. The test signal transmission unit alternately maps the fluctuation pattern of the header signal to the maximum and minimum levels of the plurality of signal levels a predetermined number of times and then continuously maps the same signal level a predetermined number of times to generate the header signal fluctuation pattern. ,
The training signal detection unit detects reception of the header signal when the magnitude determination unit discriminates between the binary values after the magnitude determination unit distinguishes the binary values at least several times continuously. The data transmitting / receiving apparatus according to claim 19, wherein: The test signal transmitter is
The header signal and the training signal are transmitted after transmitting a first lock signal in which the plurality of signal levels are formed with a known first variation pattern and includes a clock component for establishing synchronization with another data transmission apparatus. Are sent continuously,
The data transmission / reception device includes:
A transmission data signal transmitter for transmitting a transmission data signal mapping the transmission data to another data transmission device;
A clock recovery unit for recovering a clock component of the first lock signal received from another data transmission device and establishing synchronization with the data transmission device;
A lock signal identifying unit that identifies the first lock signal by detecting a match between the plurality of results distinguished by the magnitude determination unit into the binary and at least a part of the first variation pattern;
A determination level setting unit that sets a determination level for distinguishing and determining the difference value calculated by the difference calculation unit using the training signal;
A difference value determination unit that distinguishes and determines a difference value calculated by the difference calculation unit based on a determination level set by the determination level setting unit;
The data according to claim 19, further comprising: an inverse mapping unit that inversely maps a determination result output by the difference value determination unit and decodes a symbol of transmission data transmitted by the transmission signal. Transmitter / receiver. The test signal transmitter is
A first lock signal having a plurality of signal levels formed with a known first variation pattern and including a clock component for establishing synchronization with another data transmission device; or a second different from the first variation pattern After transmitting a second lock signal formed with a variation pattern and including the clock component, the header signal and the training signal are transmitted continuously,
The data transmission / reception device includes:
A transmission data signal transmitter for transmitting a transmission data signal mapping the transmission data to another data transmission device;
A clock recovery unit for recovering the clock component of the first or second lock signal received from another data transmission device and establishing synchronization with the data transmission device;
Lock signal identification for identifying the first or second lock signal by detecting a match between the plurality of results distinguished by the magnitude determination unit into the binary and at least a part of the first and second variation patterns And
A determination level setting unit that sets a determination level for distinguishing and determining the difference value calculated by the difference calculation unit using the training signal;
A difference value determination unit that distinguishes and determines a difference value calculated by the difference calculation unit based on a determination level set by the determination level setting unit;
The data according to claim 19, further comprising: an inverse mapping unit that inversely maps a determination result output by the difference value determination unit and decodes a symbol of transmission data transmitted by the transmission signal. Transmitter / receiver. When it is a master that sends the transmission signal synchronized with the reference clock held by its own device to another data transmission device,
The test signal transmitter is
After the synchronization with the reference clock is established, the first lock signal is transmitted to another data transmission device,
After the clock recovery unit establishes synchronization with another data transmission device, transmits the header signal and the training signal,
The transmission data signal transmission unit transmits the transmission data signal after the determination level setting unit sets the determination level using the training signal received from another data transmission device, respectively. The data transmitting / receiving apparatus according to claim 21. When it is a master that sends the transmission signal synchronized with the reference clock held by its own device to another data transmission device,
The test signal transmitter is
After synchronization with the reference clock is established, the first or second lock signal is transmitted to another data transmission device,
After the clock recovery unit establishes synchronization with another data transmission device, transmits the header signal and the training signal,
The transmission data signal transmission unit transmits the transmission data signal after the determination level setting unit sets the determination level using the training signal received from another data transmission device, respectively. The data transmitting / receiving apparatus according to claim 22. When another device is a slave with another data transmission device as the master for clock synchronization,
The test signal transmitter is
The clock recovery unit uses the first lock signal received from another data transmission device to establish synchronization with the other data transmission device, and then selects and transmits the same signal as the received first lock signal. ,
After the training signal detection unit detects reception of the header signal from another data transmission device, transmits the header signal and the training signal,
The transmission data signal transmission unit transmits the transmission data signal after the determination level setting unit sets the determination level using the training signal received from another data transmission device, respectively. The data transmitting / receiving apparatus according to claim 21. When another device is a slave with another data transmission device as the master for clock synchronization,
The test signal transmitter is
After the clock recovery unit establishes synchronization with another data transmission device using the first or second lock signal received from another data transmission device, the same signal as the received first or second lock signal Select to send,
After the training signal detection unit detects reception of the header signal from another data transmission device, transmits the header signal and the training signal,
The transmission data signal transmission unit transmits the transmission data signal after the determination level setting unit sets the determination level using the training signal received from another data transmission device, respectively. The data transmitting / receiving apparatus according to claim 22. The test signal transmission unit transmits the training signal for a predetermined time from transmission of the header signal,
The data transmission / reception device includes:
A counter that counts a predetermined time during which the training signal is transmitted in response to detection of reception of the header signal by the training signal detection unit;
The determination level setting unit detects the end of the training signal received from another data transmission device based on the count by the counter, and sets the final determination level;
The data transmission / reception apparatus according to claim 21 or 22, wherein the transmission data signal transmission unit transmits the transmission data signal after the determination level setting unit sets the final determination level.   The data transmission / reception apparatus according to claim 19, wherein the transmission data is a signal having a data format defined by MOST (Media Oriented Systems Transport). Data for transmitting and receiving a transmission signal including a plurality of data transmission devices connected in a ring shape via a transmission line, each data transmission device mapping each symbol of transmission data to one of a plurality of signal levels A transmission system,
In the initial operation, each of the data transmission devices includes a test signal including at least a training signal in which a plurality of signal levels of the transmission signal are formed in a known variation pattern and a header signal added to the head of the training signal. A test signal transmitter for transmitting a signal to another data transmission device;
A difference calculating unit that calculates a difference value between a signal level corresponding to a symbol in the transmission signal received from another data transmission device and a signal level of a symbol immediately preceding the symbol in the order of reception;
A magnitude determination unit that distinguishes the absolute value of the difference value calculated by the difference calculation unit by a binary value that is large or small with respect to a predetermined threshold value;
The reception of the training signal or the header signal is detected by detecting a match between the plurality of results distinguished by the magnitude determination unit and the at least part of the variation pattern of the training signal or the header signal. A data transmission system comprising a training signal detector. The test signal transmission unit alternately maps the fluctuation pattern of the header signal to the maximum and minimum levels of the plurality of signal levels a predetermined number of times and then continuously maps the same signal level a predetermined number of times to generate the header signal fluctuation pattern. ,
The training signal detection unit detects reception of the header signal when the magnitude determination unit discriminates between the binary values after the magnitude determination unit distinguishes the binary values at least several times continuously. 30. The data transmission system according to claim 29, wherein: The test signal transmitter is
After transmitting the first lock signal in which the plurality of signal levels are formed with a known first variation pattern and includes a clock component for establishing synchronization with the data transmission device, the header signal and the training signal are Send continuously,
Each of the data transmission devices includes a transmission data signal transmission unit that transmits a transmission data signal obtained by mapping the transmission data to another data transmission device,
A clock recovery unit for recovering a clock component of the first lock signal received from another data transmission device and establishing synchronization with the data transmission device;
A lock signal identifying unit that identifies the first lock signal by detecting a match between the plurality of results distinguished by the magnitude determination unit into the binary and at least a part of the first variation pattern;
A determination level setting unit that sets a determination level for distinguishing and determining the difference value calculated by the difference calculation unit using the training signal;
A difference value determination unit that distinguishes and determines a difference value calculated by the difference calculation unit based on a determination level set by the determination level setting unit;
30. The data according to claim 29, further comprising: an inverse mapping unit that inversely maps a determination result output by the difference value determination unit and decodes a symbol of transmission data transmitted by the transmission signal. Transmission system. Among the plurality of data transmission devices, the test signal transmission unit of the data transmission device set as a master that sends the transmission signal synchronized with a held reference clock to another data transmission device,
After the synchronization with the reference clock is established, the first lock signal is transmitted to another data transmission device,
After the clock recovery unit establishes synchronization with another data transmission device, transmits the header signal and the training signal,
The transmission data signal transmission unit of the data transmission device set as the master sets the determination level using the training signal received by the determination level setting unit from another data transmission device, and then transmits the transmission data. 32. The data transmission system according to claim 31, wherein a signal is transmitted. Among the plurality of data transmission devices, the test signal transmission unit of the data transmission device set as a slave with another data transmission device as a master for clock synchronization,
The clock recovery unit uses the first lock signal received from another data transmission device to establish synchronization with the other data transmission device, and then selects and transmits the same signal as the received first lock signal. ,
After the training signal detection unit detects reception of the header signal from another data transmission device, transmits the header signal and the training signal,
The transmission data signal transmission unit of the data transmission device set as the slave sets the determination level using the training signal received by the determination level setting unit from another data transmission device, and then transmits the transmission data. 32. The data transmission system according to claim 31, wherein a signal is transmitted. The test signal transmitter is
A first lock signal in which the plurality of signal levels are formed with a known first variation pattern and includes a clock component for establishing synchronization with the data transmission device, or a second variation different from the first variation pattern After transmitting the second lock signal formed in a pattern and including the clock component, continuously transmitting the header signal and the training signal,
Each of the data transmission devices includes a transmission data signal transmission unit that transmits a transmission data signal obtained by mapping the transmission data to another data transmission device,
A clock recovery unit for recovering the clock component of the first or second lock signal received from another data transmission device and establishing synchronization with the data transmission device;
Lock signal identification for identifying the first or second lock signal by detecting a match between the plurality of results distinguished by the magnitude determination unit into the binary and at least a part of the first and second variation patterns And
A determination level setting unit that sets a determination level for distinguishing and determining the difference value calculated by the difference calculation unit using the training signal;
A difference value determination unit that distinguishes and determines a difference value calculated by the difference calculation unit based on a determination level set by the determination level setting unit;
30. The data according to claim 29, further comprising: an inverse mapping unit that inversely maps a determination result output by the difference value determination unit and decodes a symbol of transmission data transmitted by the transmission signal. Transmission system. Among the plurality of data transmission devices, the test signal transmission unit of the data transmission device set as a master that sends the transmission signal synchronized with a held reference clock to another data transmission device,
After synchronization with the reference clock is established, the first or second lock signal is transmitted to another data transmission device,
After the clock recovery unit establishes synchronization with another data transmission device, transmits the header signal and the training signal,
The transmission data signal transmission unit of the data transmission device set as the master sets the determination level using the training signal received by the determination level setting unit from another data transmission device, and then transmits the transmission data. 35. The data transmission system according to claim 34, wherein a signal is transmitted. Among the plurality of data transmission devices, the test signal transmission unit of the data transmission device set as a slave with another data transmission device as a master for clock synchronization,
After the clock recovery unit establishes synchronization with another data transmission device using the first or second lock signal received from another data transmission device, the same signal as the received first or second lock signal Select to send,
After the training signal detection unit detects reception of the header signal from another data transmission device, transmits the header signal and the training signal,
The transmission data signal transmission unit of the data transmission device set as the slave sets the determination level using the training signal received by the determination level setting unit from another data transmission device, and then transmits the transmission data. 36. The data transmission system according to claim 35, wherein a signal is transmitted. 30. The data transmission system according to claim 29, wherein the transmission data is a signal having a data format defined by MOST (Media Oriented Systems Transport).

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