JP2005150856A - Sweep oscillation device, sweep oscillating method and sweep frequency control program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize high-speed sweep speed which cannot be conventionally obtained, and to supply a correct frequency sweep signal. <P>SOLUTION: A switch 4 is switched to an (a) side, and phase locking is applied to each of ten frequency points in total ranging from a sweep start frequency fmin to a sweep finish frequency fmax. Ten VCO control input voltages V<SB>CNT</SB>acquired for each of the frequency points are stored in a memory 12. Next, the switch 4 is to a (b) side, thereby separating a VCO 5 from a PLL. Then, adjacent two voltages are sequentially read from among the ten VCO control voltages V<SB>CNT</SB>stored in the memory 12, and linear interpolation operation is performed so that the predetermined number of points may come within between these two voltages. These interpolation point voltages are sequentially read from the memory 12 in an order of frequency, and the read voltages are supplied to the (b) terminal of the switch 4. A frequency signal corresponding to this voltage is outputted from the VCO 5. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a sweep oscillation apparatus, a sweep oscillation method, and a sweep frequency control program that generate a frequency within a predetermined sweep frequency range by applying a frequency control voltage to a voltage controlled oscillator.

  More specifically, the present invention relates to a sweep oscillation apparatus, a sweep oscillation method, and a sweep frequency control program for supplying a sweep frequency signal in a predetermined frequency range to an object to be measured.

  As is generally known, in a network analyzer as a measuring instrument, a predetermined frequency is measured with respect to an object to be measured (DUT: Device Under Test) in order to measure the frequency characteristics or impedance matching state of a component. A sweep oscillator that supplies a sweep frequency signal in a range with high speed and high resolution is essential.

  Although this network analyzer is expensive and large, it is an indispensable measuring instrument in the production line of mobile phones and GPS devices such as antennas and isolators. On the other hand, it is desired to further reduce the price of parts manufactured by a manufacturing line such as a mobile phone / GPS device. Therefore, it is not desirable to use an expensive and large network analyzer in a production line at present when cost competition is intense.

  Conventionally, there is a phase lock loop as a main circuit element of a sweep oscillation device used in a network analyzer or the like. In this phase lock loop, many methods are known for quickly establishing phase lock when a voltage controlled oscillator (VCO) is provided to obtain a desired oscillation frequency.

  As described in Japanese Patent Application Laid-Open No. 62-157426 (Patent Document 1), the first prior art “selects a vacant channel or the like in a synthesizer-type channel selection circuit constituted by a PLL circuit, for example. When a communication channel for scanning is scanned, a control signal having a pulse width corresponding to the scan width, that is, the frequency jump width is formed, and the PLL circuit lock-in time is changed by switching the characteristics of the PLL loop by this control signal. Is known to be faster.

  However, since this prior art is based on the premise that the frequency jump width changes, it is not suitable for a sweep oscillation device as a measuring instrument even if it can be applied to a synthesizer type tuning circuit.

  As described in FIG. 1 of Japanese Patent Application Laid-Open No. 2000-4155 (Patent Document 2), the second conventional technique includes two diodes D1 and D2 in parallel with the resistor 16 of the non-lag lead type loop filter 18. The capacitor 15 for integration is charged by the output current of the charge pump circuit 14, and the absolute value of the difference between the terminal voltage of the capacitor for integration 15 and the terminal voltage of the voltage holding capacitor 17 is connected to the diodes D1 and D2. When the forward voltage drop is reached, the diode D1 or D2 is turned on, and the voltage holding capacitor 17 is charged in a short time. With this circuit configuration, in a PLL device in which a current output type charge pump circuit is connected to the output side of the phase comparator and a non-lag lead type loop filter is connected to the output side of the charge pump circuit, The problem of “enabling high-speed lock-up” is solved.

  However, this prior art can only be used in a PLL device to which a non-lag-lead type loop filter is connected, and the shortening of the lock-up time is also shown in FIGS. There is a certain degree of improvement.

Japanese Patent Application Laid-Open No. Sho 62-157426 (right column on page 1, FIG. 1) Japanese Unexamined Patent Publication No. 2000-4155 (first page [summary], fourth page paragraph [0033], FIGS. 1, 4 and 5)

  As described above, the sweep oscillator for use in a network analyzer or the like cannot be improved only by using the above-described conventional technology.

  Therefore, a sweep oscillator using a PLL (phase lock loop) with a loop filter switching function as shown in FIG. 1 by combining the above-described conventional technique with a conventionally known general phase lock technique. Can be configured. In this circuit, first, the phase is locked at high speed by the loop filter 1 having a small time constant, and after the phase lock, the loop filter 2 having a large time constant is switched to stabilize the locking operation. According to this circuit, high-speed and accurate phase locking is possible. However, on the other hand, when trying to make the frequency step finer, the comparison frequency in the PD (phase comparator) has to be lowered, so that the lock-up time becomes longer and the loop is made to reduce the comparison frequency component after the phase lock. It is necessary to switch the filter. As a result, there arises a problem that the circuit scale is increased.

  Alternatively, it is possible to configure a sweep oscillator using a double-loop PLL as shown in FIG. 2 based on another general phase lock technique. This circuit is also called a feed forward type. First, it is pretuned to a lock point by a loop composed of a PD (phase comparator) 1, a loop filter 1, a VCO (voltage controlled oscillator) 1 and a BPF (band pass filter). Next, fine tuning is performed by a loop via PD2, loop filter 2 and VCO2. According to this circuit, the phase lock can be performed at a high speed and the frequency step can be set finely. However, on the other hand, two sets of PLLs are required, and a band-pass filter for preventing a so-called pseudo lock state in which the phase is not correct is required. As a result, the circuit scale becomes extremely large.

  The PLL has the advantage of being able to lock both the frequency and phase. However, if it is desired to change the lock frequency at high speed, the PLL frequency divider must be switched and locked, and the frequency resolution can be reduced. If it is desired to improve, it is necessary to lower the comparison frequency, so the cut-off frequency of the loop filter must also be lowered, which makes it more difficult to speed up the time required for phase locking. In addition, if the number of frequencies to be phase-locked is increased in order to increase the accuracy of the sweep frequency signal with respect to the object to be measured, the sweep time becomes longer, which is fatal to the production line.

  Accordingly, an object of the present invention is to realize a sweep oscillation apparatus capable of providing an unprecedented increase in sweep speed and supplying an accurate frequency sweep signal in spite of a simple circuit configuration in view of the above points. Another object is to provide a sweep oscillation method and a sweep frequency control program.

  In order to achieve the above object, according to a first aspect of the present invention, there is provided a sweep oscillator that generates a frequency within a predetermined sweep frequency range by applying a frequency control voltage to a voltage controlled oscillator. A phase lock is applied at a predetermined frequency point Fn (n is a positive integer from 1 to N) within the predetermined sweep frequency range, and the frequency control voltage Vn (n is a value of the voltage controlled oscillator at each frequency point). , A pre-sweep processing means for storing (a positive integer from 1 to N), and a phase lock stop means for stopping the operation of the phase locked loop including the voltage controlled oscillator and disconnecting the voltage controlled oscillator from the phase locked loop And an interpolation voltage for interpolating between two adjacent frequency control voltages among the frequency control voltages Vn stored by the sweep preprocessing means. A predetermined spot frequency sequentially from the voltage-controlled oscillator by applying the interpolation voltage to the voltage-controlled oscillator disconnected from the phase-locked loop by the operation of the calculating means for calculating the phase-locking means. And a sweep execution means to be generated.

  Here, in the sweep oscillation device, the calculation unit calculates an interpolation voltage for interpolating between two adjacent frequency control voltages among the frequency control voltages Vn stored by the sweep preprocessing unit. At this time, the storage data D1n related to the frequency control voltage Vn stored by the pre-sweep processing means is read again from the memory, the storage data D1n is converted into the analog signal A1n, and then the analog signal A1n is digitally converted and reconverted. The interpolation voltage can be calculated by forming data D2n and using the difference between the stored data D1n and the reconverted data D2n as the correction error data δ.

  In the sweep oscillation device, after the sweep mode within the predetermined sweep frequency range is executed by the sweep execution unit, the sweep preprocessing unit, the phase lock stop unit, and the calculation are performed again. The calibration mode may be executed by the means.

  According to a second aspect of the present invention, there is provided a sweep oscillation method for generating a frequency within a predetermined sweep frequency range by applying a frequency control voltage to the voltage controlled oscillator. A phase lock is applied at a predetermined frequency point Fn (n is a positive integer from 1 to N), and the frequency control voltage Vn (n is a positive integer from 1 to N) at each frequency point. ), A calculation step for calculating an interpolation voltage for interpolating between two adjacent frequency control voltages among the frequency control voltages Vn stored in the pre-sweep processing step, and a phase By applying the interpolation voltage to the voltage controlled oscillator disconnected from the lock loop, a predetermined spot frequency is set to the voltage controlled. And sweep executing step of sequentially generated from the oscillator is obtained by including a.

  Here, in the sweep oscillation method, the calculation step further includes a step of reading again the storage data D1n related to the frequency control voltage Vn stored in the pre-sweep processing step from the memory, and the storage data D1n. After converting to analog signal A1n, digitally converting analog signal A1n to form reconverted data D2n, and using the difference between stored data D1n and reconverted data D2n as correction error data δ , Correcting the frequency control voltage Vn stored in the pre-sweep processing step, and calculating an interpolation voltage for interpolating between two adjacent frequency control voltages.

  In the above sweep oscillation method, after the sweep mode within the predetermined sweep frequency range is executed by the sweep execution step, the calibration mode is again set by the pre-sweep processing step and the calculation step. It can be configured to be executed.

  The third aspect of the present invention is a sweep frequency control program that stores any of the above-described sweep oscillation methods in a form that can be read by the controller of the sweep oscillation apparatus.

  By implementing the present invention, the effects listed below can be obtained.

(1) Despite a simple circuit configuration, high-speed frequency sweep can be performed.
As a specific example, a frequency sweep of 1600 points can be executed in about 100 milliseconds. On the other hand, in the conventional sweep oscillator, when the frequency of 1200 points is swept, it takes about 250 milliseconds at the earliest, so it can be said that the speeding up according to the present invention is remarkable.

  (2) Moreover, since a necessary PLL may be a general PLL that has been conventionally known, it can be reduced in size at low cost.

  (3) Since the calibrated VCO control input voltage can be provided, the frequency resolution can be easily increased. That is, an accurate sweep frequency can be obtained at a high speed even though the phase lock is not performed during the frequency sweep.

Embodiment 1
FIG. 3 is a block diagram showing a sweep oscillation apparatus (sweep generator) to which the present invention is applied. In this figure, reference numeral 1 denotes a crystal oscillator that generates a reference frequency signal. 2 is a phase comparator (PD), 3 is a loop filter, 4 is a changeover switch, 5 is a voltage-controlled oscillator (VCO), and 6 is a 1 / N frequency divider, which form a normal PLL. Reference numeral 7 denotes an A / D converter, which receives the control input voltage _VCNT of the VCO 5 and stores it in the memory 12. A D / A converter 8 converts data stored in the memory 12 into an analog voltage. Reference numeral 9 denotes an amplifier (AMP). When the changeover switch 4 is tilted to the b terminal side, the output voltage of the amplifier 9 becomes the control input voltage _{VCNT of the} VCO 5. An I / O circuit 10 outputs a signal for controlling the changeover switch 4 and the 1 / N frequency divider 6. Reference numeral 11 denotes a CPU which performs R / W control for the memory 12, supply of a control signal to the I / O circuit 10, and other arithmetic processing.

  Next, the operation of this embodiment will be described with reference to the explanatory diagram shown in FIG.

First, the changeover switch 4 is moved to the a terminal side, and phase lock is applied to a total of ten frequency points f1 to f10 from the sweep start frequency fmin to the sweep end frequency fmax within the frequency sweep range. Ten VCO control input voltages V _{CNT (1) to} V _{CNT (10)} obtained for each of these ten frequency points f1 to f10 are stored in the memory 12 via the A / D converter 7.

Next, the VCO 5 is disconnected from the PLL by tilting the changeover switch 4 to the b terminal side. As a result, the VCO 5 can be operated independently regardless of the PLL operation. At the same time, the CPU 11 has two adjacent voltages among the _ten VCO control input voltages V _{CNT (1) to} V _{CNT (10)} stored in the memory 12, that is, V _{CNT (1)} and V _{CNT. (2) VCNT (2)} and _{VCNT (3) VCNT (3)} and _{VCNT (4) VCNT (4)} and _{VCNT (5) VCNT (5)} and _{VCNT (6 ) )} , _{VCNT (6)} and _{VCNT (7)} , _{VCNT (7)} and _{VCNT (8)} , _{VCNT (8)} and _{VCNT (9)} , _{VCNT (9)} and _{VCNT (10)} Data are read sequentially and linear interpolation (interpolation) is performed so that a predetermined number of points (for example, 40) is included between these two voltages. Since linear interpolation between two voltages is a well-known technique, description thereof is omitted here. The interpolation point voltage obtained in this way is stored in the memory 12.

Next, the CPU 11 reads out these interpolation point voltages and the above-described VCO control input voltages V _{CNT (1) to} V _{CNT (10)} in order of frequency from the memory 12, and through the D / A converter 8 and the amplifier 9, Supply to the b terminal of the changeover switch 4. At present, since the changeover switch 4 is tilted to the b terminal side, the analog voltage itself output from the amplifier 9 becomes the VCO control input voltage _VCNT , and a frequency signal corresponding to this voltage is output from the VCO 5. In other words, when the sweep frequency is generated, phase lock is not performed and the VCO 5 operates alone, so that high-speed frequency sweep is performed.

When one frequency sweep is completed, the changeover switch 4 is again moved to the a terminal side, and the ten VCO control input voltages V _{CNT (1) to} V _{CNT ( 10)} is stored. The same applies hereinafter.

In this way, by storing ₁₀ VCO control input voltages V _{CNT (1) to} V _{CNT (10)} every time one frequency sweep or every predetermined number of frequency sweeps, the temperature of the VCO 5 has. The influence of characteristics can be eliminated.

Embodiment 2
In the first embodiment described above, the description has been made on the assumption that the A / D converter 7, the D / A converter 8, and the amplifier 9 have no operation error. However, in reality, 10 VCO control inputs obtained for each of the frequency points f1 to f10 (see FIG. 4) described above due to gain errors, offset errors, or environmental changes inherent in various amplifiers. The voltages V _{CNT (1) to} V _{CNT (10)} are not necessarily accurately reproduced via the D / A converter 8 and the amplifier 9, and may include a certain error. In the second embodiment described here, a method for compensating for such an error will be described.

  FIG. 5 is a flowchart showing the operation of the second embodiment. The hardware configuration for carrying out this flowchart is as shown in FIG.

  First, in step S1, it is determined whether or not the position of the changeover switch 4 is on the a terminal side. If the position of the changeover switch 4 is not on the a terminal side, the position of the changeover switch 4 is switched to the a terminal side in step S2.

  In step S3, a PLL lock state is established for each frequency point.

  In step S4, the input signal to the VCO 5 is converted into data D1 (n) (n = 1 to 10) via the A / D converter 7 and stored in the memory 12.

  In step S5, the selector switch 4 is switched to the b terminal side.

  In step S6, data D1 (n) already stored is read.

  In step S7, a signal input to the VCO 5 through the D / A converter 8 and the amplifier 9 is generated.

  In step S8, the generated signal generated in step S7 is stored again as data D2 (n) in the memory 12 via the A / D converter 7.

  In step S9, D2 (n) −D1 (n) = error δ is calculated.

  In step S10, D1 (n) is corrected with error δ and stored as corrected data D3 (n) after correction. Specifically, D3 (n) is obtained by adding δ having a polarity opposite to that of δ to D1 (n).

  In step S11, interpolation interpolation (Y = aX + b: see FIG. 4) is performed while reading D3 (n), and interpolation is made between the two points D3 (n) and D3 (n + 1).

In step S12, a sweeping ramp wave (VCO control input voltage V _CNT : actually, a set of individual VCO control input voltages) is generated by repeating all the number of phase-locked points (f1 to f10).

  In step S13, the signal ramp wave generated in step S12 is output via the D / A converter 8 and the amplifier 9.

  In step S14, the ramp wave generated in step S13 is input to VCO 5, and frequency sweeping is started.

  By performing the above error correction processing, errors caused by the ambient temperature or the like can be corrected.

Embodiment 3
In the first and second embodiments described above, all 10 lock frequency points f1 to f10 are connected to sweep the frequency of fmin to fmax. For example, as indicated by SW1 in FIG. 6A, fmin to f1. It is also possible to sweep between f1 and fmax. Further, as indicated by SW2 in FIG. 6B, it is possible to pause between fmin and f2, sweep between f2 and f3, and pause between f3 and fmax. Further, as indicated by SW3 in FIG. 6C, it is possible to pause between fmin and f4 and sweep between f4 and fmax.

  In this way, by controlling the readout range of each point stored in the memory 12, a frequency sweep suitable for the object to be measured can be performed.

  The present invention is applicable to a network analyzer. In a network analyzer as a measuring instrument, there is a sweep oscillation device that supplies a sweep frequency signal in a predetermined frequency range to a device under test at a high speed and with a high resolution in order to measure the frequency characteristics or impedance matching state of a component. It is essential. Therefore, according to the present invention, it is possible to provide a sweep oscillation apparatus, a sweep oscillation method, and a sweep frequency control program that supply a sweep frequency signal in a predetermined frequency range to a device under test.

It is a circuit diagram explaining the technique used as the premise of this invention. It is a circuit diagram explaining the other technique used as the premise of this invention. It is a block diagram which shows the sweep oscillation apparatus to which this invention is applied. It is explanatory drawing for demonstrating the operation | movement of FIG. 10 is a flowchart for explaining an operation in the second embodiment. FIG. 11 is an explanatory diagram showing an operation example in the third embodiment.

Explanation of symbols

1 Crystal oscillator 2 Phase comparator (PD)
3 Loop filter 4 Changeover switch 5 Voltage controlled oscillator (VCO)
6 1 / N frequency divider 7 A / D converter 8 D / A converter 9 Amplifier (AMP)
10 I / O circuit 11 CPU
12 memory

Claims (7)

In a sweep oscillation device that generates a frequency within a predetermined sweep frequency range by applying a frequency control voltage to the voltage controlled oscillator,
A phase lock is applied at a predetermined frequency point Fn (n is a positive integer from 1 to N) within the predetermined sweep frequency range, and the frequency control voltage Vn (n is a value of the voltage controlled oscillator at each frequency point). , A sweep preprocessing means for storing (a positive integer from 1 to N),
Phase lock stop means for stopping the operation of the phase locked loop including the voltage controlled oscillator and disconnecting the voltage controlled oscillator from the phase locked loop;
An arithmetic means for calculating an interpolation voltage for interpolating between two adjacent frequency control voltages among the frequency control voltages Vn stored by the sweep preprocessing means;
Sweep execution means for sequentially generating a predetermined spot frequency from the voltage controlled oscillator by applying the interpolation voltage to the voltage controlled oscillator separated from the phase locked loop by the operation of the phase lock stop means;
A sweep oscillation apparatus comprising: The sweep oscillation apparatus according to claim 1,
The calculation means calculates an interpolation voltage for interpolating between two adjacent frequency control voltages among the frequency control voltages Vn stored by the sweep preprocessing means.
The storage data D1n related to the frequency control voltage Vn stored by the sweep preprocessing unit is read again from the memory,
After converting the stored data D1n into an analog signal A1n, the analog signal A1n is digitally converted to form reconverted data D2n;
The interpolation voltage is calculated by using the difference between the stored data D1n and the reconverted data D2n as correction error data δ.
A sweep oscillation device characterized by that. The sweep oscillation device according to claim 1 or 2,
After the sweep mode within the predetermined sweep frequency range is executed by the sweep execution means, the calibration mode is executed again by the pre-sweep processing means, the phase lock stop means, and the calculation means. A sweep oscillation apparatus characterized by the above. In a sweep oscillation method for generating a frequency within a predetermined sweep frequency range by applying a frequency control voltage to the voltage controlled oscillator,
A phase lock is applied at a predetermined frequency point Fn (n is a positive integer from 1 to N) within the predetermined sweep frequency range, and the frequency control voltage Vn (n is a value of the voltage controlled oscillator at each frequency point). , A pre-sweep processing step that stores a positive integer from 1 to N),
A calculation step for calculating an interpolation voltage for interpolating between two adjacent frequency control voltages among the frequency control voltages Vn stored in the pre-sweep processing step;
A sweep execution step of sequentially generating a predetermined spot frequency from the voltage controlled oscillator by applying the interpolated voltage to the voltage controlled oscillator disconnected from the phase locked loop;
A sweep oscillation method characterized by comprising: The sweep oscillation method according to claim 4, wherein
The calculation step further includes:
Reading stored data D1n related to the frequency control voltage Vn stored in the pre-sweep processing step from the memory again;
Converting the stored data D1n into an analog signal A1n and then digitally converting the analog signal A1n to form reconverted data D2n;
By using the difference between the stored data D1n and the reconverted data D2n as the correction error data δ, the frequency control voltage Vn stored in the pre-sweep processing step is corrected, and the difference between the two adjacent frequency control voltages is corrected. Calculating an interpolation voltage for interpolating
A sweep oscillation method characterized by comprising: The sweep oscillation method according to claim 4 or 5,
After the sweep mode within the predetermined sweep frequency range is executed by the sweep execution step, the calibration mode is executed again by the sweep preprocessing step and the calculation step. Oscillation method.   7. A sweep frequency control program storing the sweep oscillation method according to claim 4 in a form readable by a controller of the sweep oscillation apparatus.

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