JP2005150673A - Etching method and element isolation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide etching method capable of carrying out the etching which is uniform and can be easily controlled even in various semiconductor devices, such as semiconductor device of a multilayer structure or multi-element semiconductor and to provide an element isolation method. <P>SOLUTION: The etching is as follows: an etchant composed of hydrochloric acid is cooled at 5°C or lower and a phosphorus semiconductor layer is immersed in the etchant. It is desirable that the etchant is cooled at 0°C or lower, considering maintenance of an active layer area. The phosphorous semiconductor layer may be a multilayer structure and have a layer containing aluminum as well as have a layer containing gallium, indium, or phosphorus. The unevenness of the etching can be prevented by carrying out the etching divided into a plurality of times and by carrying out the cleaning to remove bubbles on the surface of the phosphorous semiconductor layer in an interval of etching. When carrying out a plurality of etching, the temperature range of the entchant is desirably at -5°C or lower, more preferably at -10°C or lower. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an element isolation method for a semiconductor element using etching, and more particularly to an etching method and an element isolation method for a semiconductor element having a multi-element multilayer structure.

Conventionally, in order to individually isolate each semiconductor element after forming a plurality of semiconductor elements on a substrate, an element isolation method has been used in which an element isolation groove is formed by removing between the semiconductor elements using etching. . The etchant used for etching is appropriately selected depending on the constituent elements of the layer structure to be removed. In a gallium indium phosphorus (GaInP) based semiconductor element, hydrogen chloride (HCl) and acetic acid (CH ₃ COOH) are used. A mixed aqueous solution was used. (For example, see Patent Document 1)

  In the etching for forming the element isolation trench to separate the semiconductor element, it is necessary to make the size of the semiconductor element uniform, and in order to adjust the surface state of the semiconductor element, the removal rate of the semiconductor layer per unit time It is important to control the etching rate. If the etching rate is too high, the removal amount of the semiconductor layer changes due to fluctuations in etching time, and it becomes difficult to make the size of the semiconductor element uniform. Further, if the etching rate is too high, unevenness, which is a region where the progress of etching is locally slow, occurs, which may disturb the surface state of the semiconductor element and adversely affect the performance of the semiconductor element.

  In the conventional etching using an etchant in which acetic acid and hydrogen chloride are mixed, the etching rate is adjusted by controlling the concentration of acetic acid using acetic acid as a buffer material. In general, in the etching reaction of the semiconductor layer, the etching rate changes depending on the temperature at the time of the reaction. Therefore, the etching rate is also controlled by controlling the temperature of the etchant.

JP 2002-198616 A

  However, in the etchant containing acetic acid described in Patent Document 1, the acetic acid begins to solidify around 5 ° C., which is the freezing point of acetic acid, and the etchant becomes a gel in a temperature range of 5 ° C. or lower. There is a problem that it cannot be used for etching. In addition, when the ratio of acetic acid contained in the etchant is lowered, the concentration of hydrogen chloride increases, so that the etching rate increases, and it becomes difficult to control the thickness of the semiconductor layer removed by etching. there were.

  In addition, when the structure of the semiconductor element is a multi-element structure and a multilayer structure, since the etching rate for each layer is different, different amounts of etching are performed for each layer. Therefore, there is a problem that the etched surface is not uniform. Further, in the technique described in Patent Document 1, since the object to be removed is gallium indium phosphorus (GaInP), even if etching is performed in a temperature range above the freezing point of acetic acid, it is removed because the etching rate is low. Easy to control the amount. However, for example, a layer containing aluminum (Al) has a problem that the etching rate is increased, the time required for etching is extremely short, and the removal amount is difficult to control. For example, when the temperature rises by 2 ° C. at the end of etching due to reaction heat, the etching rate rapidly changes because the temperature reaches 10 ° C. at the end of etching at about 8 ° C., and the amount of etching can be controlled in seconds. It was difficult.

  Further, when a wafer on which a light-emitting diode (LED) structure is formed is separated, methods such as dicing and cleavage are used. However, when the LED is diced, the cleavage surface is likely to be damaged, and it is difficult to form an inclined surface on the side surface of the element. Therefore, for example, a device in which an n-type gallium phosphide (GaP) substrate that is sufficiently thick with respect to the thickness of the LED structure and an n-type cladding layer of the LED are bonded together is subjected to element isolation by dicing. An inclined surface is formed on the GaP substrate side, and an inclined surface for improving light extraction is formed on the element side surface.

  In the case of forming an inclined surface by separating elements by wet etching, acetic acid is mixed in hydrochloric acid as an etchant as a buffer, and hydrochloric acid and acetic acid in the etchant are mixed in a low temperature region of 5 ° C. or more and room temperature where the solution does not solidify. In order to mix well, wet etching was performed with stirring. However, it is difficult to accurately control the etching amount per unit time in the fabrication of the element shape using this etching technique, and in the multilayer film having different material composition and material composition ratio, the etching rate for each layer is also high. Because of the difference, it is difficult to form a uniform inclined surface (for example, 111 surface) on the side surface of the element, and it is difficult to make the inclination angle and area uniform.

  Thus, since it is difficult to strictly control the etching rate in the conventional method, it is extremely difficult to form a uniform side shape on a fine element, and the element shape is formed by applying physical external force. Thus, there is a problem that the side surface of the element is damaged by the processing. When the element is damaged, there is a problem that the physical characteristics of the element such as electric conductivity and light emission characteristics are changed or defective.

  Accordingly, an object of the present invention is to provide an etching method and an element isolation method capable of performing uniform and easy control even in various semiconductor elements such as a multi-layer semiconductor element and a multi-element semiconductor element. .

  In order to solve the above-described problems, the etching method of the present invention includes performing etching by cooling an etchant made of hydrochloric acid to a temperature lower than 5 ° C. and immersing a phosphorous semiconductor layer formed on a substrate in the etchant. Features.

  By using hydrochloric acid as an etchant and cooling to a temperature range lower than 5 ° C. to etch the phosphorous semiconductor layer, the etching rate can be lowered. Therefore, the time required for etching can be extended, and the removal amount can be easily controlled to perform uniform etching. Further, since the fluctuation of the etching rate due to the reaction heat in the etching can be suppressed, the removal amount can be easily controlled.

  Further, by etching by etching an etchant made of hydrochloric acid to a temperature lower than 5 ° C., even when the phosphorus-based semiconductor layer has a multi-layer structure, the etching rate for removing each layer of the multi-layer structure becomes uniform, and the removal amount is reduced. Control becomes easy. In addition, even in a layer having a relatively high etching rate, such as a layer containing aluminum, it can be uniformly removed at the same etching rate as the other layers. Is possible. Even when the multilayer structure of the phosphorus-based semiconductor layer has a layer containing gallium, indium, and phosphorus, the etching rate can be made uniform and low.

  Even with an etchant containing a small amount of phosphoric acid, the etching rate can be kept low, and the removal amount can be easily controlled. In addition, by using alcohol as a coolant for cooling the etchant, the etchant can be easily cooled to a temperature range lower than 5 ° C., and the etching rate is suppressed to be low and the controllability of the removal amount is improved. be able to. By using alcohol as the coolant, it is possible to further control the etching rate by cooling the etchant to 0 ° C. or lower. Further, by cooling the etchant to −5 ° C. or lower, it becomes possible to control the etching amount in a favorable manner even when the surface of the phosphorus-based semiconductor layer is cleaned by repeating etching a plurality of times.

  Further, in order to solve the above-described problems, the etching method of the present invention performs etching a plurality of times by cooling an etchant made of hydrochloric acid to a temperature lower than 5 ° C. and immersing a phosphorous semiconductor layer formed on the substrate in the etchant. And performing cleaning to remove bubbles adhering to the surface of the phosphorus-based semiconductor layer between the first etching and the second etching.

  Etching is performed by cooling the etchant made of hydrochloric acid to a temperature lower than 5 ° C., so that the time required for the etching can be increased. Therefore, the etching can be performed a plurality of times. During the first etching and the second etching, cleaning is performed to remove bubbles adhering to the surface of the phosphorus-based semiconductor layer, thereby removing bubbles generated on the surface of the phosphorus-based semiconductor layer and causing uneven etching. And uniform removal can be realized.

  Further, in order to solve the above-described problems, the element isolation method of the present invention includes an element obtained by cooling an etchant made of hydrogen chloride to a temperature lower than 5 ° C. and immersing a phosphorous semiconductor layer formed on a substrate in the etchant. A separation groove is formed.

  By using hydrochloric acid as an etchant and cooling to a temperature range lower than 5 ° C. to etch the phosphorous semiconductor layer, the etching rate can be lowered. Therefore, the time required for etching can be extended, and the removal amount can be easily controlled to form a uniform element isolation groove. Further, since the fluctuation of the etching rate due to the reaction heat in the etching can be suppressed, the removal amount can be easily controlled.

  In order to solve the above problems, an element isolation method of the present invention is an element isolation method in which an element isolation groove is formed using an etchant made of hydrochloric acid, and the solubility of the etchant on the surface of a phosphorous semiconductor layer is increased. A mask having a side intersecting with a high crystal orientation at a predetermined angle is formed, the etchant is cooled to a temperature lower than 5 ° C., and the phosphorus-based semiconductor layer is immersed in the etchant to form an inclined surface in the element isolation trench. It is characterized by that.

  By using hydrochloric acid as an etchant in a low temperature region and utilizing so-called etching anisotropy that the etching rate varies depending on the crystal plane orientation of the etching target, an inclined surface can be formed in the element isolation groove without damaging the element. Thus, it is possible to improve the characteristics of the element, such as improving the light extraction efficiency.

  At this time, it is assumed that one side of the mask is formed in a direction perpendicular to the crystal orientation in which the phosphorus-based semiconductor layer has high solubility in the etchant, or one side of the mask has crystal orientation in which the phosphorus-based semiconductor layer has low solubility in the etchant. Therefore, it is possible to easily form a surface with low solubility as the inclined surface of the element isolation groove. The crystal orientation with high solubility in the etchant is the 110 direction of the phosphorous semiconductor layer, and the inclined surface is the 111 plane of the phosphorous semiconductor layer. In addition, by setting the inclination angle of the inclined surface with respect to the substrate within a range of 30 degrees to 60 degrees, it is possible to improve the light extraction efficiency when light emitted inside the element is extracted from the 100 surface.

  By immersing the phosphorus-based semiconductor layer in an etchant made of hydrochloric acid in an environment at a temperature lower than 5 ° C., a low etching rate can be realized even if the temperature rise due to reaction heat in etching is taken into account. It is possible to control the removal amount by increasing the time. Also, even in a multi-element, multi-layered semiconductor layer, the etching rate of each layer can be made uniform, so that the element shape is uniformed by forming uniform element isolation grooves with uniform removal amounts of each layer. Is possible.

Hereinafter, an etching method and an element isolation method to which the present invention is applied will be described in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably.
[First embodiment]

  FIG. 1 is a process step view for explaining an etching method and an element isolation method according to the present invention. In the etching method and element isolation method of the present invention, in order to form a plurality of semiconductor elements on a substrate, a multi-layer structure of a phosphorus-based semiconductor layer is formed on the substrate, and then between each element is etched and removed. An element isolation trench is formed.

  First, as shown in FIG. 1A, as a phosphorus-based semiconductor layer to be subjected to element isolation, aluminum-gallium n-type doped on a n-type gallium arsenide (n-GaAs) layer 11 on a substrate. Indium-phosphorus (n-AlGaInP) layer 12, active layer 13 constituting a multi quantum well, p-type doped aluminum gallium indium-phosphorus (p-AlGaInP) layer 14, p-type doped A multilayer semiconductor unit 10 having a multilayer structure in which a gallium indium phosphide (p-GaInP) layer 15 and a p-type doped gallium arsenide (p-GaAs) layer 16 are formed is prepared. Thereafter, a resist is applied on the p-GaAs layer 16 which is the uppermost layer. After exposure to an element isolation pattern, the resist is removed to form a mask layer 17. After the mask layer 17 is formed, etching is performed to remove the p-GaAs layer 16 at a position corresponding to the opening of the mask layer 17.

  Here, an aluminum / gallium / indium / phosphorus layer or a gallium / indium / phosphorus layer is shown as a phosphorus-based semiconductor layer formed on the substrate. However, if a semiconductor layer containing phosphorus is formed, other compositions may be used. It may be a semiconductor layer. Further, it is not necessary that all layers contain phosphorus, and a semiconductor layer containing phosphorus may be formed in a layer to be removed by etching. Further, in the multilayer semiconductor portion 10 which is a phosphorus-based semiconductor layer formed on the substrate shown in FIG. 1A, the elements are separated by etching to form an LED (light-emitting diode) which is a light emitting element. However, the element separated by etching does not have to be a light emitting element.

  Next, as shown in FIG. 1B, the multilayer semiconductor portion 10 is immersed in an etchant cooled to −11 ° C. with hydrochloric acid, and the p-GaInP layer 15, the p-AlGaInP layer 14, the active layer 13, and the n− The AlGaInP layer 12 is removed. Since the etchant used for etching of the present invention does not contain acetic acid, the etchant temperature can be cooled to a temperature lower than the freezing point of acetic acid, and the etching rate is suppressed. The etching reaction proceeds more slowly. By performing the etching at a low etching rate using a low temperature etchant, the time required for the etching becomes longer, so that the removal amount by the etching can be easily controlled.

  In addition, since etching is performed using an etchant made of hydrochloric acid, the etching progresses evenly in the multilayer semiconductor portion 10 having a multilayer structure, regardless of the composition to be removed. Accordingly, the etching reaction in the multilayer semiconductor portion 10 becomes isotropic, and the removal amount similar to that of the other layers can be realized even in the layer containing aluminum. Since the reaction by etching is isotropic in each layer, the etching gradually proceeds in the lower layer direction of the multilayer semiconductor portion 10, and the p-GaInP layer 15, the p-AlGaInP layer 14, the active layer 13, and the n-AlGaInP. Even if the layer 12 is removed, V-shaped grooves are gradually formed in the depth direction and the horizontal direction as shown in FIG.

  As shown in FIG. 1C, the etching reaction using hydrochloric acid proceeds uniformly and isotropically in each layer of the multilayer structure of the multilayer semiconductor portion 10, and the etchant reaches the n-GaAs layer 11 which is the lowest layer. Reach. Since the n-GaAs layer 11 does not react with an etchant made of hydrochloric acid, the etching reaction stops at the n-GaAs layer 11 and the n-GaAs layer 11 functions as an etching stop layer. After the etching reaction in the depth direction stops in the n-GaAs layer 11, the etching reaction proceeds in the horizontal direction of each layer until the multilayer semiconductor portion 10 is taken out from the etchant. When these etching reactions are completed, an element isolation groove 18 is formed at a position corresponding to the opening of the mask layer 17 to complete the isolation of the semiconductor element.

  In the etching method and the element isolation method shown in FIG. 1, since etching takes a long time by performing etching at a low etching rate using a low temperature etchant, it becomes easy to control the amount removed by etching. . Etching with hydrochloric acid at a low temperature removes each layer of the multilayer structure even when the multilayer semiconductor portion 10 has a multilayer structure and has a layer containing aluminum or a layer containing gallium, indium, and phosphorus. The etching rate becomes uniform and the removal amount can be easily controlled. In addition, even in a layer having a relatively high etching rate, such as a layer containing aluminum, it can be uniformly removed at the same etching rate as the other layers. Is possible.

  FIG. 2 is a schematic view showing an apparatus configuration example for realizing the above-described etching method and element isolation method of the present invention. A cooling vessel 21 for cooling the etchant with a Peltier element or the like to realize a temperature range of 0 ° C. or lower is filled with a refrigerant 22 such as alcohol that does not solidify even at 0 ° C. or lower, and the reaction vessel 23 is installed in the refrigerant 22. . An etchant 24 made of hydrochloric acid is placed in the reaction vessel 23, and the multilayer semiconductor portion 10 on which a mask for forming an element isolation groove is formed is immersed in the etchant 24.

  By using hydrochloric acid as the etchant 24 and cooling it to a temperature range lower than 5 ° C. to etch the multilayer semiconductor portion 10, the etching rate can be lowered. Therefore, the time required for etching can be extended, and the removal amount can be easily controlled to form a uniform element isolation groove. Further, since the fluctuation of the etching rate due to the reaction heat in the etching can be suppressed, the removal amount can be easily controlled. At this time, by cooling the etchant to −10 ° C. or lower, the etching rate is further lowered and the removal amount can be easily controlled.

  Although alcohol is exemplified here as the refrigerant 22, any material that can cool the etchant to 0 ° C. or lower may be used. For example, a material that can be cooled to about the freezing point of hydrochloric acid is preferably used as the refrigerant. Further, although the Peltier element is illustrated as a means for cooling the cooling container 21, many methods such as a cooling means using a compressor and a refrigerant may be used instead of a cooling means by a thermoelectric effect. Further, although the etchant is hydrochloric acid, other solution such as phosphoric acid may be mixed slightly, but the etchant should be substantially made of hydrochloric acid. For example, when an aqueous solution in which a small amount of phosphoric acid is added to hydrochloric acid is used as an etchant, the n-GaAs layer 11 at which etching stops is slightly removed, but some removal of the n-GaAs layer 11 can be allowed. In this case, phosphoric acid can be mixed. Even with an etchant containing a small amount of phosphoric acid, the etching rate can be kept low, so the removal amount can be easily controlled.

  An etchant made of hydrochloric acid has a freezing point of about −50 ° C. only with hydrogen chloride. For example, a commercially available hydrochloric acid with a concentration of 30% has a freezing point of about −10 ° C. or lower. Etching may be performed in a temperature range in which the etchant can hold a liquid without being limited to ° C. Since the chemical reaction is suppressed by lowering the Gibbs free energy, the etching rate is lowered as the etchant temperature is lowered, and the etching time is prolonged, so the controllability of the removal amount is improved. When aluminum (Al) is contained in the etching target layer, the etching progresses quickly, so that the amount to be removed can be easily adjusted by performing the etching at a low temperature.

  In the prior art, water was used as a coolant for cooling the etchant, so that the etchant could not be cooled to a temperature range lower than 0 ° C., and the lower limit of the etching rate was limited. It was difficult to control the removal amount. However, in the element isolation method of the present invention, by using alcohol or the like as a refrigerant, the etchant can be cooled to a temperature range of 0 ° C. or lower, and the etching rate can be lowered and the etching time can be extended. This makes it easy to control the removal amount.

  FIG. 3 is a photomicrograph showing the state of the semiconductor element after etching. FIG. 3A shows the semiconductor element when the element isolation method of the present invention is used, and FIG. Shows a semiconductor element when a conventional element isolation method is used.

  In the element isolation method of the present invention shown in FIG. 3A, as described with reference to FIG. 1, etching is performed by immersing the multilayer semiconductor portion 10 in an etchant cooled to −10 ° C. with hydrochloric acid. The element isolation groove 18 was formed until the GaAs layer 11 was reached. By using the element isolation method of the present invention, as shown in the micrograph of FIG. 3A, the side surfaces of the element isolation grooves 18 are uniformly removed over each layer of the multilayer structure, and the multilayer semiconductor portion 10 having the multilayer structure. However, it can be seen that the etching reaction progressed isotropically.

In the conventional element isolation method shown in FIG. 3B as a comparison object, the multilayer semiconductor portion 10 is placed in an etchant cooled to 8 ° C. for 30 seconds with an aqueous solution in which hydrogen chloride (HCl) and acetic acid (CH ₃ COOH) are mixed. The element isolation groove 18 was formed by dipping until the n-GaAs layer 11 was reached. As shown in the micrograph in FIG. 3B, it can be seen that the side surfaces of the element isolation grooves 18 are removed unevenly, and each layer of the multilayer structure is stepped. When acetic acid (CH ₃ COOH), which is a buffer, is not mixed, and an etchant containing only hydrochloric acid is used at about 8 ° C, the etching rate is too high and etching can be performed only for about 1 second. Becomes even more difficult.

  FIG. 4A is a diagram schematically showing a cross section of the multilayer semiconductor portion 10 when the element isolation method is used using the etchant made of hydrochloric acid shown in FIG. In the multilayer semiconductor portion 10 having the structure, the element isolation groove 18 can be formed by performing uniform etching. In particular, it can be seen that the etching proceeds uniformly regardless of whether the layer contains aluminum (Al) or not.

FIG. 4B schematically shows a cross section of the multilayer semiconductor portion 10 in the case of using an etchant mixed with hydrogen chloride (HCl) and acetic acid (CH ₃ COOH) shown in FIG. In the phosphorus-based semiconductor layer having a multi-element and multi-layer structure, the etching rate varies depending on the constituent elements of each layer, so that the side surfaces of the element isolation trenches 18 are non-uniform. Since an etchant mixed with acetic acid is used, it is necessary to perform etching in a temperature range of 5 ° C. or more, which is the freezing point of acetic acid, and the etching rate increases in the layer containing aluminum (Al), so It becomes difficult to maintain uniformity.

FIG. 5 is a photomicrograph showing the surface of the multilayer semiconductor portion 10 in a state where the etchant made of hydrochloric acid is cooled to −5 ° C., the multilayer semiconductor portion 10 is immersed, the element isolation trench is formed, and then washed with water. Bubbles that appear to be hydrogen (H ₂ ) due to the etching reaction adhere to the surface of the multilayer semiconductor portion 10 and the surface of the element isolation groove 18 being formed. If the etching reaction is continued with this being left as it is, the etchant does not come into contact with the multilayer semiconductor portion 10 or the element isolation groove 18 in the area where the bubbles are attached, and the etching becomes uneven and the surface is disturbed, as shown in FIG. Residue may be generated.

  As described above, in the etching method and the element isolation method of the present invention, the etching reaction can be prolonged by cooling the etchant made of hydrochloric acid to a temperature lower than 5 ° C. Etching can be performed once.

  Therefore, the reaction time is lengthened by etching at a low temperature, and the etching is performed in two or more times. At this time, the multilayer semiconductor part 10 is pulled up from the etchant 24 between the first etching and the second etching, and the surface of the multilayer semiconductor part 10 is washed with running water to remove bubbles. By performing cleaning between etchings, even when bubbles are generated by the etching reaction, it is possible to achieve uniform removal by suppressing the occurrence of etching unevenness due to the influence of the bubbles, and the end surfaces of the element isolation grooves are prepared. It is possible to perform element isolation.

  FIG. 6 is a graph showing the results of measuring the active layer area of the device at five locations within the substrate surface. For element isolation, crystal growth is performed on a 3 inch diameter semiconductor substrate, immersed in hydrochloric acid at −10 ° C., the surface of the multilayer semiconductor portion 10 is washed with pure water, and then immersed in hydrochloric acid at −10 ° C. again. An element isolation trench was formed.

  FIG. 7 is a graph showing the temperature characteristic of the active layer area of the LED and the temperature characteristic of the etching rate when the etching method and the element isolation method of the present invention are used. In the figure, the horizontal axis indicates the temperature of hydrochloric acid as an etchant, the vertical axis indicates the active layer area of the LED element formed on the substrate, and the vertical axis indicates the etching rate in etching using hydrochloric acid. . Moreover, the graph shown by the open triangle in the figure shows the result of etching by immersing the phosphorus-based semiconductor layer formed on the substrate in hydrochloric acid. In addition, the graph shown by the white square in the figure is the result after double etching in which the phosphorus-based semiconductor layer formed on the substrate was immersed in hydrochloric acid, washed with pure water, and then immersed in hydrochloric acid and etched again. Is shown. The graph indicated by black triangles in the figure indicates the etching rate of hydrochloric acid.

  As can be seen from the graph indicated by the white triangle in the figure, the active layer area of the LED element formed on the substrate decreases as the etchant temperature rises, and from 0 ° C. as the etching rate increases. It can be seen that the active layer area is significantly reduced at high temperatures. Moreover, the residue as shown in FIG. 5 may generate | occur | produce on the surface of a semiconductor layer below -2 degreeC of the graph shown with the white triangle in the figure. However, as shown by the white squares in the figure, no residue was observed after double etching in which additional etching was performed after pure water cleaning.

  From this result, it can be seen that in the case of hydrochloric acid having an etchant temperature range higher than 5 ° C., the element size becomes about 80% or less of the design value by side etching after element isolation. Although this side etching rate greatly depends on the etchant temperature, the etching time can be controlled optimally for element isolation because the etching rate hardly changes even when additional etching is performed at 0 ° C. or lower. As indicated by the white squares in the figure, when the etchant temperature is 0 ° C. or lower, the active layer area is maintained even when double etching is performed, and particularly at −5 ° C. or lower, the active layer is 80% or higher. The area can be maintained, and an active layer area of 90% or more can be maintained at −10 ° C. or lower. Therefore, it can be seen that it is important to perform the etching in a temperature range of preferably −5 ° C. or lower, more preferably −10 ° C. or lower in order to maintain the active layer area.

  From the temperature dependency of the etching rate shown in FIG. 7, it can be seen that the etching rate increases exponentially with respect to the temperature of hydrochloric acid. This is due to the behavior of Gibbs energy and can be said to be the result of following the chemical reaction law. For example, when an element shape equivalent to etching for 60 seconds at an etchant temperature of −10 ° C. is to be realized by etching at an etchant temperature of 5 ° C., simply calculating from the etching rate ratio results in etching. The time required is 4.5 seconds or less.

  In an actual manufacturing process, it is difficult to completely control the work from start to finish within such a short etching time. Further, when etching a semiconductor layer formed on a 3-inch substrate in a temperature range higher than 5 ° C., the heat generated by a chemical reaction increases as the area increases, greatly affecting the etching rate. . Therefore, in order to improve the work accuracy of etching, the temperature range of the etchant should be lower than 5 ° C., preferably 0 ° C. or lower, and -5 ° C. or lower or −10 ° C. or lower in consideration of maintaining the total active area. .

  The element shape in the plane of a 3-inch wafer subjected to double etching at −10 ° C. was very uniform as shown in FIG. Since the area of a 3-inch wafer is large, it is slightly smaller than the active layer area under the same conditions when a temperature-dependent experiment is performed. This is considered to be due to the influence of heat generated by a chemical reaction. When the liquid temperature of the etchant is 5 ° C. or higher, the etching rate changes greatly due to the influence of reaction heat, so that uniform element shape control can be considered very difficult.

As described above, the temperature range of the etchant is desirably lower than 5 ° C. in the element isolation method using hydrochloric acid as an etchant also from the viewpoint of the temperature dependency of the etching rate, the temperature dependency of the element shape, and the working accuracy. A more preferable temperature range is 0 ° C. or less where the active layer area can be formed. Moreover, even if double etching is performed, it can be seen that the active layer area is well maintained at −5 ° C. or lower, more preferably −10 ° C. or lower.
[Second Embodiment]

  Next, another embodiment of the element isolation method of the present invention will be described with reference to the drawings. In the element isolation method of this embodiment, etching is performed using hydrochloric acid as an etchant in a low temperature region, and so-called etching anisotropy is used in which the etching rate varies depending on the crystal plane orientation to be etched. By performing etching using etching anisotropy, a slope can be formed as an etched surface after element isolation, and the characteristics of the element can be improved, for example, by improving light extraction efficiency.

  As in FIG. 1A, which is the first embodiment, as a phosphorus-based semiconductor layer to be subjected to element isolation, n-type doped gallium arsenide (n-GaAs) layer 11 is formed on a substrate. Type-doped aluminum / gallium / indium / phosphorus (n-AlGaInP) layer 12, active layer 13 constituting a multiple quantum well, p-type doped aluminum / gallium / indium / phosphorus (p-AlGaInP) layer 14. A multilayer semiconductor section 10 having a multilayer structure in which a p-type doped gallium indium phosphide (p-GaInP) layer 15 and a p-type doped gallium arsenide (p-GaAs) layer 16 are formed is prepared.

Thereafter, a resist is applied on the p-GaAs layer 16 which is the uppermost layer. After exposure to an element isolation pattern, the resist is removed to form a mask layer 17. After the mask layer 17 is formed, etching is performed with an aqueous solution in which phosphoric acid (H ₃ PO ₄ ), hydrogen peroxide water (H ₂ O ₂ ), and water (H ₂ O) are mixed, so that openings in the mask layer 17 are formed. The p-GaAs layer 16 at the corresponding position is removed.

  FIG. 8A is a plan view showing a state in which the mask layer 17 is formed on the p-GaAs layer 16 of the phosphorus-based semiconductor layer. The directions indicated by the arrows in the figure are the a-axis and b-axis directions of the crystal orientation, and the direction perpendicular to the paper surface is the c-axis direction. FIG. 8B is a view seen from the short side of the mask shape in order to show the 110 plane and the 111 plane of the multilayer semiconductor portion 10 which is a phosphate semiconductor layer. FIG. 8C is a view of the 111 surface of the multilayer semiconductor portion 10 that is a phosphoric acid semiconductor layer as viewed from the long side of the mask shape. A direction indicated by a thick arrow in the drawing indicates that etching proceeds in a direction perpendicular to the 110 plane of the multilayer semiconductor portion 10.

  The shape of the mask layer 17 is a rectangle as shown in the figure, and its long side direction is perpendicular to the 110 direction of the phosphorus-based semiconductor layer. In general, in wet etching, the etching rate varies depending on the crystal plane orientation to be etched. For this reason, the etching reaction proceeds in accordance with the plane orientation, and the shape of the region removed by the etching depends on the crystal plane orientation. In the etching of the phosphorus-based semiconductor layer used in this embodiment, the etching rate in the 110 direction is particularly fast. For this reason, when the p-GaInP layer 15, the p-AlGaInP layer 14, the active layer 13, and the n-AlGaInP layer 12 are removed by wet etching, the etching reaction proceeds and reaches the etching stop layer of the n-GaAs layer 11. After that, etching proceeds in the direction of eroding the 110 plane.

  Etching of the p-GaInP layer 15, the p-AlGaInP layer 14, the active layer 13, and the n-AlGaInP layer 12 is performed in an etchant obtained by cooling hydrochloric acid having a concentration of 30% to −10 ° C. as in FIG. Dipping part 10 is performed. At this time, it is not necessary to swing the multilayer semiconductor portion 10 within the etchant.

  Since the etchant used for etching of the present invention does not contain acetic acid, the etchant temperature can be cooled to a temperature lower than the freezing point of acetic acid, and the etching rate is suppressed. The etching reaction proceeds more slowly. By performing the etching at a low etching rate using a low temperature etchant, the time required for the etching becomes longer, so that the removal amount by the etching can be easily controlled. In addition, by performing cleaning between two etchings, even when bubbles are generated due to the etching reaction, it is possible to achieve uniform removal by suppressing the occurrence of etching unevenness due to the influence of bubbles. It is possible to perform element isolation in which the end face of the groove is arranged.

  As shown in FIG. 1C, the etching reaction using hydrochloric acid proceeds uniformly and isotropically in each layer of the multilayer structure of the multilayer semiconductor portion 10, and the element separator 18 is formed in a V shape. The etchant reaches the n-GaAs layer 11 which is the lowest layer. Since the n-GaAs layer 11 does not react with an etchant made of hydrochloric acid, the etching reaction stops at the n-GaAs layer 11 and the n-GaAs layer 11 functions as an etching stop layer. After the etching reaction in the depth direction stops in the n-GaAs layer 11, the etching reaction proceeds in the horizontal direction of each layer until the multilayer semiconductor portion 10 is taken out from the etchant. When these etching reactions are completed, an element isolation groove 18 is formed at a position corresponding to the opening of the mask layer 17 to complete the isolation of the semiconductor element.

  As described above, the etchant that has reached the n-GaAs layer 11 that is the etching stop layer undergoes an etching reaction in the horizontal direction of each layer. At this time, the etching rate for the multi-layer semiconductor portion 10 is approximately one-hundredth of the etching rate for the 111 surface relative to the etching rate for the 110 surface, and thus the mask formed perpendicular to the 110 direction. On the long side of the layer 17, the etching reaction is suppressed by exposing the 111 surface. Therefore, after the multilayer semiconductor portion 10 is taken out from the etchant and the element isolation is completed, a slope is formed only on the long side of the element by the 111 plane. On the other hand, on the short side of the mask layer 17, the 111 surface is never exposed as a surface, so that the etching reaction proceeds on the 110 surface, and the etching rate is not reduced, and the mask layer 17 is short. A vertical surface is formed by etching up to the side region.

  FIG. 9A is a schematic diagram showing the relationship between the plane orientation of the semiconductor substrate forming the multilayer structure of the multilayer semiconductor 10 and the formation direction of the mask layer 17. An orientation flat indicating the plane orientation of the semiconductor substrate indicates the 110 plane, and the long side direction of the mask layer 17 is formed in a direction perpendicular to the 110 direction. In the drawing, in order to show the relationship between the long side direction of the mask layer 17 and the plane orientation of the semiconductor substrate, the size of the mask layer 17 is enlarged, but the size of the mask layer 17 is arbitrary, Is formed as a very fine pattern compared to the size of the semiconductor substrate.

  FIG. 9B is a photomicrograph after element isolation is performed by etching using hydrochloric acid at a low temperature as described above after forming the mask layer 17 as shown in FIG. 9A. A region shown as a rectangle in the figure is an element shape provided with a mask layer 17, and an element isolation groove is formed by etching between adjacent elements. In the drawing, the long side region of the element is black in the same direction as the long side direction of the mask layer 17, and the etching reaction is suppressed by exposing the 111 surface, and a slope corresponding to the 111 surface is formed. It is because it has been. On the other hand, no slope is formed in the short side region of the element, and it can be seen that the element isolation groove can be formed in a substantially vertical direction.

  FIG. 10A is a schematic diagram showing the relationship between the plane orientation of the semiconductor substrate and the formation direction of the mask layer 17 when the short side direction of the mask layer 17 is perpendicular to the 110 plane of the multilayer semiconductor 10. FIG. An orientation flat indicating the plane orientation of the semiconductor substrate indicates the 110 plane, and the long side direction of the mask layer 17 is formed in a direction perpendicular to the 110 direction. FIG. 10B is a photomicrograph after element isolation is performed by etching using hydrochloric acid at a low temperature as described above after the mask layer 17 is formed as shown in FIG. As in FIG. 9, in the short side region of the mask layer 17 formed in the direction perpendicular to the 110 plane, the 111 plane is exposed, so that the etching reaction is suppressed and a slope corresponding to the 111 plane is formed. . In the element isolation method of the present invention, the slope of the element isolation groove can be formed using the fact that the etching reaction on the 111 plane is slower than the etching reaction on the 110 plane. Therefore, by forming the short side direction or the long side direction of the mask layer 17 perpendicular to the 110 direction, it is possible to form the inclination of the element isolation groove in an arbitrary direction.

  FIG. 11 is a photomicrograph showing the state of the element isolation groove after element isolation by etching with hydrochloric acid at a low temperature. The left-right direction in the figure is the 110 direction, and the up-down direction in the figure is the 100 direction. In the peripheral region of the element, the side formed in the direction perpendicular to the 110 direction becomes an inclined surface, and the side formed in the 110 direction is separated from the element by etching in the direction perpendicular to the substrate. Understand. At this time, the side surface of the element isolation groove formed as the inclined surface was formed at an angle of approximately 45 degrees with respect to the substrate. Since the 111 plane is at an angle of about 55 degrees with respect to the substrate, the inclination of the element isolation groove on the side perpendicular to the 110 direction is not the state where the 111 plane is completely exposed, but the concentration of hydrochloric acid and It is considered that it is determined by etching conditions such as temperature. Therefore, by changing the etching conditions, it is possible to form an inclination angle similar to the inclination angle of the 111 plane, and to form an inclined surface of about 30 to 60 degrees with respect to the substrate.

  In this way, by performing etching using hydrochloric acid at a low temperature and forming the mask layer 17 in the direction perpendicular to the 110 direction, the 111 surface of the multilayer semiconductor portion 10 is difficult to be etched, and the element is used. An inclined surface can be formed on the side surface. In the case of emitting light by forming a light emitting diode (LED) as an element, light guided in the horizontal direction inside the element is reflected by the inclined surface and proceeds in the vertical direction. For example, a light-emitting diode material using a phosphoric acid semiconductor has a high refractive index, and light emitted from the active layer of the light-emitting diode is reflected toward the inside of the element at the interface with the air, and light traveling in the lateral direction has a sloped surface. Since light is efficiently reflected at the interface and extracted in the vertical direction, the light extraction efficiency can be improved.

  FIG. 12 is a plan view showing an example in which an octagonal mask layer 17 is formed on the p-GaAs layer 16 of the phosphorus-based semiconductor layer. The octagonal mask layer 17 is also formed such that the long side direction is perpendicular to the 110 direction and the short side direction is perpendicular to the 110 plane. As described above, an inclined surface is formed in the element isolation trench on the side formed in the direction perpendicular to the 110 direction. However, when the mask layer 17 is formed in a rectangular shape, the rectangular vertex region is etched in an oblique direction by side etching. 9 to 11 also show that element isolation trenches are formed in the 221 plane direction near the apex of the mask layer 17. Therefore, the mask layer 17 may have an octagonal shape instead of a rectangular shape.

  FIG. 13 is a view showing a state in which an octagonal mask layer 17 is formed and etching is performed. FIG. 13A shows a side shape of an element isolation groove formed by etching, and FIG. These are photomicrographs showing the element shape after etching. Since the long side direction of the mask layer 17 is formed perpendicular to the 110 direction, an inclined surface is formed by the 111 surface having a slow etching rate. Further, as the etching reaction with respect to the 221 plane proceeds, an inclined surface is formed such that the 221 plane is exposed in the periphery where the short side and the long side of the mask layer 17 intersect.

  On the sides of the mask layer 17 formed in the direction perpendicular to the 110 plane, the element isolation trench is formed substantially perpendicular to the substrate because the etching speed of the 110 plane is high. If the side surface of the element is perpendicular to the substrate, the light extraction efficiency cannot be improved due to the reflection of light by the inclined surface described above. However, by forming the inclined surface that exposes the 221 surface, the side surface of the element perpendicular to the substrate is reduced, and the light extraction efficiency can be further improved.

  FIG. 14 is a diagram showing a state in which the octagonal mask layer 17 is formed and etching is performed excessively, and FIG. 14A shows the side shape of the element isolation groove formed by etching, and FIG. b) is a photomicrograph showing the element shape after etching. When the etching time is lengthened, the etching reaction that erodes the 221 surface proceeds, and the device side surface perpendicular to the substrate disappears. If etching is performed excessively, it is difficult to secure the area of the element and the light emission efficiency may be reduced. However, by controlling the etching time, the area of the element side surface perpendicular to the substrate is reduced. It becomes possible to control.

  As described above, the long side of the mask is patterned so as to be perpendicular to the 110 direction by using anisotropic etching of the multilayer semiconductor portion 10, so that the long side of the element is formed by the 111 plane. An inclined surface can be formed. By forming this inclined surface in the element isolation groove, that is, the side surface of the element, the light path in the lateral direction of the element generated by light emission inside the element is reflected in the vertical direction, and the amount of light extracted from the 100 surface of the element Can increase the light extraction efficiency. In the formation of the inclined surface by etching, damage to the element can be reduced as compared with applying physical external force such as dicing or cleavage, and deterioration of the characteristics of the element can be prevented.

It is process sectional drawing explaining the etching method and element isolation method of this invention. It is a schematic diagram which shows the example of an apparatus structure for implement | achieving the etching method and element isolation method of this invention. FIG. 3A is a micrograph of a multilayer semiconductor portion in which element isolation trenches are formed. FIG. 3A is an element isolation method using hydrochloric acid of the present invention as an etchant, and FIG. 3B is hydrogen chloride (HCl) and acetic acid. An etchant mixed with (CH ₃ COOH) is used. FIG. 4A is a schematic cross-sectional view of a multilayer semiconductor portion in which an element isolation groove is formed. FIG. 4A shows an element isolation method using hydrochloric acid of the present invention as an etchant. FIG. 4B shows hydrogen chloride (HCl). An etchant mixed with acetic acid (CH ₃ COOH) is used. It is a microscope picture which shows the state which the residue generate | occur | produced when forming an element isolation groove. It is a graph which shows distribution of the active layer area in a substrate surface at the time of performing etching with hydrochloric acid in two steps. It is the graph which showed the temperature characteristic of the active layer area of LED at the time of using the etching method and element isolation method of this invention, and the temperature characteristic of an etching rate. It is a schematic diagram which shows the element isolation method in 2nd embodiment of this invention, and has shown the state which formed the long side direction of the mask layer perpendicular | vertical with respect to 110 direction. It is a figure which shows the element shape formed with the element isolation method in 2nd embodiment of this invention, and Fig.9 (a) is a schematic diagram which shows the relationship between the surface orientation of a semiconductor substrate, and the formation direction of a mask layer. FIG. 9B is a photomicrograph after element isolation. It is a figure which shows the element shape formed with the element isolation method in 2nd embodiment of this invention, and Fig.10 (a) is a schematic diagram which shows the relationship between the surface orientation of a semiconductor substrate, and the formation direction of a mask layer. FIG. 10B is a photomicrograph after element isolation. It is a microscope picture which shows the state of an element isolation groove after performing element isolation with the element isolation method in 2nd embodiment of this invention. It is a schematic diagram which shows the element isolation method in 2nd embodiment of this invention, and is a top view which shows the example which formed the octagonal mask layer. It is a figure which shows a mode that the octagonal mask layer was formed and etched, FIG.13 (a) shows the side surface shape of the element isolation groove formed by etching, FIG.13 (b) performed the etching It is a microscope picture which shows the latter element shape. FIGS. 14A and 14B show a state where an octagonal mask layer is formed and etching is performed excessively. FIG. 14A shows a side shape of an element isolation groove formed by etching, and FIG. It is a microscope picture which shows the element shape after performing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Multilayer semiconductor part 11 n-GaAs layer 12 n-AlGaInP layer 13 Active layer 14 p-AlGaInP layer 15 p-GaInP layer 16 p-GaAs layer 17 Mask layer 18 Element isolation groove 21 Cooling vessel 22 Refrigerant 23 Reaction vessel 24 Etchant

Claims (16)

  An etching method characterized in that etching is performed by cooling an etchant made of hydrochloric acid to a temperature lower than 5 ° C. and immersing a phosphorous semiconductor layer formed on a substrate in the etchant.   The etching method according to claim 1, wherein the phosphorus-based semiconductor layer has a multilayer structure.   The etching method according to claim 2, wherein the phosphorus-based semiconductor layer has a layer containing aluminum.   The etching method according to claim 2, wherein the phosphorus-based semiconductor layer has a layer containing gallium, indium, and phosphorus.   2. The etching method according to claim 1, wherein a trace amount of phosphoric acid is contained in the etchant.   2. The etching method according to claim 1, wherein alcohol is used as a coolant for cooling the etchant.   The etching method according to claim 1, wherein the etchant is cooled to 0 ° C. or lower.   The etching method according to claim 1, wherein the etchant is cooled to −5 ° C. or lower. An etchant made of hydrochloric acid is cooled to a temperature lower than 5 ° C., and a phosphorous semiconductor layer formed on the substrate is etched several times in the etchant,
An etching method characterized by performing cleaning to remove bubbles adhering to the surface of the phosphorus-based semiconductor layer between the first etching and the second etching.   An element isolation method comprising forming an element isolation groove by cooling an etchant made of hydrogen chloride to a temperature lower than 5 ° C. and immersing a phosphorous semiconductor layer formed on a substrate in the etchant. An element isolation method for forming an element isolation groove using an etchant made of hydrochloric acid,
On the surface of the phosphorus-based semiconductor layer, a mask having a side intersecting at a predetermined angle with a crystal orientation having high solubility in the etchant is formed,
An element isolation method, wherein the etchant is cooled to a temperature lower than 5 ° C., the phosphorus-based semiconductor layer is immersed in the etchant, and an inclined surface is formed in an element isolation groove.   12. The element isolation method according to claim 11, wherein one side of the mask is formed in a direction perpendicular to a crystal orientation in which the phosphorus-based semiconductor layer is highly soluble in the etchant.   12. The element isolation method according to claim 11, wherein one side of the mask is formed in a direction parallel to a crystal orientation in which the solubility of the phosphorus-based semiconductor layer with respect to the etchant is low.   12. The element isolation method according to claim 11, wherein the crystal orientation having high solubility in the etchant is the 110 direction of the phosphorus-based semiconductor layer.   The element isolation method according to claim 11, wherein the inclined surface is a 111 surface of the phosphorus-based semiconductor layer. 12. The element isolation method according to claim 11, wherein an inclination angle of the inclined surface with respect to the substrate is in a range of 30 degrees to 60 degrees.