JP2005141164A - Image display device and image display method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device capable of improving the compression rate of image data to be stored into a video memory of an image display device. <P>SOLUTION: The image display device is equipped with a run length determination circuit capable of performing prompt coding of the image data for the purpose of storing the display data to be displayed on a display screen into a video memory, appropriately changing the display contents and using the same. The device promptly codes the data to be displayed on the display screen, stores the data into a video memory, and appropriately edits and uses the data of the video memory in changing the display contents. The image display device is so constituted as to count the number of appearances relating to all the data patterns of one piece of the image data, select a reference pattern which is a candidate from the counting result of the number of appearance of the pattern, perform compression actually by using the selected reference pattern, determine the reference pattern at which the finest compression rate is attained and store the reference pattern intrinsic to that image together with the coding data into a storage medium (a video memory). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus, an image display apparatus for encoding / decoding image data to be displayed on a display screen using a CRT (Cathode / Ray / Tube) or an LCD included in the image forming apparatus, and an image display method. .

  Generally, an image display device is provided with a video memory for storing image data for display. Since this video memory stores display data as bitmap data, the entropy redundancy affects the memory consumption. For example, in the case of monochrome display of a 640 × 480 dot VGA (Video Graphics Array) screen, when the background data is white data or black data, if it continues as many lines, if stored as bitmap data as it is, 640 × (number of lines) It will take up memory.

  Not only for such display but generally the amount of information of image data is enormous, and when trying to store the image data as it is, the amount of data stored in the video memory becomes enormous and requires a lot of memory As a result, it will be costly.

  Therefore, when storing image data, an encoding method has been proposed in which the amount of data is reduced by encoding and compression, and the image data is handled in the encoded state. For example, there are an MH encoding method or an MMR encoding method, a conversion encoding method such as JPEG and JBIG for natural images, and a compression method including an arithmetic encoding method.

  Also, in the encoding / decoding device of the image display device for binarized image data, the image data is divided into fixed length data, pattern matching comparison processing is performed in parallel, and the matching comparison result In the immediate encoding method in which the run length is determined from the entropy encoding, the display image is stored in the video memory, and at the time of decoding, the image information is decoded into the original bitmap data by the inverse conversion of the above process from the run length. An image display device for forming display data has also been proposed.

  Also, in the encoding / decoding device of the image display device for binarized image data, the image data is divided into fixed length data, pattern matching comparison processing is performed in parallel, and the matching comparison result In the image display device that immediately executes entropy coding by determining the run length from the data register, a register for setting the reference pattern is provided in the data pattern comparison means, and the contents of the predetermined reference pattern for comparison and reference are processed by software from the outside There has been proposed a method having a structure in which the number of data actually stored after being encoded and compressed can be read out via a register by software processing.

Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique that economically realizes an image compression / decompression apparatus that can switch between a plurality of algorithms according to applications and that operates at high speed. According to this, the host CPU that controls the entire apparatus generates or interprets control information for compression or expansion processing, selects an appropriate program from a plurality of image processing apparatus programs stored in the hard disk, The data is transferred to an encoding / decoding device that performs encoding / decoding. The encoding / decoding device downloads and executes it. Next, the host CPU extracts images or compressed data from the hard disk and sequentially transfers them to the encoding / decoding device. The encoding / decoding device processes the data sent according to the previous program. The host CPU sequentially takes out the data processed by the encoding / decoding device and outputs it to the hard disk.
JP-A-5-316369

  However, the conventional encoding and compression method has a complicated encoding process and performs a determination process and an arithmetic process. For example, QM-Coder, which is an arithmetic encoding method, has a complicated process and a low processing speed. Therefore, a lot of processing time is required for encoding or decoding. In addition, since the conventional encoding compression method has been developed in the field of transmitting images with a facsimile machine or the like, there is a tendency to presuppose processing in units of pages in order to improve the compression rate. As a result, when the stored image data is partially extracted and decoded, or further edited and stored, it is necessary to decode a lot of image data in addition to the target data, which wastes time. Therefore, it was not suitable for decoding or editing any part.

  Furthermore, in the conventional encoding method for improving the redundancy, since the run length which is the length of the same data pattern (run) is sequentially counted and encoded, it is a hardware encoding apparatus. Even the software needed a lot of time to determine the optimal pattern. Several clocks or tens of clocks are required to determine one run length. When such a conventional encoding / decoding method is applied to storage of display data (image data) in a video memory, the processing time is tens or thousands of times longer than the method of storing and editing as bitmap data. Is required, resulting in a slow drawing speed.

  Also, in the encoding / decoding device of the image display device for binarized image data, the optimization of the reference pattern is determined by changing the reference pattern by cut-and-try and evaluating the compression rate It was a way to do. In other words, it was unclear how much of the set reference pattern contributed to the improvement of the compression ratio.

  In Patent Document 1, compression and decompression are performed by switching a plurality of algorithms according to applications, and the gist of the present invention is different from that of the present invention.

  In view of the above problems, the present invention stores display data to be displayed on a display screen in a storage means (video memory), and performs immediate encoding of image data for the purpose of appropriately changing display contents. In an image display apparatus that performs immediate encoding with a possible run length determination circuit, the number of appearances for the data pattern of all cases of one image data (for example, 256 types for 8-bit data and 16 types for 4-bit data) From the count result of the number of occurrences of the pattern, select a reference pattern as a candidate, actually compress using the selected reference pattern, determine the reference pattern with the best compression rate, By storing the reference pattern unique to the image together with the encoded data in a storage means (video memory), a predetermined pattern (reference) for comparison and reference is stored. The pattern) optimized for each image, and an object thereof is to provide an image display device and an image display method capable of improving the compression rate of image data to be stored in the video memory.

  According to the first aspect of the present invention, image data receiving means for receiving image data and the received image data are divided into a plurality of fixed length data having a predetermined data length, and each fixed length data Data pattern comparing means for determining whether the data pattern and the reference pattern match, and outputting true (1) as a comparison result when it is determined to match, and false (0) as a comparison result otherwise; A determination unit that determines whether or not true continues among the data pattern comparison results of a plurality of fixed-length data output from the data pattern comparison unit, or whether the true exists alone; and the reference pattern A reference pattern switching means for changing the contents of a predetermined reference pattern to be compared and referenced using the register for setting the reference pattern, and the reference Using the reference pattern set by the turn switching means, a data pattern appearance number counting means for counting the number of appearances for the data patterns of all cases of one image data, and from the result of counting the pattern appearance number, A reference pattern selection means for selecting a reference pattern, a data compression means for actually compressing using the reference pattern selected by the reference pattern selection means, and a compression rate based on the result of compression by the compression means A reference pattern determining means for determining the best reference pattern, a means for storing a reference pattern optimized for each image data using the reference pattern determining means, together with image data, and storing in the image data storing means Image display device comprising image display means for displaying stored image data Characterized in that it was.

  According to a second aspect of the present invention, the image data storage means converts each fixed-length data determined to have the true number of times consecutively or singly based on the determination result of the determination means into the same data pattern. The image display device according to claim 1, wherein the image display device stores the run length codes as a series.

  According to a third aspect of the present invention, the image data storage means is the image display device according to the first or second aspect, which comprises only a combinational circuit.

  The invention according to claim 4 is stored in the image data receiving means for receiving the image data, the image data storing means for encoding and storing the image data received by the image data receiving means, and the image data storing means. Image display means for decoding and displaying the image data, and dividing the image data into a plurality of fixed length data of a predetermined data length, and the data pattern of each fixed length data and the predetermined reference pattern match A data pattern comparison unit that outputs true (1) as a comparison result when it is determined that they match, and false (0) as a comparison result otherwise, and a plurality of data pattern output from the data pattern comparison unit A determination means for determining whether or not true continues among the comparison results of data patterns of fixed-length data, or whether or not true exists alone; When the means determines that the true value exists several times continuously or singly in the comparison result output by the data pattern comparing means, the image data storage means determines that the true value exists several times continuously or singly. In addition, a method for storing each fixed length data as a run-length code that is a series of the same data pattern only by a combinational circuit and a register for setting a reference pattern in the data pattern comparison unit are provided for comparison reference. A means for changing the content of the predetermined reference pattern, a means for providing a reference pattern switching function, counting the number of appearances of patterns in all cases, and selecting a reference pattern as a candidate from the counting result, Perform actual compression using the selected reference pattern, determine the reference pattern with the best compression rate, Characterized in that the image display and means for storing together with data optimized reference pattern.

  According to a fifth aspect of the present invention, an image data receiving step for receiving image data, and the received image data are divided into a plurality of fixed length data having a predetermined data length. A data pattern comparing step of determining whether the data pattern and the reference pattern match, and outputting true (1) as a comparison result when it is determined to match, and false (0) as a comparison result otherwise; Among the comparison results of the data patterns of a plurality of fixed length data output from the pattern comparison step, a determination step for determining whether or not true is continuous, or whether true is present alone, and the reference pattern A reference pattern switching step for changing the contents of a predetermined reference pattern for comparison and reference using a register to be set; and a reference pattern set by the reference pattern switching step. A data pattern appearance count counting step for counting the number of appearances for the data patterns of all cases of one image data, and a reference pattern for selecting candidate reference patterns from the result of counting the number of pattern appearances A selection step, a data compression step for actually compressing using the reference pattern selected in the reference pattern selection step, and a reference pattern with the best compression ratio are determined based on the result of compression in the compression step. A reference pattern determining step, a step of storing a reference pattern optimized for each image data together with image data using the reference pattern determining step, and an image for displaying image data stored in the image data storing step An image display method comprising a display step.

  According to a sixth aspect of the present invention, in the image data storing step, each fixed length data determined that the true exists several times continuously or independently based on a determination result of the determination step is stored in the same data pattern. 6. The image display method according to claim 5, wherein the image display method stores the run-length codes as a series.

  A seventh aspect of the invention is characterized in that the image data storing step is the image display method according to the fifth or sixth aspect, wherein the image data storing step is performed only by a combinational circuit.

  According to the present invention, the display data to be displayed on the display screen is stored in the video memory, and the display screen is provided with a run length determination circuit capable of immediately encoding the image data for the purpose of changing the display contents as appropriate. In the image display device that uses the data of the video memory by appropriately encoding the data to be displayed in the video memory and storing it in the video memory, and changing the display contents as appropriate, all the data patterns of one image data are used. Count the number of appearances, select candidate reference patterns from the count results of pattern appearances, perform actual compression using the selected reference patterns, and determine the reference pattern with the best compression rate Then, by storing the reference pattern specific to the image together with the encoded data in the storage means (video memory), a predetermined pattern (reference) Optimize turn) for each image to improve the compression ratio of the image data stored in the video memory. Therefore, the video memory capacity can be reduced.

  In one embodiment of the image display device according to the present invention, image data receiving means for receiving image data, the received image data is divided into a plurality of fixed length data having a predetermined data length, A data pattern that determines whether the data pattern of each fixed-length data matches the reference pattern, and outputs true (1) as a comparison result when it is determined that they match, and false (0) as a comparison result otherwise. A determination unit that determines whether or not true continues among the data pattern comparison results of a plurality of fixed-length data output from the comparison unit and the data pattern comparison unit, or whether true exists alone And a reference pattern cut-off for changing the content of a predetermined reference pattern for comparison and reference using the register for setting the reference pattern and the register for setting the reference pattern. Means, a data pattern appearance number counting means for counting the number of appearances for the data patterns of all cases of one image data using the reference pattern set by the reference pattern switching means, and counting the number of pattern appearances From the results, reference pattern selection means for selecting candidate reference patterns, data compression means for actually compressing using the reference patterns selected by the reference pattern selection means, and results compressed by the compression means A reference pattern determining means for determining a reference pattern with the best compression ratio, a means for storing a reference pattern optimized for each image data together with image data using the reference pattern determining means, and the image data Image display means for displaying image data stored in the storage means And wherein the Rukoto. According to this embodiment, the compression rate of the image data stored in the video memory included in the image display device is improved, and the video memory capacity can be reduced.

  An embodiment to which the present invention is applied will be described below in detail with reference to FIGS. The screen size of the VGA display screen is horizontal 640 dots and vertical 480 dots, but in this embodiment, the data width handled at one time (data of one horizontal line) is 64 bits and the minimum unit of encoding is 8 bits in order to simplify the description. And

  FIG. 20 is a block diagram illustrating the overall configuration of the image display apparatus according to the present embodiment. FIG. 1 is a diagram showing the line buffer of this embodiment. FIG. 2 is a diagram showing data pattern comparison means (pattern comparator) of the present embodiment. It is assumed that the image data encoding method of the image display apparatus of this embodiment encodes data for one horizontal line at a time.

  Image data drawn by an external host CPU (central processing unit) by software processing of the image display device is temporarily stored in a 64-bit line buffer 2209 shown in FIG. Image data of one horizontal line is divided into 8 bits, which is the minimum unit of encoding, and is connected in parallel to the pattern comparator shown in FIG. 2 as LD1, LD2,.

  In this embodiment, four types of pattern comparators 201 to 204 are used. As an example of the operation explanation, based on the pattern set in the reference pattern register 2212, the pattern comparator 201 compares with a pattern in which all 8 bits are 0, the pattern comparator 202 compares with a pattern with all 1, and the pattern comparator 203 has It is assumed that the comparison with the 10 repeated patterns and the pattern comparator 204 compare with the 01 repeated pattern.

  The outputs PC01 to PC08, PC11 to PC18, PC21 to PC28, and PC31 to PC38 of the pattern comparators 201 to 204 are true (1) when all the input data patterns match the reference pattern, and false otherwise ( 0).

  The output of the pattern comparator is connected to the run length determination preprocessing unit 2201 in FIG. 3 to 6 show circuits of the run length determination preprocessing unit of the present embodiment. The run length determination pre-processing unit in FIG. 3 inputs comparison results PC01 to PC08 with reference patterns of all zeros. The run length determination pre-processing unit in FIG. 4 inputs the comparison results PC11 to PC18 with all 1 reference patterns. The run length determination pre-processing unit in FIG. 5 inputs comparison results PC21 to PC28 with 10 repeated reference patterns. The run length determination pre-processing unit in FIG. 6 inputs comparison results PC31 to PC38 with a reference pattern of 01 repetition.

  As shown in FIGS. 3 to 6, the run length determination preprocessing unit takes an AND (logical product) of the comparator outputs of adjacent rows, and ANDs the adjacent outputs of the AND outputs. The AND circuit decreases by 1 every time one stage is advanced, and finally, one AND output RL801 to RL831 is obtained. In this embodiment, the circuits as shown in FIGS. 3 to 6 are referred to as a converged chain type AND circuit.

  The output of the pattern comparator and the AND output of each stage means that there is a series (run) of the same data pattern, but in the stage of FIGS. The run length cannot be determined.

  The output of the pattern comparator signifying the presence of a run and the AND output of each stage of FIGS. 3 to 6 obtained as described above are input to the run length determination circuit 2202 of FIG. 7 to 10 are diagrams showing the internal circuit configuration of the run length determination circuit 2202. The run length determination circuit of FIG. 7 receives signals 2L01 to 2L07, 3L01 to 3L06, 4L01 to 4L05, 5L01 to the comparison outputs PC01 to PC08 with all 0 reference patterns and output from the preprocessing unit of FIG. This circuit inputs 5L04, 6L01 to 6L03, and 7L01 to 7L02. Similarly, the other three types of pre-processing unit outputs are provided with run length determination circuits as shown in FIGS.

  The run length determination circuit 2202 determines how many times the coincidence output of the same pattern continues from the input signal indicating the presence of the run. This determination is performed by determining a portion that is true alone, and basically the same pattern (run) of interest in a 3-input AND circuit is true and the same when an adjacent run is false. The run length (run length), which is a series of patterns, is determined.

  The run length determination outputs RL101 to RL131, RL201 to RL231, RL301 to RL331, RL401 to RL431, RL501 to RL531, RL601 to RL631, RL701 to RL731, and the outputs RL801 to RL831 of FIGS. Eye run length determination result ”.

  Similarly, RL102 to RL132, RL202 to RL232, RL302 to RL332, RL402 to RL432, RL502 to RL532, RL602 to RL632, RL702 to RL732 are referred to as “run length determination result of the second row”, RL103 to RL133, RL203 to RL233, RL303 to RL333, RL403 to RL433, RL503 to RL533, and RL603 to RL633 are set as “run length determination result in the third row”.

  Similarly, RL104 to RL134, RL204 to RL234, RL304 to RL334, RL404 to RL434, and RL504 to RL534 are referred to as “run length determination result in the fourth row”, RL105 to RL135, RL205 to RL235, RL305 to RL335, and RL405 to RL405. The RL 435 is set to “run length determination result on the fifth row”.

  Similarly, RL 106 to RL 136, RL 206 to RL 236, and RL 306 to RL 336 are “run length determination results on the sixth row”, RL 107 to RL 137, and RL 207 to RL 237 are “run length determination results on the seventh row”, RL 108 to RL 138. Is the “run-length determination result on the eighth line”.

  There is no run-length determination output that is true at the same time among the “run-length determination results for any row”, and the “run-length determination results for the same row” for the other three types of pattern comparator outputs are also true at the same time. It will never be. That is, if the only run-length decision output in the only kind of any row is true, or if that row is not included in any kind of run-length, the decision results are all false. In this way, the run length is determined.

  The case where the line is not included in the run length is a case where all kinds of pattern comparator outputs related to the line are false. The data not belonging to the code represented by the run length corresponds to, for example, the case where the pattern comparator outputs PC01, PC11, PC21, and PC31 of LD1 are all false, that is, the image data of LD1 does not match any reference pattern. In this embodiment, such image data is directly stored in the video memory as bitmap data.

  The run length determination output thus obtained is connected to the code determination circuit 2204 and the blank row determination circuit 2205 in FIG.

A BM determination circuit 2203 shown in FIG. 20 is provided for the purpose of detecting bitmap data.
FIG. 15 shows the internal circuit. For example, BM1 becomes true when the first row is bitmap data.

  BM1 to BM8 correspond to each row of the run length determination result. For example, when BM1 is true, all the run length determination results of the first row are false, and any of the run length determination results of the first row is When true, BM1 is false. Therefore, when BM1 is true, the data in LD1 is stored as it is in the video memory as bitmap data.

  In this embodiment, a code representing a run length (run length code) and data for identifying bitmap data are added to the MSB by 1 bit. Therefore, the data to be stored is 9 bits in each row. This identification data is added to the output of the code determination circuit 2204 by the identification data addition circuit 2213. Outputs BM1 to BM8 of the BM determination circuit 2203 are connected to the identification data addition circuit 2213. For example, when BM1 is true, “1” is added to the MSB side of the data of LD1. When BM1 is false, “0” is added to the MSB side of the run length code.

  When data LDj corresponding to an arbitrary j-th line is included in the run-length determination result of a higher-order line, all of the run-length determination result of j line and BMj are false, and there is no code corresponding to j-line. It will be. In this way, only the codes of the lines having run lengths and the lines having bitmap data are added with the identification data and stored in the video memory.

  As a result of encoding in this way, it is not determined how many bytes of data to store, and therefore, bitmap data and run-length codes must be extracted every time a blank line is excluded at the stage of encoding. For this purpose, a signal indicating the distribution of blank rows is connected to the code determination circuit 2204 in FIG.

  First, the output of the run length determination circuit 2202 in FIG. 20 is connected to the blank row determination circuit 2205. The blank row determination circuit 2205 is configured as shown in FIGS. 11 to 14 and FIG. 16, and connects the output of the run length determination circuit 2202 to the circuits shown in FIGS. The outputs of the circuits in FIGS. 11 to 14 are true when a run-length code exists in each row. The outputs of FIGS. 11 to 14 are connected to the circuits of FIG. Further, outputs BM1 to BM8 of the BM determination circuit 2203 are also connected to the respective circuits in FIG.

  The outputs nBMRL2 to nBMRL8 in FIG. 16 are true when there is no run-length code in each row and the data in that row is not bitmap data. That is, the line is included in the upper run-length code and is blank. When nBMRL2 to nBMRL8 is false, it means that run-length code or bitmap data exists in the row.

Next, the outputs nBMRL2 to nBMRL8 in FIG. 16 are connected to the blank run length determination preprocessing unit 2206 in FIG. The circuit configuration of the blank run length determination preprocessing unit 2206 is shown in the converged chain logical product circuit in FIG. 17 and the converged chain logical sum circuit in FIG.
The output in FIG. 17 means that there is a series of blanks (runs) as in the run length determination preprocessing unit 2201. This output is connected to the blank run length determination circuit 2207 of FIG.

  In the output of FIG. 19, NCOR 22 indicates that there are blanks in the second and third lines. Similarly, NCOR32 has 2-4 lines, NCOR42 has 2-5 lines, NCOR52 has 2-6 lines, NCOR62 has 2-7 lines, and NCOR72 has 2-8 lines. Yes. These outputs are connected to the code determination circuit 2204 in FIG.

  The blank run length determination circuit 2207 is a circuit as shown in FIG. 18 and, like the run length determination circuit 2202, determines how many times the blank continues from the input signal indicating the presence of the blank run. Is.

  Next, the output of the blank row determination circuit 2205, the output of the blank run length determination preprocessing unit 2206, and the output of the blank run length determination circuit 2207 are connected to the blank number determination circuit 2208 of FIG. Perform the processing necessary to confirm. The blank number determination circuit 2208 is configured as shown in FIGS.

  The blank number determination circuit 2208 outputs signals NCODE3_1 to NCODE7_6 indicating how many blanks exist from the second line to the corresponding line. For example, NCODE3_1 means that only one blank exists by the third line, and NCODE7_6 indicates that six blanks exist by the seventh line.

  FIG. 21 is a logic circuit NCODE3SEL (2301) for determining signals NCODE3_1 and NCODE3_2 representing blanks up to the third row and its truth table. Here, among the signals input to the NCODE3SEL (2301), NCODE2_1 has the same meaning as nBMRL2. That is, this signal indicates that there is only one blank before the second line.

  FIG. 22 is a logic circuit NCODE4SEL (2401) for determining signals NCODE4_1, NCODE4_2, and NCODE4_3 representing blanks up to the fourth row and its truth table. FIG. 23 shows the signals NCODE5_1, NCODE5_2, NCODE5_3 and NCODE5_4 representing the blanks up to the fifth line and the logic circuit NCODE5SEL (2501) for determining the truth table.

  FIG. 24 shows signals NCODE6_1 to NCODE6_5 representing blanks up to the sixth line and a logic circuit NCODE6SEL (2601) for determining a truth table. FIG. 25 shows signals NCODE7_1 to NCODE7_6 representing blanks up to the seventh line and a logic circuit NCODE7SEL (2701) for determining a truth table.

  The code determination circuit 2204 in FIG. 20 includes outputs of the line buffer 2209, the BM determination circuit 2203, the run length determination circuit 2202, the blank row determination circuit 2205, the blank run length determination preprocessing unit 2206, and the blank number determination circuit 2208 described above. Enter.

  In addition, the code register 2210 inputs code conversion setting data (all0rl1 to all0rl8, all1rl1 to all1rl8, all2rl1 to all2rl8, all3rl1 to all3rl8) that are input and controlled from the outside to obtain encoded data CODE1 to CODE8. . The code determination circuit 2204 of this embodiment is configured as shown in FIGS.

  FIG. 26 shows logic circuits (ENCODE1SEL (2801) and ENCODE1LATCH (2802)) for determining CODE1, and FIG. 27 is a truth table thereof. FIG. 28 is a logic circuit (ENCODE5SEL (3001) and ENCODE5LATCH (3002)) for determining CODE5, and FIG. 29 is a truth table thereof. FIG. 30 is a logic circuit (ENCODE8SEL (2901) and ENCODE8LATCH (2902)) for determining CODE8, and FIG. 31 is a truth table thereof. The circuits for determining CODE2 to CODE4, CODE6 and CODE7 are the same as those shown in FIGS.

  Next, the reference pattern switching circuit 2217 has a function of automatically switching the reference pattern to automate the optimization of the reference pattern. When storing new image data, the external host CPU sets the reference pattern optimization mode by software processing. In the reference pattern optimization mode, all data patterns included in one image data are counted for all cases.

  Further, in order to realize the effect of the present invention, a data pattern appearance number counter 2218 and a data pattern appearance number register 2219 are provided. When the data to be compared is 8 bits, there are 256 types of patterns, but four types are set in the reference pattern register 2212 and counted by the data pattern appearance count counter 2218.

  When the data pattern of the received data matches the reference pattern, the signals PC01 to PC08, PC11 to PC18, PC21 to PC28, and PC31 to PC38 output from the pattern comparator 2211 are counted by the data pattern appearance counter 2218. The value counted by the data pattern appearance number counter 2218 is stored in the data pattern appearance number register 2219.

  Further, a stored data number calculation circuit 2215 and a stored data number register 2216 are provided, and identification data is added to the encoded data CODE1 to CODE8, which is the output of the code determination circuit 2204, by the identification data adding circuit 2213, and the video memory Data stored in 2214 is input, and the number of data is input to the stored data number calculation circuit 2215. The stored data number calculation circuit 2215 calculates the number of stored data from the compressed code, and stores the number of stored data for each pattern in the stored data number register 2216.

  The data pattern having the largest number of appearances stored in the data pattern appearance number register 2219 is set in the reference pattern register 2212 as a reference pattern in order, and the combination that minimizes the number of compressed data is selected from the result of the stored data number calculation circuit 2215. To do. When the reference pattern optimization process is completed, an interrupt signal is generated for the external host CPU, and the reference pattern optimization mode is terminated.

  Based on this interrupt signal, the host CPU recognizes that the reference pattern has been determined, and starts the writing operation of the corresponding image data in the normal editing mode. When storing the image data, the identification data adding circuit 2213 adds the reference pattern determined this time together with the image data identification code as a header of the image data.

  When data is read from the video memory, first, a reference pattern is fetched from the header of the image data and decoding processing is performed. When further editing and storing, encoding processing is performed using the reference pattern fetched in the reference pattern register 2212, and the encoded data is stored in the video memory.

  In this embodiment, 8-byte display data is pattern-compared and encoded in 8-bit units. However, data for one line is set to 128 bits, 256 bits, or the number of other bits, or the minimum encoding unit is 4 bits, 16 bits, Even if the number of bits is 32 bits or any other number, encoding can be performed in exactly the same manner. It is necessary to optimize the number of bits for one line and the minimum number of bits for encoding according to the configuration of the video memory, the editing method (access method from the host CPU), or the characteristics of the display data to be handled.

  In this embodiment, the case where the encoding / decoding method of the display image data is applied to the image display device has been described. However, the present invention is not limited to this, and image processing of other image processing devices and image forming devices is performed. The present invention may also be applied to encoding / decoding of image data at the time of image formation.

It is a figure which shows the structure of the line buffer of a present Example. It is a figure which shows the structure of the pattern comparator of a present Example. It is a figure which shows the circuit of the run length determination pre-processing part of a present Example. It is a figure which shows the circuit of the run length determination pre-processing part of a present Example. It is a figure which shows the circuit of the run length determination pre-processing part of a present Example. It is a figure which shows the circuit of the run length determination pre-processing part of a present Example. It is a figure which shows the internal circuit structure of the run length determination circuit of a present Example. It is a figure which shows the internal circuit structure of the run length determination circuit of a present Example. It is a figure which shows the internal circuit structure of the run length determination circuit of a present Example. It is a figure which shows the internal circuit structure of the run length determination circuit of a present Example. It is a figure which shows the blank line determination circuit of a present Example. It is a figure which shows the blank line determination circuit of a present Example. It is a figure which shows the blank line determination circuit of a present Example. It is a figure which shows the blank line determination circuit of a present Example. It is a figure which shows the bitmap determination circuit of a present Example. It is a figure which shows the blank line determination circuit of a present Example. It is a figure which shows the circuit of the blank run length determination pre-processing part of a present Example. It is a figure which shows the blank run length determination circuit of a present Example. It is a figure which shows the circuit of the blank run length determination pre-processing part of a present Example. It is a block diagram which shows the whole structure of the image display apparatus of a present Example. It is a figure which shows the structure and truth table of internal circuit NCODE3 SEL which investigates the blank to the 3rd line which concerns on a present Example. It is a figure which shows the structure and truth table of internal circuit NCODE4 SEL which investigates the blank to the 4th line which concerns on a present Example. It is a figure which shows the structure and truth table of internal circuit NCODE5 SEL which investigates the blank to the 5th line which concerns on a present Example. It is a figure which shows the structure and truth table of internal circuit NCODE6 SEL which investigates the blank to the 6th line concerning a present Example. It is a figure which shows the structure and truth table of internal circuit NCODE7 SEL which investigates the blank to the 7th line concerning a present Example. It is a figure which shows the internal circuit ENCODE1 SEL which determines CODE1 which concerns on a present Example, and ENCODE1 LATCH. FIG. 27 is a diagram showing a truth table of an internal circuit ENCODE1 SEL for determining CODE1 of FIG. 26 according to the present embodiment. It is a figure which shows the internal circuit ENCODE5 SEL which determines CODE5 based on a present Example, and ENCODE5 LATCH. It is a figure which shows the truth table of internal circuit ENCODE5 SEL which determines CODE5 which concerns on a present Example. It is a figure which shows the internal circuit ENCODE8 SEL which determines CODE8 which concerns on a present Example, and ENCODE8 LATCH. It is a figure which shows the truth table of internal circuit ENCODE8 SEL which determines CODE8 which concerns on a present Example.

Claims (6)

Image data receiving means for receiving image data;
The received image data is divided into a plurality of fixed length data having a predetermined data length, and it is determined whether or not the data pattern of each fixed length data matches the reference pattern, and it is determined that they match. Data pattern comparing means for outputting true (1) as a comparison result and false (0) as a comparison result in other cases;
Among the comparison results of the data patterns of a plurality of fixed-length data output from the data pattern comparison means, determination means for determining whether or not true is continuous, or whether true is present alone,
A register for setting the reference pattern;
Reference pattern switching means for changing the content of a predetermined reference pattern for comparison and reference using a register for setting the reference pattern;
A data pattern appearance number counting unit that counts the number of appearances for the data patterns of all cases of one image data using the reference pattern set by the reference pattern switching unit;
Reference pattern selection means for selecting a reference pattern as a candidate from the counting result of the number of pattern appearances;
Data compression means for actually compressing using the reference pattern selected by the reference pattern selection means;
A reference pattern determining means for determining a reference pattern having the best compression rate based on the result of compression by the compression means;
Means for storing a reference pattern optimized for each image data together with encoded image data using the reference pattern determining means;
An image display device comprising: image display means for decoding and displaying the encoded image data stored in the image data storage means.   The image data storage means, based on the determination result of the determination means, each fixed-length data determined to be true several times continuously or singly as a run-length code that is a series of the same data pattern. The image display device according to claim 1, wherein the image display device is stored.   3. The image display device according to claim 2, wherein the image data storage means performs the processing according to claim 2 performed by the means only by a combinational circuit. An image data receiving process for receiving image data;
The received image data is divided into a plurality of fixed length data having a predetermined data length, and it is determined whether or not the data pattern of each fixed length data matches the reference pattern, and it is determined that they match. A data pattern comparison step of outputting true (1) in the case, false (0) in the other cases as a comparison result;
Among the comparison results of the data patterns of a plurality of fixed-length data output from the data pattern comparison step, a determination step of determining whether true is continuous or whether true is present alone,
A reference pattern switching step of changing the content of a predetermined reference pattern to be compared and referenced using a register for setting the reference pattern,
Using the reference pattern set by the reference pattern switching step, a data pattern appearance number counting step for counting the number of appearances for the data pattern of all cases of one image data,
From the counting result of the pattern appearance frequency, a reference pattern selection step of selecting a candidate reference pattern,
A data compression step of actually compressing using the reference pattern selected by the reference pattern selection step;
A reference pattern determining step for determining a reference pattern having the best compression rate based on the result of compression by the compression step;
Storing the reference pattern optimized for each image data together with the encoded image data using the reference pattern determination step;
An image display method comprising: an image display step of decoding and displaying the encoded image data stored in the image data storage step.   In the image data storage step, each fixed length data determined to have the true number of times continuously or independently based on the determination result of the determination step is used as a run-length code that is a series of the same data pattern. 5. The image display method according to claim 4, wherein the image is stored.   6. The image display method according to claim 5, wherein in the image data storing step, the processing according to claim 2 performed by the step is performed only by a combinational circuit.

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