JP2005136475A - Method and apparatus of data transmission - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and an apparatus of data transmission which are capable of transmission of additional information by utilizing a change in duty ratio in addition to the transmission of a primary original signal without causing deterioration in transmission quality. <P>SOLUTION: The duty ratio of the primary original signal to be transmitted is changed by a quantity corresponding to "1" or "0" of the additional data so that the change in duty ratio comes within a range permitted by digital audio interface standards equivalent to the standards of transmission system of the original signal, for example, IEC 958, and the additional data are transmitted together with the original signal from a transmitter side to a receiver side. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data transmission method and apparatus capable of transmitting additional information in addition to original original information.

  Conventionally, the basic design was to set the duty ratio of the digital signal to 50% as much as possible. However. In various devices and various standards that handle digital signals, the duty ratio of the digital signals is not necessarily 50%.

As a standard for handling such a digital signal, for example, there is a digital audio interface equivalent to IEC958 (for example, see Non-Patent Document 1).
In this standard, the duty cycle rate ranges from 40% to 60% when the data bit is logically “1”, and 45% to 55% when two data bits are logically “0” in succession. It must be within range.
Japan Electronic Machinery Association Standard, EIAJ CP-1201

  Such conventional data transmission methods and apparatuses are accompanied by the following disadvantages. For example, when a digital signal is handled in accordance with a digital audio interface standard equivalent to IEC 958, the waveform level, time axis, and duty ratio are required to be within the standard range. Increasing the possibility that elements such as the time axis and the duty ratio deviate from the allowable range of the standard causes deterioration in transmission quality such as an increase in error rate when transmitting a digital signal. For this reason, a data transmission method and apparatus for transmitting data by adding information to the duty ratio have not been devised.

  The present invention has been made in view of such circumstances, and enables transmission of additional information using a change in duty ratio in addition to the original original signal without causing deterioration in transmission quality. It is an object to provide a data transmission method and apparatus.

  In order to achieve the above object, a data transmission method according to the present invention is a data transmission method for transmitting additional data together with an original signal to be transmitted, wherein a duty ratio of the original signal is set according to the additional data. The additional data is reproduced from the amount of change in the duty ratio of the original signal on the receiving side.

  In order to achieve the above object, an apparatus according to the present invention is a data transmission apparatus that transmits additional data together with an original signal to be transmitted, the duty ratio of the original signal being an amount corresponding to the additional data, A duty modulation means for changing, and a transmission means for transmitting the original signal in which the duty modulation means changes an amount duty ratio according to the additional data.

  In order to achieve the above object, an apparatus according to the present invention is a data transmission apparatus that receives additional data together with an original signal to be transmitted, the receiving means receiving the original signal, and the receiving means receiving the data. Detecting means for detecting a change in duty ratio with respect to a duty ratio reference value of the original signal, and determining means for determining the additional data according to the change in the duty ratio based on a detection result of the detecting means; It is provided with.

  As is clear from the above description, the data transmission method and apparatus according to the present invention changes the duty ratio of the original signal by an amount corresponding to the additional data, and transmits the duty ratio of the original signal on the receiving side. Since the additional data is reproduced from the change amount of the ratio, it is possible to transmit the additional information using the change of the duty ratio in addition to the original original information without deteriorating the transmission quality.

  The purpose of enabling transmission of additional information by using a change in the duty ratio in addition to the original original information without degrading the transmission quality, and changing the duty ratio of the original signal according to the additional data This is realized by reproducing the additional data from the amount of change in the duty ratio of the original signal.

  Also, the purpose of enabling transmission of additional information using the change of the duty ratio in addition to the original original information without degrading the transmission quality, the duty ratio of the original signal according to the additional data This is realized by including a duty modulation means for changing the quantity and a transmission means for sending the original signal in which the duty modulation means changes the quantity duty ratio according to the additional data.

  The receiving means for receiving the original signal and the reception for the purpose of enabling transmission of additional information by utilizing the change of the duty ratio in addition to the original original information without causing deterioration of the transmission quality Detecting means for detecting a change in the duty ratio with respect to a duty ratio reference value of the original signal received by the means, and determining the additional data according to the change in the duty ratio based on a detection result of the detecting means This is realized by providing a judging means.

  In the standard of the digital audio interface equivalent to IEC958, the time axis standard in the format is normally allowed up to about ± 32 nsec when the sampling frequency is 48 KHz, and the change of the duty ratio in this range is not a problem. The tolerance for the duty ratio when the sampling frequency is 48 KHz is ± about 10% in the case of 64 Fs (64 times the sampling frequency).

In the additional data transmission apparatus to which the data transmission method of the first embodiment is applied, digital signals are handled according to the digital audio interface standard equivalent to IEC958.
FIG. 1 is a block diagram showing the configuration of an additional data transmission apparatus on the transmission side to which the data transmission method of the first embodiment is applied. This additional data transmission apparatus includes an original signal output unit 1, an additional data modulation unit (duty modulation means) 2, a low-pass filter circuit 3, a mixer circuit (duty modulation means) 4, and an amplifier (transmission means) 5.

  The original signal output unit 1 outputs the original information to be transmitted, that is, the original signal A. The duty ratio of the original signal A is within the tolerance range based on the duty ratio of 50%, which is allowed by the digital audio interface standard equivalent to IEC958.

  The additional data modulation unit 2 outputs additional data for modulating the original signal A. In particular, at the time of a high transfer rate, since it is necessary to synchronize the additional data with the original signal A, the synchronization signal of the original signal A extracted by the original signal output unit 1 is necessary.

The low-pass filter circuit 3 blocks the high-frequency component of the original signal A output from the original signal output unit 1 while allowing the low-frequency component to pass therethrough and causes the signal waveform of the original signal A to rise and fall. Slow change. The mixer circuit 4 mixes the original signal B output from the low-pass filter circuit 3 and delayed in rising and falling with the additional data signal C output from the additional data modulator 2. The original signal D in which the duty ratio is modulated by the additional data signal C is output. The amplifier 5 amplifies the original signal D output from the mixer circuit 4 and outputs it as a signal E. The signal E has a duty ratio modulated by the additional data signal C. For example, “1” of the additional data corresponds to a state where the duty ratio is 50% or more, and “0” of the additional data corresponds to a state where the duty ratio is less than 50%. It is a thing.
In this case, the change in the duty ratio is within the range allowed by the standard of the digital audio interface equivalent to IEC958. The upper limit in the allowable range is in a state where the duty ratio is 50% or more and corresponds to “1” of the additional data, and the lower limit in the allowable range is in a state where the duty ratio is less than 50% and the additional data Corresponding to “0”.

FIG. 3 is a block diagram showing a configuration of a receiving side additional data transmission apparatus to which the data transmission method of the first embodiment is applied. This additional data transmission apparatus includes a first low-pass filter circuit (receiving means) 11, a waveform correction circuit (duty ratio reference value generation means, waveform correction means) 12, and a second low-pass filter circuit (duty ratio reference value generation means). 13, a comparator (detection means, determination means) 14, and an original signal receiving device 15. The case where the receiving side additional data transmission apparatus shown in FIG. 3 is applicable is that the transfer rate of the additional data is low and the original signal is a high-frequency signal having a high transfer rate.
Since the original signal of the received signal E is a high frequency, the first low-pass filter circuit 11 cuts off the original signal and allows low-frequency additional data with a low transfer rate to pass, and according to the additional data. A signal F whose level varies is output.
The waveform correction circuit 12 is a circuit that corrects the waveform to a duty ratio of 50% when the duty ratio is 50% or more and less than 50% included in the signal waveform of the received signal E. The second low-pass filter circuit 13 is a circuit that generates and outputs a reference signal H based on the waveform-corrected signal G output from the waveform correction circuit 12.
The comparator 14 compares the signal F with the reference signal H, and outputs additional data included in the received signal E. The original signal receiving device 15 is a circuit that receives the original signal A output from the original signal output unit 1 on the transmission side shown in FIG. 1 on the basis of the waveform-corrected signal G.

Next, the operation of the additional data transmission apparatus according to the first embodiment will be described.
2 is a timing chart showing the operation of the transmission side additional data transmission apparatus shown in FIG. 1, and FIG. 4 is a timing chart showing the operation of the reception side additional data transmission apparatus shown in FIG. The operation will be described below with reference to these timing charts.
The original signal A output from the original signal output unit 1 passes through the low-pass filter circuit 3, and the original signal shown in FIG. B is output to the mixer circuit 4. The mixer circuit 4 mixes the original signal B output from the low-pass filter circuit 3 whose change at the rising and falling time is delayed with the additional data signal C output from the additional data modulation unit 2. The original signal D, the duty ratio of which is modulated by the additional data signal C, is output to the amplifier 5. The amplifier 5 amplifies the original signal D output from the mixer circuit 4 and outputs the amplified signal D as a signal E shown in FIG. 2 (e) to the additional data transmission apparatus on the receiving side shown in FIG. In the signal E, the duty ratio of the original signal is modulated by the additional data signal C. For example, “1” of the additional data is set to a state where the duty ratio of the original signal is 50% or more, and “0” of the additional data is set to the duty. This corresponds to a state of less than 50%.

  In the additional data transmission apparatus on the reception side, the original signal, which is a high frequency signal, is blocked by the first low-pass filter circuit 11 with respect to the received signal E, and is shifted from the reference center value to plus or minus according to the additional data. A signal F is generated and input to the non-inverting terminal of the comparator 14. This signal F is a signal in which the direct current level fluctuates from the reference center value to plus or minus corresponding to a state where the duty ratio of the original signal is 50% or more or less than 50%.

  The received signal E is also supplied to the waveform correction circuit 12, and the waveform correction circuit 12 performs a duty ratio on the original signal having a duty ratio of 50% or more and a duty ratio of less than 50%. A waveform correction process is executed to set the value to 50%. The signal G subjected to the waveform correction processing so that the duty ratio becomes 50% is supplied to the second low-pass filter circuit 13 and the original signal receiving device 15.

  The second low-pass filter circuit 13 integrates the signal G that has been subjected to the waveform correction processing, generates a reference signal H when the duty ratio is maintained at 50%, and outputs it to the inverting terminal of the comparator 14. To do. As shown in FIG. 4D, the signal H is a signal indicating a direct current level corresponding to an original signal with a duty ratio of 50% output from the original signal output unit 1.

The comparator 14 compares the signal F with the signal H, and the section in which the level of the signal F is higher than the level of the signal H (in the section where the duty ratio of the original signal is 50% or more). Yes, section indicating additional data “1”), “1” as additional data
Is output. Further, a section in which the level of the signal F is smaller than the level of the signal H (a section in which the duty ratio of the original signal is less than 50%, a section indicating the additional data “0”), additional data "0" is output.

  As described above, according to the first embodiment, when the duty ratio of an original signal to be originally transmitted is defined as 50% within a predetermined tolerance, the duty ratio is set to “1” of additional data or An amount corresponding to “0” is changed so that the change of the duty ratio falls within a range allowed by the standard of the original signal transmission system, the digital audio interface equivalent to IEC 958, and the original Since the additional data is transmitted from the transmitting side to the receiving side together with the signal, the additional data is transmitted in addition to the original original signal in addition to the original original signal without causing deterioration in transmission quality. There is an effect that it is possible to provide a data transmission method and apparatus.

  In the above description, the change in the duty ratio is within the range allowed by the digital audio interface standard equivalent to IEC 958, and the upper limit within the allowable range is a state where the duty ratio is 50% or more. The additional data corresponds to “1”, and the lower limit within the allowable range is less than 50% of the duty ratio and corresponds to the additional data “0”. The upper limit and the lower limit of the change amount of the duty ratio allowed in the standard applied to the transmission system of the original signal is made to correspond to the number of multilevel levels that the additional data can take, and the original signal The duty ratio of the additional data is changed with respect to an amount and a reference value corresponding to each multi-value level of the additional data, and is transmitted to the receiving side. The amount of change in the duty ratio of the signal is determined by a plurality of detection points corresponding to each multilevel level, and the additional data of the multilevel level is reproduced.

FIG. 5 is a circuit diagram showing the configuration of the additional data transmission apparatus on the transmission side according to the second embodiment. This additional data transmission device on the transmission side includes D flip-flops (duty modulation means) 21, 23, inverter circuits (duty modulation means) 22, 32, an OR circuit (duty modulation means) 24, an OR circuit (transmission means). 33, AND circuits (duty modulation means) 25, 26 and 27, and a synchronization circuit (duty modulation means) 31.
In the D flip-flop 21, the original signal A is input to the data input terminal, and a signal of 1024 Fs (1024 times the sampling frequency) is supplied to the clock input terminal as the clock signal CLK.
In the D flip-flop 23, the output from the Q terminal of the D flip-flop 21 is input to the data input terminal, and the 1024 Fs signal is supplied as the clock signal CLK via the inverter circuit 22.

The OR circuit 24 is a circuit that outputs a logical sum operation result of the original signal A and the output from the Q terminal of the D flip-flop 23 as a signal E.
The AND circuit 25 is a circuit that outputs a logical product operation result of the original signal A and the output from the Q terminal of the D flip-flop 23 as a signal F.
The AND circuit 26 is a circuit that outputs a logical product operation result of the signal E output from the OR circuit 24 and the signal G output from the synchronization circuit 31.
The AND circuit 27 is a circuit that outputs a logical product operation result of the signal F output from the AND circuit 25 and the signal G output from the synchronization circuit 31 input via the inverter circuit 32.

The synchronization circuit 31 is a circuit that outputs a signal G for switching between the signal E and the signal F subjected to duty modulation based on the additional data modulation signal synchronized with the original signal A. This additional data modulation signal is synchronized with the rising or falling timing of the original signal A.
The OR circuit 33 is a circuit that outputs a logical sum operation result of the signal output from the AND circuit 26 and the signal output from the AND circuit 27 as a signal H.

FIG. 7 is a circuit diagram showing a configuration of the additional data transmission device on the receiving side. This additional data transmission device on the reception side includes a waveform correction circuit (waveform correction means) 41, an original reception device 42, a PLL circuit 43, a 16-frequency divider counter (detection means) 44, and a frequency-divide-by-18 counter (detection means). ) 45, 32 frequency division counter (detection means) 46, 34 frequency division counter (detection means) 47, 48 frequency division counter (detection means) 48, 50 frequency division counter (detection means) 49, and judgment circuit (Detection means, determination means) 51 is provided.
The waveform correction circuit 41 is a circuit that performs waveform correction for returning the duty ratio of the received original signal A to 50% because the received original signal A is subjected to duty modulation.
The original receiving device 42 receives the original signal A whose duty ratio is returned to 50%.
The PLL circuit 43 is a circuit that generates a stable 1024 Fs signal from the reference clock signal.

The divide-by-16 counter 44 is a counter that is reset at the rising edge of the received original signal A subjected to duty modulation, and the 1024 Fs signal generated by the PLL circuit 43 is supplied as the clock signal CLK. . Further, a signal B obtained by dividing the input signal, which is the received original signal A subjected to duty modulation, by 16 is output.
The 18 frequency division counter 45 is a counter that is reset at the rising edge of the received original signal A subjected to duty modulation, and the 1024 Fs signal generated by the PLL circuit 43 is supplied as the clock signal CLK. . Also, a signal C obtained by dividing the input signal, which is the received original signal A subjected to duty modulation, by 18 is output.
The divide-by-32 counter 46 is a counter that is reset at the rising edge of the received original signal A subjected to duty modulation, and the 1024 Fs signal generated by the PLL circuit 43 is supplied as the clock signal CLK. . Also, a signal D obtained by dividing the input signal, which is the received original signal A subjected to duty modulation, by 32 is output.
The 34-dividing counter 47 is a counter that is reset at the rising edge of the received original signal A subjected to duty modulation, and the 1024 Fs signal generated by the PLL circuit 43 is supplied as the clock signal CLK. . Further, a signal E obtained by dividing the input signal, which is the received original signal A subjected to duty modulation, by 34 is output.
The 48-frequency division counter 48 is a counter that is reset at the rising edge of the received original signal A subjected to duty modulation, and the 1024 Fs signal generated by the PLL circuit 43 is supplied as the clock signal CLK. . Further, a signal F obtained by dividing the input signal, which is the received original signal A subjected to duty modulation, by 48 is output.
The 50-frequency division counter 49 is a counter that is reset at the rising edge of the received original signal A subjected to duty modulation. The 1024 Fs signal generated by the PLL circuit 43 is supplied as the clock signal CLK. . Also, a signal G obtained by dividing the input signal, which is the received original signal A subjected to duty modulation, by 50 is output.
The determination circuit 51 is a circuit for extracting additional data based on the output of each frequency dividing counter. In the second embodiment, an additional data extraction program is used for extracting additional data.

Next, the operation of the additional data transmission apparatus according to the second embodiment will be described.
6 is a timing chart showing the operation of the transmission-side additional data transmission apparatus shown in FIG. 5, and FIG. 8 is a flowchart showing the operation of the reception-side additional data transmission apparatus shown in FIG. The operation will be described below with reference to these timing charts and flowcharts.
First, the operation of the additional data transmission apparatus on the transmission side will be described. The original signal A shown in FIG. 6A is input to the data input terminal of the D flip-flop 21, and the 1024 Fs signal is input to the clock input terminal as the clock signal CLK. Further, the output of the Q terminal of the D flip-flop 21 is supplied to the data input terminal of the D flip-flop 23, and the signal of 1024 Fs is input to the clock input terminal as the clock signal CLK via the inverter circuit 22. . Accordingly, the D flip-flop 21 reads the original signal A at the rising edge of the clock signal CLK, and outputs the read value from the Q terminal to the D flip-flop 23. The D flip-flop 23 reads the value of the original signal A read by the D flip-flop 21 at the falling edge of the clock signal CLK, and the signal D shown in FIG. Output to the AND circuit 25. In the OR circuit 24, the logical sum of the signal D output from the Q terminal of the D flip-flop 23 and the original signal A is calculated and output as a signal E shown in FIG. In the AND circuit 25, the logical product of the signal D output from the Q terminal of the D flip-flop 23 and the original signal A is calculated and output as the signal F shown in FIG.
Assuming that the duty ratio of the original signal A is 50%, this signal E has a duty ratio that is higher than that of the signal A for a period of one cycle of the 1024 Fs signal input as the clock signal CLK. The signal is 56%.
The signal F is a signal having a duty ratio of 44%, which has a duty ratio smaller than that of the signal A for a period of one cycle of the 1024 Fs signal input as the clock signal CLK.
The signal E and the signal F are switched in accordance with the “High” level or the “Low” level of the signal G shown in FIG. 6G output based on the additional data modulation signal input to the synchronization circuit 31. The signal H is output from the OR circuit 33 as shown in FIG. That is, when the signal G is at “Low” level, the original signal A is duty-modulated to a signal with a duty ratio of 44%, and when the signal G is at “High” level, the original signal A is at a duty ratio of 56%. The signal is duty-modulated and output.

Next, the operation of the additional data transmission apparatus on the receiving side will be described.
In this additional data transmission apparatus on the receiving side, a stable 1024 Fs signal is generated by the PLL circuit 43 from the reference clock signal of the original receiving device 42. This signal is supplied as a clock signal CLK to the 16-frequency divider 44, the 18-frequency divider 45, the 32-frequency counter 46, the 34-frequency counter 47, the 48-frequency counter 48, and the 50-frequency counter 49.

  Since the bi-phase modulation IEC958 is taken as an example in the second embodiment, the width of a signal that can exist is only three types of periods of 128 Fs, 64 Fs, and 128/3 Fs in the “High” period and the “Low” period. Absent. For this reason, in the additional data transmission apparatus on the reception side shown in FIG. 7, the duty ratio is determined from the width of the “High” level of the duty-modulated signal H that is the received input signal. Only three windows corresponding to the three types of periods are divided into 16 division counter 44, 18 division counter 45, 32 division counter 46, 34 division counter 47, 48 division counter 48, 50 division. It is set by the counter 49. That is, the first window is set by software by processing the signal B output from the 16-dividing counter 44, the signal C output from the 18-dividing counter 45, and the original signal A in the flowchart shown in FIG. The The second window is set by software by processing the signal D output from the divide-by-32 counter 46, the signal E output from the divide-by-34 counter 47, and the original signal A in the flowchart shown in FIG. Is done. The third window is set by software by processing the signal F output from the 48-frequency divider 48, the signal G output from the 50-frequency counter 49, and the original signal A in the flowchart shown in FIG. Is done.

According to the flowchart of FIG. 8, first, the 16-frequency dividing counter 44, the 18-frequency dividing counter 45, the 32-frequency dividing counter 46, the 34-frequency dividing counter 47, and the 48-frequency dividing counters 48, 50 according to the rising edge of the received signal H. The frequency dividing counter 49 is reset (step S1).
Next, when the signal B output from the divide-by-16 counter 44 is at "High" level, it is determined whether or not the received signal H is at "Low" level (step S2). As a result of the determination, if the signal H is at the “Low” level, it is determined that the duty ratio of the pulse of the received signal H is less than 50% (below the duty ratio of 44%), and the determination circuit 51 is used as additional data. The “Low” level is output (step S3).

  In step S2, when the signal B is at "High" level and the received signal H is at "High" level, subsequently, when the signal C output from the 18-frequency divider counter 45 is at "High" level. Then, it is determined whether or not the received signal H is at the “Low” level (step S4). As a result of this determination, if the signal H is at the “Low” level, it is determined that the duty ratio of the pulse of the received signal H exceeds 50% (duty ratio exceeds 56%), and the determination circuit 51 The “High” level is output as additional data (step S5).

  In step S4, when the signal C is at "High" level and the received signal H is at "High" level, the signal D output from the divide-by-32 counter 46 is at "High" level. Then, it is determined whether or not the received signal H is at the “Low” level (step S6). As a result of the determination, if the signal H is at the “Low” level, it is determined that the duty ratio of the pulse of the received signal H is less than 50% (below the duty ratio of 44%), and the determination circuit 51 is used as additional data. The “Low” level is output (step S7).

  If the received signal H is at the “High” level when the signal D is at the “High” level in step S6, then, when the signal E output from the 34-dividing counter 47 is at the “High” level, It is determined whether or not the received signal H is at the “Low” level (step S8). As a result of this determination, if the signal H is at the “Low” level, it is determined that the duty ratio of the pulse of the received signal H exceeds 50% (duty ratio exceeds 56%), and the determination circuit 51 The “High” level is output as additional data (step S9).

  In step S8, when the signal E is at "High" level and the received signal H is at "High" level, subsequently, when the signal F output from the 48-frequency division counter 48 is at "High" level. Then, it is determined whether or not the received signal H is at the “Low” level (step S10). As a result of the determination, if the signal H is at the “Low” level, it is determined that the duty ratio of the pulse of the received signal H is less than 50% (below the duty ratio of 44%), and the determination circuit 51 is used as additional data. The “Low” level is output (step S11).

  If the received signal H is at “High” level when the signal F is at “High” level in step S10, then, when the signal G output from the 50-frequency divider counter 49 is at “High” level, It is determined whether or not the received signal H is at the “Low” level (step S12). As a result of this determination, if the signal H is at the “Low” level, it is determined that the duty ratio of the pulse of the received signal H exceeds 50% (duty ratio exceeds 56%), and the determination circuit 51 A “High” level is output as additional data (step S13).

  In step S12, when the signal G is at "High" level and the received signal H is at "High" level, an error flag is set (step S14).

  As described above, the first window is formed by steps S2 and S4, the second window is formed by steps S6 and S8, and the third window is formed by steps S10 and S12. The presence / absence of duty modulation and the change in duty ratio with respect to three periods of 128Fs, 64Fs, and 128 / 3Fs are determined by the respective windows, and additional data carried by the duty modulation on the original signal has the determination result. And extracted.

  According to the second embodiment, the “High” and “Low” level sections of the pulse waveform of the original signal are forcibly expanded / contracted using the 1024 Fs signal. In this case, one period of the 1024 Fs signal is generated. The section of “High” level and “Low” level can be digitally expanded and contracted, the duty ratio is changed, and additional data can be put on the change of the duty ratio to transmit data. In addition, since the change in the duty ratio can be digitally determined also on the receiving side, an additional data transmission device that is more accurate than the analog duty modulation of the first embodiment and can cope with a case where the transfer rate is high is also provided. There is an effect that can be provided.

  In the above description, the width of a signal that can exist is described as an example of IEC 958 having only three types of periods of 128 Fs, 64 Fs, and 128/3 Fs in both the “High” period and the “Low” period. Not only IEC958 but also any digital transmission system can have the same additional data transmission by having as many modulation circuits and detection circuits as the number of times that can be taken in the “High” section and “Low” section. It is.

It is a block diagram which shows the structure of the transmission side additional data transmission apparatus with which the data transmission method of Example 1 of this invention is applied. It is a timing chart which shows operation | movement of the additional data transmission apparatus by the side of the transmission of Example 1 of this invention. It is a block diagram which shows the structure of the receiving side additional data transmission apparatus with which the data transmission method of Example 1 of this invention is applied. It is a timing chart which shows operation | movement of the additional data transmission apparatus of the receiving side of Example 1 of this invention. It is a circuit diagram which shows the structure of the additional data transmission apparatus by the side of the transmission of Example 2 of this invention. It is a timing chart which shows operation | movement of the additional data transmission apparatus by the side of the transmission of Example 2 of this invention. It is a circuit diagram which shows the structure of the additional data transmission apparatus of the receiving side of Example 2 of this invention. It is a flowchart which shows operation | movement of the additional data transmission apparatus of the receiving side of Example 2 of this invention.

Explanation of symbols

  2... Additional data modulation section (duty modulation means), 4... Mixer circuit (duty modulation means), 5... Amplifier (transmission means), 11... First low-pass filter circuit (reception means), 12. Waveform correction circuit (duty ratio reference value generation means, waveform correction means), 13 ... second low-pass filter circuit (duty ratio reference value generation means), 14 ... comparator (detection means, determination means), 21, 23 ... ... D flip-flop (duty modulation means), 22, 32 ... inverter circuit (duty modulation means), 24 ... OR circuit (duty modulation means), 25, 26, 27 ... AND circuit (duty modulation means), 31 ... Synchronous circuit (duty modulation means), 33 ... OR circuit (transmission means), 41 ... waveform correction circuit (waveform correction means), 44 ... divided by 16 (Detection means), 45... 18 division counter (detection means), 46... 32 division counter (detection means), 47... 34 division counter (detection means), 48. Detection means), 49... 50 frequency division counter (detection means), 51... Judgment circuit (detection means, determination means).

Claims (7)

A data transmission method for transmitting additional data together with an original signal to be transmitted,
A data transmission characterized by changing the duty ratio of the original signal by an amount corresponding to the additional data, and reproducing the additional data from the amount of change of the duty ratio of the original signal on the receiving side. Method.   The upper limit and the lower limit of the change amount of the duty ratio allowed in the standard applied to the transmission system of the original signal are made to correspond to the state that the additional data can take, respectively, and the duty ratio of the original signal is set according to the additional data 2. The data transmission method according to claim 1, wherein transmission is performed with respect to a predetermined amount and a reference value.   Corresponding to the multi-value level that the additional data can take between the upper limit and the lower limit of the change amount of the duty ratio permitted in the standard applied to the transmission system of the original signal, the duty ratio of the original signal is added. The amount corresponding to the multi-value level of the data is changed and transmitted with respect to the reference value. On the receiving side, the amount of change in the duty ratio of the original signal is determined by a plurality of detection points corresponding to the multi-value level. 2. The data transmission method according to claim 1, wherein the multi-level additional data is reproduced. A data transmission device for transmitting additional data together with an original signal to be transmitted,
Duty modulation means for changing the duty ratio of the original signal in an amount corresponding to the additional data; and
Transmitting means for transmitting the original signal in which the duty modulation means changes the amount duty ratio according to the additional data;
A data transmission device comprising: A data transmission device for receiving additional data together with an original signal to be transmitted,
Detecting means for detecting a change in duty ratio with respect to a duty ratio reference value of the received original signal;
A determination unit that determines the additional data according to a change in the duty ratio based on a detection result of the detection unit;
A data transmission device comprising:   6. The data transmission apparatus according to claim 5, further comprising duty ratio reference value generating means for generating the duty ratio reference value. 7. The data transmission apparatus according to claim 5, further comprising waveform correction means for correcting a change in duty ratio with respect to a duty ratio reference value of the received original signal.

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