JP2005124177A - Digital modulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital modulator capable of executing adaptive modulation by a simple circuit structure. <P>SOLUTION: A CPU 10 outputs a mode selection signal MODSEL for each slot for specifying one modulation method from BPSK, π/4 shift-QPSK and 16QAM. A timing signal generation circuit 20 generates a clock signal CLK1 of which the rate is same as a data rate of the modulation method specified by the mode selection signal, and a clock signal CLK 2 at a symbol period. A serial/parallel conversion circuit 30 converts a base band signal AN into 4-bit parallel data in response to the clock signals CLK1 and CLK2. A mapping circuit 40 uniquely provides symbol mapping data corresponding to the specified modulation method. A digital filter 50 controls a band for I-phase and Q-phase symbol mapping data in time division multiplexing, and performs multiplication with a carrier signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a digital modulator, and more particularly to a digital modulator used as a MODEM (Modulator Demodulator) in a digital communication device such as a mobile communication system.

  2. Description of the Related Art Conventionally, in a mobile communication system such as a PHS (Personal Handyphone System), an information signal is transmitted by modulating a carrier signal with a digital information signal (baseband signal) in order to improve transmission efficiency. It is.

  As such a modulation method, an amplitude modulation method for modulating the amplitude of the carrier signal in accordance with a digital baseband signal (modulated wave signal), and a frequency modulation method for shifting the frequency of the carrier signal in accordance with the modulation wave signal There are various methods such as a phase modulation method for changing the phase of a carrier wave signal in accordance with a modulated wave signal.

Among these modulation schemes, a π / 4 shift QPSK (Quadrature Phase Shift Keying) modulation scheme, which is one of phase modulation schemes, is frequently used in mobile communication systems such as PHS.

  FIG. 42 is a diagram showing the arrangement of symbol points by the π / 4 shift QPSK modulation method on IQ plane coordinates.

  Referring to FIG. 42, four signal points at which symbol points corresponding to the data of the I-phase component and the Q-phase component of the baseband signal (modulated wave signal) at a certain point are located concentrically on the IQ coordinate plane. Assume that it exists in any one of a, c, e, and g. Further, at the next time point after a predetermined time slot has elapsed, this signal point is obtained by intersecting points b, d, f, and two concentric circles with two virtual axes obtained by rotating the I axis and the Q axis by π / 4. Move to any of h. As shown in FIG. 42, the phase change (π / 4, 3π / 4, 5π / 4, 7π / 4) at this time is transmitted in correspondence with the data (00, 01, 10, 11), so that 2 Bit data can be transmitted at once.

  The actual modulation is performed in a digital modulator mounted as a MODEM in each of the mobile terminal apparatus and the radio base apparatus (see, for example, Patent Document 1).

  For example, as disclosed in Patent Document 1, a conventional digital modulator includes a serial / parallel conversion circuit for converting a serial baseband signal (modulated wave signal) into parallel data, current parallel data, and A mapping circuit that differentially encodes parallel data one clock before and performs mapping on a signal space diagram, a digital filter that performs band limitation of mapping data and multiplication with a carrier signal, and analog modulation of the output of the digital filter A digital / analog converter for converting the signal into a signal and a low-pass filter are provided.

  In such a configuration, when a baseband signal representing the transmission content as serial data is input, it is converted into 2-bit parallel data (Xk, Yk) by serial-parallel conversion.

Next, the parallel data (Xk, Yk) is differentially encoded in the mapping circuit, and 2
The data is converted into 4-bit symbol mapping data composed of two quadrature components, that is, an in-phase (I-phase) component and a quadrature-phase (Q-phase) component.

  Further, these I-phase component and Q-phase component are respectively multiplied by carrier wave signal cos ωt and −sin ωt obtained by phase shifting the carrier wave signal by π / 2. By adding the two multiplication results, a modulated carrier signal (modulated signal) is output.

As described above, in the conventional mobile communication system, since the data transmission is performed with the modulation method fixed to the π / 4 shift QPSK modulation method, the digital modulator has a configuration corresponding to only a single modulation method. It was a thing.
JP-A-5-292135

  However, recent mobile communication systems require high-speed and large-capacity data transmission as compared with conventional voice communication, as in data communication, and therefore have a larger number of values than in the above QPSK modulation method. Many modulation schemes have been developed. As an example of such a multi-level modulation method, a 16QAM (Quadrature Amplitude Modulation) modulation method is known.

  FIG. 43 is a diagram showing the arrangement of symbol points by the 16QAM modulation method on the IQ plane coordinates.

  Referring to FIG. 43, as is well known, the 16QAM modulation system is based on one of a total of 16 signal points in the entire coordinate plane, arranged in a four-lattice form in each quadrant on the IQ coordinate plane. The symbol point of the band signal corresponds. For this reason, as shown in FIG. 43, 4-bit data indicating any of the 16 signal points can be transmitted at a time.

  On the other hand, if a modulation system with a large number of values such as the 16QAM modulation system is employed as a modulation system for a mobile communication system such as PHS, the symbol points are short and the symbol points are dense. If the communication environment of the propagation path is poor, there is a possibility that the symbol point may be recognized erroneously, and there is a problem that a reception error tends to occur while the communication speed is faster than the π / 4 shift QPSK modulation method. sell.

  In addition to the above-mentioned π / 4 shift QPSK and 16QAM, there is a BPSK (Binary Phase Shift Keying) modulation method.

  FIG. 44 is a diagram showing the arrangement of symbol points by the BPSK modulation method on the IQ coordinate plane.

  Referring to FIG. 44, the BPSK modulation method is a binary transmission method in which the phase of the carrier wave is changed to “0”, “π” corresponding to transmission data “0”, “1”, as is well known. is there.

  The BPSK modulation scheme is inferior to the above two modulation schemes in terms of frequency utilization, but is resistant to noise. Therefore, even when the communication environment of the propagation path is poor, communication can be performed without causing a reception error. Have.

  Therefore, depending on the state of the propagation path, that is, the communication quality, a modulation system with a small number of multivalues such as BPSK and π / 4 shift QPSK and a modulation system with a large number of multivalues such as 16QAM are adaptively switched. Conventionally, the idea of adaptive modulation that improves the communication speed as much as possible by performing communication has been proposed.

  For this reason, when performing adaptive modulation, the above-described digital modulator is required to have a configuration that can reliably cope with switching of modulation schemes. However, at present, a digital modulator that can cope with adaptive modulation has not necessarily been realized.

  On the other hand, it is not preferable that the circuit scale of the digital modulator is increased and complicated and the manufacturing cost is remarkably increased by implementing adaptive modulation.

  Therefore, an object of the present invention is to provide a digital modulator capable of realizing adaptive modulation with a simple circuit configuration.

  According to one aspect of the present invention, there is provided a digital modulator capable of supporting a plurality of modulation schemes having different multi-level numbers, and a high-order processor means for generating a digital baseband signal, and a plurality of consecutive bits of the baseband signal. Means for performing serial-to-parallel conversion every time, mapping means for uniquely giving symbol mapping data composed of orthogonal in-phase and orthogonal phase for each of a plurality of consecutive bits, and band-limiting the in-phase and orthogonal phase symbol mapping data And a digital filter means for multiplying the carrier signal by time division multiplexing, and means for converting the output of the digital filter means into an analog modulation signal. The upper processor means further includes means for generating a mode selection signal for selecting one modulation system from a plurality of modulation systems. The serial-to-parallel conversion means performs serial-to-parallel conversion for each of a plurality of bits corresponding to the number of bits that can be transmitted in the modulation system having the largest number of multi-values among the plurality of modulation systems. Symbol mapping data corresponding to the modulation scheme specified by the mode selection signal is given to the plurality of bits.

  Preferably, there is further provided timing signal generating means for generating a first clock signal having a speed equal to or higher than the data rate of the modulation scheme specified by the mode selection signal and a second clock signal equal to the symbol period. The serial-to-parallel conversion means latches the baseband signal in response to the first clock signal, and in response to the second clock signal, performs serial-to-parallel conversion for each of a plurality of bits, and outputs the mapping means. In response to the second clock signal, a plurality of bits are latched to uniquely provide symbol mapping data.

  More preferably, the timing signal generating means includes a switching signal generating means for switching the digital filter means between the in-phase symbol mapping data and the orthogonal phase symbol mapping data in a time division multiplexing manner.

  Preferably, the digital filter means corresponds to a means for accumulating each of the in-phase and quadrature-phase symbol mapping data in a time-division multiplexed manner corresponding to the plurality of symbol sections in accordance with the switching signal and the plurality of symbol sections. A plurality of storage means each storing a multiplication result of the symbol data that has passed a predetermined impulse response waveform and a corresponding carrier signal, and a means for adding the multiplication results read from the plurality of storage means Including. Each of the plurality of storage means stores a plurality of multiplication results corresponding to each of the plurality of modulation schemes.

  Preferably, each of the plurality of storage means stores a plurality of multiplication results corresponding to each of the plurality of modulation schemes, using the mode selection signal or a signal based on the mode selection signal as an upper address.

Preferably, the upper processor further includes means for generating an instruction signal instructing rising and falling of the baseband signal in burst transmission. The digital filter means further includes output mask means for selectively reading out the multiplication results from the plurality of storage means, and mask control means for controlling the output mask means in response to the instruction signal.

  According to another aspect of the present invention, the digital filter means has a predetermined number of tap outputs, and shift register means for holding each of the in-phase and quadrature-phase symbol mapping data sequentially delayed by a symbol period, and a desired A memory means for holding tap coefficients corresponding to a predetermined number of sampling points set on the impulse response waveform of the first, a predetermined number of tap outputs of the shift register means, and a multiplication of each of the held tap coefficients. Multiplying means for performing and adding means for adding the results of the multiplication are provided.

  According to the digital modulator according to the present invention, adaptive modulation for switching the modulation method in accordance with the communication quality can be easily realized only by making a slight change to the conventional digital modulator.

  Further, since the increase in circuit scale and complexity of the digital modulator accompanying adaptive modulation can be suppressed, an increase in manufacturing cost can be avoided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[Embodiment 1]
FIG. 1 is a block diagram showing a configuration of a digital modulator according to the first embodiment of the present invention. In the following embodiments, as an example of adaptive modulation, a configuration of a digital modulator for realizing adaptive modulation among the BPSK modulation scheme, the π / 4 shift QPSK modulation scheme, and the 16QAM modulation scheme is proposed.

  Referring to FIG. 1, the digital modulator includes a CPU (central processing unit) 10, a timing signal generation circuit 20, a serial / parallel conversion circuit (S / P) 30, a mapping circuit 40, and a digital filter 50. And a digital / analog converter (D / A) 80 and a low-pass filter (LPF) 90.

  The CPU 10 is a host processor for controlling the modulation processing of the entire digital modulator, and generates a serial baseband signal (modulated wave signal) AN during burst transmission. In addition, a burst input signal BIN that is activated in response to the rise of the baseband signal AN is generated. The burst input signal BIN is a signal given to the mask control circuit 53 in the digital filter 50, as will be described later.

  The CPU 10 further determines which of the BPSK, π / 4 shift QPSK, and 16QAM modulation schemes is used for each slot, and outputs 2-bit mode selection signals MODSEL0 and MODSEL1 for designating the modulation scheme. To do. Specifically, the mode selection signal [MODSEL1, MODSEL0] indicates [0, 0] when selecting the BPSK modulation method, and indicates [0, 1] when selecting the π / 4 shift QPSK modulation method. In the case of the system, [1, X] is indicated. Here, X means 0 or 1.

  The timing signal generation circuit 20 is driven by an input clock signal CLK higher than the symbol speed, and generates clock signals CLK1 and CLK2, time information A0 to A3 and an I / Q switching signal I / Q to be given to the digital filter 50. To do.

Specifically, the timing signal generation circuit 20 receives a mode selection signal MODSE from the CPU 10.
When L1 and MODSEL0 are received, a clock signal CLK1 having a speed corresponding to the modulation method designated by the mode selection signal MODSEL is generated.

  FIG. 2 is a circuit diagram showing a configuration of timing signal generating circuit 20 shown in FIG.

  Referring to FIG. 2, timing signal generation circuit 20 includes a counter circuit 21 that counts input clock signal CLK, a multiplexer 22, a flip-flop 23, and a NOT circuit G20.

  Although not shown, the counter circuit 21 includes five stages of cascaded flip-flops, and constitutes a 32-ary up counter. When an input clock signal CLK having a frequency higher than the symbol rate is input to the first flip-flop, the I / Q switching signal I is output as an output pulse obtained by dividing the frequency of the input clock signal CLK by 1/2. / Q is output. When this I / Q switching signal I / Q is input to the flip-flop at the second stage, an output pulse A0 further divided by half is output. Similarly, output pulses A1, A2, and A3 divided by ½ for each stage are also output from the third, fourth, and fifth stage flip-flops. These output pulses A0 to A3 are input to the multiplexer 22.

At this time, the output pulse A3 divided by 1/32 (= 1/2 ⁵ ) of the input clock signal CLK is inverted by the NOT circuit G20 and output as the clock signal CLK2. The clock signal CLK2 has the same speed as the symbol speed, and is supplied to the serial / parallel conversion circuit 30, the mapping circuit 40, and the digital filter 50 as shown in FIG. 1, and is used for latching each input data.

  The output pulses A0 to A3 are time information given to the digital filter 50 shown in FIG. Further, as will be described later, the I / Q switching signal I / Q is used for time division multiplexing of the digital filter 50 between the I-phase data and the Q-phase data.

  The multiplexer 22 receives the mode selection signals MODSEL1 and MODSEL0 from the CPU 10 together with the output pulses A0 to A3. The multiplexer 22 selects one output pulse according to the modulation method specified by the mode selection signals MODSEL1 and MODSEL0. Specifically, when the BPSK modulation method is designated (corresponding to [MODSEL1, MODSEL0] = [0, 0]), the output pulse A3 having the same speed as the symbol speed is selected. When the π / 4 shift QPSK modulation method is designated (corresponding to [MODSEL1, MODSEL0] = [0, 1]), the output pulse A2 having a speed twice the symbol speed is selected. Further, when the 16QAM modulation method is designated (corresponding to [MODSEL1, MODSEL0] = [1, X]), the output pulse A1 having a rate four times the symbol rate is selected.

  The output pulse selected according to the modulation method is output as the clock signal CLK1 in the flip-flop 23 after being synchronized with the input clock signal CLK. As shown in FIG. 1, the clock signal CLK1 is supplied to the serial / parallel conversion circuit 30 and used to latch the serial baseband signal AN.

  Referring to FIG. 1 again, when the serial baseband signal AN is given from the CPU 10, the serial / parallel conversion circuit 30 synchronizes with the clock signals CLK1 and CLK2 to generate parallel 4-bit data (Wk, Vk, Yk, Xk).

  FIG. 3 is a circuit diagram showing a configuration of serial / parallel conversion circuit 30 shown in FIG.

  Referring to FIG. 3, serial / parallel conversion circuit 30 includes four flip-flops 31 to 34 connected in cascade, and four flip-flops connected corresponding to the outputs of flip-flops 31 to 34, respectively. 35-38.

  The serial baseband signal AN input through the input terminal is sampled at the timing of the data rate clock signal CLK1 supplied from the timing signal generation circuit 20, and is held in the flip-flops 31 to 34 for 4 bits. As shown in FIG. 3, 4-bit parallel data (Wk-1, Vk-1, Yk-1, Xk-1) is held and output from the flip-flops 31-34 in response to the clock signal CLK1. Is done.

  Further, the 4-bit parallel data (Wk-1, Vk-1, Yk-1, Xk-1) is sampled at the timing of the clock signal CLK2 of the symbol period supplied from the timing signal generation circuit 20, and is flip-flop 35. Held in each of .about.38.

  The flip-flops 35 to 38 output 4-bit parallel data (Wk, Vk, Yk, Xk) in response to the clock signal CLK2.

  In this way, the serial baseband signal AN is converted into 4-bit parallel data. Here, the clock signal CLK1, which is the timing at which the flip-flops 31 to 34 hold the serial baseband signal AN, has the same speed as the data rate, and has a different speed for each modulation method as described above. Specifically, the data rate and the symbol rate are the same in the BPSK modulation method, which is the slowest modulation method among the modulation methods that can be supported in the present embodiment. On the other hand, in the π / 4 shift QPSK modulation method, the data rate is twice the symbol rate. Further, in the 16QAM modulation system, which is the fastest modulation system, the data rate is four times the symbol rate.

  Therefore, the parallel data output from the serial / parallel conversion circuit 30 in each modulation method is as follows.

  FIG. 4 is a timing chart for explaining parallel data output in the 16QAM modulation system.

  Referring to FIG. 4, the data rate of serial baseband signal AN is four times that of clock signal CLK2 having a symbol period. In accordance with the clock signal CLK1 having the same speed as the data rate, the flip-flops 31 to 34 hold 4-bit data (Wk-1, Vk-1, Yk-1, Xk-1). As shown in FIG. 3, the baseband signal AN (for example, N4, N3, N2, N1) is held as 4-bit data (Wk-1, Vk-1, Yk-1, Xk-1).

  Further, 4-bit data (for example, N4, N3, N2, N1) is output as parallel data (Wk, Vk, Yk, Xk) in response to the rising edge of the clock signal CLK2. Similarly, 4-bit data (N8, N7, N6, N5) is output in response to the next rise of clock signal CLK2. In this way, in the 16QAM modulation system, 4-bit parallel data is sequentially output for each symbol period.

  FIG. 5 is a timing diagram for explaining parallel data output in the π / 4 shift QPSK modulation method.

Referring to FIG. 5, the data rate of serial baseband signal AN is twice that of clock signal CLK2 having a symbol period. Clock signal C at the same speed as this data rate
According to LK1, flip-flops 31 to 34 hold 4-bit data (Wk-1, Vk-1, Yk-1, Xk-1). Of these 4-bit data, 2 bits (Yk-1, Xk-1) are set to an unused state ("UNUSED").

  Further, 4-bit data (Wk-1, Vk-1, Yk-1, Xk-1) is output as parallel data (Wk, Vk, Yk, Xk) in response to the clock signal CLK2. Of these, 2 bits (Yk, Xk) are not used according to unused input data (Yk-1, Xk-1). Therefore, 2-bit data (Wk-1, Vk-1) is converted into 2-bit parallel data (Wk, Vk) at the timing of the clock signal CLK2. As shown in FIG. 5, 2-bit parallel data (Wk, Vk) changes from (N-1, N-2) to (N1, N0), (N3, N2). In this way, in the π / 4 shift QPSK modulation system, 2-bit parallel data is sequentially output for each symbol period.

  FIG. 6 is a timing diagram for explaining parallel data output in the BPSK modulation method.

  Referring to FIG. 6, the data rate of serial baseband signal AN is the same as that of clock signal CLK2 having a symbol period. In accordance with the clock signal CLK1 having the same speed as the data rate, the flip-flops 31 to 34 hold 4-bit data (Wk-1, Vk-1, Yk-1, Xk-1). Of these 4-bit data, 3 bits (Vk-1, Yk-1, Xk-1) are not used.

  Further, 4-bit data (Wk-1, Vk-1, Yk-1, Xk-1) is output as parallel data (Wk, Vk, Yk, Xk) in response to the clock signal CLK2. Of these, 3 bits (Vk, Yk, Xk) are not used according to the unused input data (Vk-1, Yk-1, Xk-1). Therefore, in the BPSK modulation method, 1-bit data (Wk) is sequentially output at the timing of the clock signal CLK2 for each symbol period.

  Referring again to FIG. 1, parallel 4-bit data (Wk, Vk, Yk, Xk) is transmitted to mapping circuit 40. The mapping circuit 40 maps 4-bit data according to the modulation method specified by the mode selection signals MODSEL0 and MODSEL1 given from the CPU 10. Here, mapping refers to associating input data with any one of the symbol points (hereinafter also referred to as phase points) on the IQ coordinate axis plane composed of the I-phase component and the Q-phase component. That is, mapping refers to conversion of input data into symbol mapping data including I-phase component data and Q-phase component data representing symbol points.

  FIG. 7 is a circuit diagram showing a configuration of mapping circuit 40 shown in FIG.

  Referring to FIG. 7, mapping circuit 40 is largely divided into a mapping unit for π / 4 shift QPSK modulation system, a mapping unit for 16QAM system, and a mapping unit for BPSK modulation system in order to cope with adaptive modulation. Separated. The mapping circuit 40 includes multiplexers 45, 46, 47 and 48.

  First, the mapping unit for the π / 4 shift QPSK modulation method is a part that performs differential encoding of 2-bit parallel data (Wk, Vk) input from the serial / parallel conversion circuit 30 in FIG. It includes a 4-bit parallel register 41, an EXOR circuit G40, an adder 44, EXNOR circuits G41, G42, G44, G45, and a NOT circuit G43.

The EXOR circuit G40 performs a coincidence comparison of 2-bit parallel data (Wk, Vk), and outputs “0” (= corresponding to “L”) when the two are equal as a coincidence comparison result. 1 ″ (= corresponding to “H”) is output. The coincidence comparison result signal is input to the input A of the adder 44.
2 is input.

  Further, (Vk) of the 2-bit parallel data is input to the input A3 of the adder 44. As shown in FIG. 7, the inputs A2 and A3 of the adder 44 and the inputs A1 and A4 to which the power supply voltage and the ground voltage are respectively applied constitute 4-bit data [A4; A1] indicating a phase change.

  The adder 44 adds the phase change indicated by the 2-bit parallel data (Wk, Vk) to the symbol point one symbol before, and derives the symbol point in the current symbol. The symbol points are displayed as 3-bit signals (SM2, SM1, SM0) from the outputs S1 to S3 of the adder 44.

  The 4-bit parallel register 41 holds a 3-bit signal (SM2, SM1, SM0) indicating a symbol point one symbol before in response to the clock signal CLK2 having a symbol period. Further, these 3-bit signals are input to the inputs B1 to B3 of the adder 44 at the timing of the current symbol. The inputs B1 to B3 of the adder 44 and the input B4 to which the ground voltage is applied constitute 4-bit data [B4; B1] indicating a symbol point one symbol before.

  The adder 44 outputs the addition result of [A4; A1] and [B4; B1] of the input data to the outputs S1 to S4. As shown in FIG. 7, the output S4 indicating the most significant bit of the addition result is not used, and is encoded into 3-bit binary numbers (SM2, SM1, SM0) by the outputs S1 to S3. The 3-bit binary code (SM2, SM1, SM0) is input to the subsequent logic circuits G41 to G45 and held in the 4-bit parallel register 41.

  The EXNOR circuits G41, G42, G44, G45 and the NOT circuit G43 decode the 3-bit binary code (SM2, SM1, SM0) and generate 4-bit symbol mapping data (I1, I0, Q1, Q0). Occur. The 4-bit symbol mapping data is input to the inputs D2 of the multiplexers 45 to 48 provided for each bit.

  Multiplexers 45 to 48 receive symbol mapping data of 16QAM modulation system and BPSK modulation system, which will be described later, in addition to the above-described symbol mapping data of π / 4 shift QPSK modulation system, at inputs D1 to D4, respectively. The multiplexers 45 to 48 select one bit from the four-bit input in accordance with the mode selection signals MODSEL1 and MODSEL0, and output them as symbol mapping data (I1, I0, Q1, Q0).

  Hereinafter, the operation principle of the mapping circuit 40 in the π / 4 shift QPSK modulation method will be described in detail.

  In the π / 4 shift QPSK modulation system, differential encoding is generally performed in which data is discriminated from the relative phase between consecutive symbols in the symbol point arrangement diagram shown in FIG. If the IQ coordinate axis of the layout diagram of FIG. 42 is phase-shifted by π / 8, as shown in FIG. 8, the data of the I phase and the Q phase each have a quaternary level. Π / 4 shift QPSK modulation using such differential encoding is generally referred to as π / 4 shift DQPSK modulation.

  FIG. 8 is a diagram showing an arrangement of symbol points according to the π / 4 shift DQPSK modulation method.

Referring to FIG. 8, in π / 4 shift DQPSK modulation, symbol points necessary for representing a phase are displayed in the form of a 3-bit binary code. In the mapping operation shown below, these symbol points are expressed by decimal numbers from “0” to “7” in order to simplify the calculation. That is, the symbol points (000), (001), (010),.
Each is displayed as “0, 1, 2,... 7”.

  Further, as the symbol point is represented by a decimal number, a phase change indicated by 2-bit parallel data (Wk, Vk) is also converted into a decimal number notation (ADD-DATA).

  FIG. 9 is a truth table for explaining the mapping operation in the π / 4 shift QPSK modulation method.

  Referring to FIG. 9, 2-bit parallel data (Wk, Vk) is “1” when (0, 0), “3” when (1, 0), and (1, 1). It is represented by decimal data (hereinafter also referred to as ADD-DATA), such as “7” when “5” and (0, 1). This ADD-DATA is added to “0” to “7” indicating the symbol point of the previous symbol, and the result is subjected to MOD8 arithmetic processing, whereby “0” to “7” indicating the symbol point of the current symbol. A numerical value can be obtained. The MOD8 calculation process is an operation for obtaining a remainder obtained by dividing a certain numerical value by eight. As described above, in an actual circuit, numerical values “0” to “7” indicating symbol points are represented by 3-bit binary codes (SM2, SM1, SM0). Therefore, the ADD-DATA indicated by “1”, “3”, “5”, and “7” is also binary encoded by the EXOR circuit G40 shown in FIG.

  FIG. 10 is a truth table for explaining the mapping operation in the π / 4 shift QPSK modulation method.

  Referring to FIG. 10, the numerical values “0” to “7” indicating the symbol points of the current symbol are represented as 3-bit binary codes (SM2, SM1, SM0). These 3-bit binary codes are further decoded to generate 4-bit symbol mapping data (I1, I0, Q1, Q0). For example, the phase point “0” is represented by a 3-bit binary code (SM2, SM1, SM0) = (0, 0, 0), and this binary code is further converted to 4-bit symbol mapping data (I1). , I0, Q1, Q0) = (1, 1, 1, 0).

  Referring to FIG. 7 again, the 16QAM modulation scheme mapping unit is a part that maps 4-bit parallel data (Wk, Vk, Yk, Xk).

  4-bit parallel data (Wk, Vk, Yk, Xk) is input to inputs D3, D4 of multiplexers 45-48, respectively. Specifically, (Wk) of the 4-bit parallel data is input to the inputs D3 and D4 of the multiplexer 46. Similarly, (Vk) of the 4-bit parallel data is input to the inputs D3 and D4 of the multiplexer 45. Similarly, (Yk) of the 4-bit parallel data is input to the inputs D3 and D4 of the multiplexer 48. Similarly, (Xk) of the 4-bit parallel data is input to the inputs D3 and D4 of the multiplexer 47.

In the multiplexers 45 to 48, the input parallel data (Wk, Vk, Yk, Xk) is selected and output according to the mode selection signals MODSEL1, MODSEL0. As described above, when the mode selection signal [MODSEL1, MODSEL0] is [1, X], parallel data (Wk, Vk, Yk, Xk) in the 16QAM modulation system is a symbol at the output Q1 of each multiplexer 45-48. Output as mapping data (I1, I0, Q1, Q0).

  FIG. 11 is a truth table for explaining the mapping operation in the 16QAM modulation system.

  Referring to FIG. 11, when the mode selection signal [MODSEL1, MODSEL0] is [1, X], as described above, 4-bit parallel data (Wk, Vk, Yk, Xk) is 4 bits each. Mapped to symbol mapping data (I1, I0, Q1, Q0).

  Referring to FIG. 7 again, the BPSK modulation scheme mapping unit is a part that maps 1-bit data (Wk), and includes a NOT circuit G46.

  In the BPSK modulation system, out of 4-bit parallel data (Wk, Vk, Yk, Xk), (Vk, Yk, Xk) is not in use, and therefore, as shown in FIG. Wk) is input to the inputs D1 of the multiplexers 45 to 48, respectively. Data is input to the input D1 of the multiplexer 48 via the NOT circuit G46.

  The multiplexers 45 to 48 select and output the input D1 when the mode selection signal [MODSEL1, MODSEL0] becomes [0, 0] indicating that the BPSK modulation method is designated. In this way, 1-bit data (Wk) in the BPSK modulation method is output as symbol mapping data (I1, I0, Q1, Q0). Data (Wk) and symbol mapping data (I1, I0, Q1, Q0) have the relationship shown in FIG.

  As described above, in the mapping circuit 40, symbol mapping data (I1, I0, Q1, Q0) corresponding to each modulation method is generated and selectively output by the mode selection signals MODSEL1 and MODSEL0 that specify the modulation method. . The output symbol mapping data is transmitted to the digital filter 50 of FIG. The digital filter 50 limits the band of the baseband signal given by the symbol mapping data (I1, I0, Q1, Q0) and multiplies it with the carrier signal, and outputs digital data.

  FIG. 13 is a circuit diagram showing a configuration of digital filter 50 shown in FIG. The digital filter 50 of FIG. 13 basically uses a symbol tap ROM (Read Only Memory) division method.

  In the symbol tap ROM division method, the digital filter 50 is composed of a plurality of ROMs, and the multiplication result of the baseband signal and the carrier wave signal band-limited by the Nyquist filter is stored in the corresponding ROM for each symbol. In this method, the outputs of the respective ROMs are added. In the present embodiment, data corresponding to 4 symbol intervals, that is, a total of 9 symbol intervals, are accumulated before and after the central symbol interval, and the baseband signal passing through the Nyquist filter is multiplied by the carrier signal. It is assumed that the obtained data is output.

  Referring to FIG. 13, digital filter 50 includes symbol mapping data storage circuit 51, nine ROMs 50 </ b> A to 50 </ b> I arranged for each symbol section, and nine pieces arranged corresponding to the outputs of ROMs 50 </ b> A to 50 </ b> I. Mask circuits 50J to 50R, an adder 52 for outputting the sum of the outputs of the mask circuits 50J to 50R, and a mask control circuit 53 for controlling the outputs of the mask circuits 50J to 50R.

  When the symbol mapping data (I1, I0, Q1, Q0) generated in the mapping circuit 40 shown in FIG. 7 is input to the symbol mapping data storage circuit 51, the symbol mapping data storage circuit 51 has nine symbol intervals at the timing of the clock signal CLK2 of the symbol period. Accumulate minute data.

  FIG. 14 is a circuit diagram showing a detailed configuration of the symbol mapping data storage circuit 51.

  Referring to FIG. 14, symbol mapping data storage circuit 51 includes four 8-bit shift registers 54A to 54D, four flip-flops 55A to 55D, and ten multiplexers 56 to 65. Hereinafter, when the 8-bit shift registers 54A to 54D and the flip-flops 55A to 55D are collectively referred to, reference numerals 54 and 55 are used, respectively.

  Although not shown, the 8-bit shift register 54 includes eight stages of delay elements connected in cascade. The I-phase symbol mapping data (I1, I0) and the Q-phase symbol mapping data (Q1, Q0) are sequentially input to the 8-bit shift register 54 for each sampling period (corresponding to the symbol period clock signal CLK2). . Each delay element (not shown) sequentially holds input symbol mapping data while being delayed for each sampling period. Of the outputs Q0 to Q7 of each stage of the 8-bit shift register 54, the output Q7 is further output as an output Q delayed by the sampling period in the cascaded flip-flop 55. That is, the 8-bit shift register 54 and the flip-flop 55 constitute a nine-stage delay element. The outputs Q0 to Q7, Q of each stage form nine tap outputs of the digital filter 50, as will be described later.

  The outputs Q0 to Q7 and Q of the 8-bit shift register 54 and the flip-flop 55 are divided and given to five multiplexers 56 to 60 or 61 to 65. Specifically, out of the outputs Q0 to Q7 and Q of the 8-bit shift register 54A that holds the I-phase symbol mapping data I1, the outputs Q0 and Q1 are input to the inputs A0 and B0 of the multiplexer 56, respectively. The outputs Q2 and Q3 are input to the inputs A0 and B0 of the multiplexer 57. The outputs Q4 and Q5 are input to the inputs A0 and B0 of the multiplexer 58. The outputs Q6 and Q7 are input to the inputs A0 and B0 of the multiplexer 59. The output Q is input to the input A0 of the multiplexer 60.

  Similarly, of the outputs Q0 to Q7 and Q of the 8-bit shift register 54B and the flip-flop 55B that holds the Q-phase symbol mapping data Q1, the outputs Q0 and Q1 are input to the inputs A1 and B1 of the multiplexer 56, respectively. The outputs Q2 and Q3 are input to the inputs A1 and B1 of the multiplexer 57. The outputs Q4 and Q5 are input to the inputs A1 and B1 of the multiplexer 58. The outputs Q6 and Q7 are given to the inputs A1 and B1 of the multiplexer 59. The output Q is input to the input A1 of the multiplexer 60.

As shown in FIG. 14, the multiplexers 56 to 65 receive the outputs Q0 to Q7 and Q at the inputs (A0, A1, B0, B1), and as the control input SE for selecting the output, the I / Q switching signal I / Q Take Q. The I / Q switching signal I / Q is generated by the timing signal generation circuit 20 described above, and is changed between “1” and “0” at twice the speed of the least significant bit A0 of the time information A0 to A3. It is a transition signal.

  In response to the I / Q switching signal I / Q, the multiplexers 56 to 65 selectively output 2 bits of the 4-bit inputs (A0, A1, B0, B1) as outputs A and B. Specifically, when the I / Q switching signal I / Q is “0”, the multiplexers 56 to 65 select the input (A0, B0) and output it to the outputs A, B. On the other hand, when the I / Q switching signal I / Q is “1”, the multiplexers 56 to 65 select the inputs (A1, B1) and output them to the outputs A, B.

  When the above operation is examined with respect to the multiplexers 56 to 60 receiving the outputs Q0 to Q7 and Q from the 8-bit shift registers 54A and 54B, when the I / Q switching signal I / Q is "0", each multiplexer 56 Outputs Q0 to Q7, Q based on the I-phase symbol mapping data I1 input to the inputs (A0, B0) to -60 are selected and output. As for the multiplexer 60, since the input B0 is set to the ground potential, the output Q given to the input A0 is output to the output A.

  Therefore, when the I / Q switching signal I / Q is “0”, the data for nine symbol sections of the I-phase mapping data I1 are selected from the multiplexers 56 to 60, and as shown in FIG. (M41, M31, M21, M11, PM01, P11, P21, P31, P41).

  On the other hand, when the I / Q switching signal I / Q is “1”, the outputs Q0 to Q7 and Q based on the Q-phase symbol mapping data Q1 input to the inputs (A1 and B1) of the multiplexers 56 to 60 are selected. Is output. For the multiplexer 60, since the input B1 is set to the ground potential, the output Q given to the input A1 is output to the output A.

  Accordingly, when the I / Q switching signal I / Q is “1”, the data for nine symbol sections of the Q-phase symbol mapping data Q1 are selected from the multiplexers 56 to 60, and as shown in FIG. Data (M41, M31, M21, M11, PM01, P11, P21, P31, P41) will be output.

  Similarly for the I-phase symbol mapping data I0 and the Q-phase symbol mapping data Q0, the data Q0 to Q7 accumulated for each sampling period CLK2 by the 8-bit shift registers 54C and 54D and the flip-flops 55C and 55D. , Q are input to the inputs (A0, A1, B0, B1) of the multiplexers 61-65.

  Multiplexers 61-65 receive data for 9 symbol sections of I-phase symbol mapping data I0 and data for 9 symbol sections of Q-phase symbol mapping data Q0 in accordance with I / Q switching signal I / Q. Select alternately and output as data (M40, M30, M20, M10, PM00, P10, P20, P30, P40).

  As described above, the I-phase symbol mapping data (I0, I1) and the Q-phase symbol mapping data (Q0, Q1) are alternately output in response to the I / Q switching signal I / Q. By adopting such a configuration, one digital filter can be used in a time-division multiplexed manner, so that it is not necessary to provide a digital filter for each of the I phase and the Q phase, and the circuit configuration is simplified. Can do.

  FIG. 15 is a timing chart for explaining the operation of the symbol mapping data storage circuit 51.

  Referring to FIG. 15, symbol mapping data (I1, I0, Q1, Q0) input to symbol mapping data storage circuit 51 is (I1n-1, I0n) according to the symbol period (corresponding to clock signal CLK2). −1, Q1n−1, Q0n−1 (n is a natural number)) to (I1n, I0n, Q1n, Q0n).

  As for the symbol mapping data, 9 symbol sections are sequentially stored in 8-bit shift registers 54A to 54D and flip-flops 55A to 55D shown in FIG. Specifically, the 8-bit shift registers 54A to 54D and flip-flops 55A to 55D have (I1n-2, I1n-3... I1n-10) and (Q1n-2, Q1n− as shown in FIG. 3,... Q1n-10) are sequentially accumulated. These mapping data are transmitted to the subsequent multiplexers 56-65.

  Multiplexers 56 to 65 alternately output I-phase symbol mapping data and Q-phase symbol mapping data in accordance with I / Q switching signal I / Q. As shown in FIG. 15, the I / Q switching signal I / Q is a signal that transitions at a speed that is twice as fast as the time information A0 (corresponding to a speed eight times that of the clock signal CLK2). Accordingly, the outputs (M41, M31, M21, M11, PM01, P11, P21, P31, P41) of the multiplexers 56 to 60 are the I-phase symbol mapping data (I1n-2, I1n-3... I1n-10) and Q-phase symbol mapping data (Q1n-2, Q1n-3,... Q1n-10). For this reason, the symbol mapping data storage circuit 51 can be used in a time division multiplexed manner.

  In general, in digital wireless communication, a digital filter is used to narrow the band of digital data from the viewpoint of effective use of radio waves, and there is no intersymbol interference as a digital filter that realizes this narrow band. A known Nyquist filter having transmission characteristics (Nyquist characteristics) is used.

  The basic processing of the Nyquist filter is as follows. That is, a tap coefficient for each sampling point of a desired impulse response waveform with respect to an impulse input is held, and input digital data is sequentially held in a shift register having a predetermined number of taps, and each tap output is multiplied by the corresponding tap coefficient. To obtain the filter output.

  FIG. 16 is an impulse response waveform of a digital filter that realizes the Nyquist characteristic.

  Referring to FIG. 16, the impulse response waveform has a waveform that attenuates rapidly around the main lobe. The impulse response waveform is discretely quantized at sampling points corresponding to the number of tap outputs of the digital filter at predetermined sampling (symbol) intervals. The widening quantized at each sampling point corresponds to the aforementioned tap coefficient.

  In the symbol tap ROM division method employed in the present embodiment, for each sampling point, a band-limited baseband signal obtained by multiplying a tap output and a corresponding tap coefficient is multiplied by a carrier signal. Filter output data is obtained, and the filter output data is stored in advance in a plurality of ROMs arranged for each tap output. The filter output can be obtained by reading the multiplication result for each ROM using the input digital data as an address and adding them. Note that the data length of the multiplication result stored in each ROM differs depending on the ROM depending on the dynamic range of each symbol section of the impulse response waveform of the Nyquist filter with a roll-off factor α = 0.5.

  In the present invention, each ROM has a multiplication result in the π / 4 shift QPSK modulation method, a multiplication result in the 16QAM modulation method, and a single digital filter to cope with adaptive modulation among a plurality of modulation methods. Is stored. Note that symbol mapping data, which is input digital data of the BPSK modulation method, coincides with a part of the symbol mapping data of the π / 4 shift QPSK modulation method (equivalent to the coincidence of the symbol points on the IQ coordinate plane). The multiplication result of the π / 4 shift QPSK modulation method can be used as the multiplication result of the BPSK modulation method. That is, each ROM has storage areas for multiplication results of two modulation methods, and these storage areas are sorted by a mode selection signal MODSEL1 which is the most significant address A6 of input digital data, as shown below. Has been.

  Referring to FIG. 13 again, the data for nine symbol sections of the I-phase and Q-phase symbol mapping data stored in symbol mapping data storage circuit 51 is divided and input into nine ROMs 50A-50I. The total of nine ROMs 50A to 50I corresponds to the total number of tap outputs in the digital filter 50 described above.

  When the I / Q switching signal I / Q is “0”, the data for nine symbol sections of the I-phase symbol mapping data (I0, I1) is given to the corresponding ROMs 50A to 50I for each symbol section. . On the other hand, when the I / Q switching signal I / Q is “1”, the data for nine symbol sections of the Q-phase symbol mapping data (Q0, Q1) is stored in the corresponding ROMs 50A to 50I for each symbol section. Given.

  The ROMs 50A to 50I use the 4-bit time information A0 to A3 given from the timing signal generation circuit 20 of FIG. 1 and the 2-bit symbol mapping data of the corresponding symbol section as address inputs A0 to A5. Further, the 1-bit mode selection signal MODSEL1 is used as the most significant address input A6. As described above, the mode selection signal MODSEL1 is a signal for selecting the π / 4 shift QPSK modulation method and the BPSK modulation method when “0” and for selecting the 16QAM modulation method when “1”. Therefore, the filter output data corresponding to each modulation method is read from the ROMs 50A to 50I by the most significant address A6. These filter output data are read as symbol data D having a predetermined data length in accordance with address inputs A0 to A6.

  Specifically, in consideration of the dynamic range of each symbol interval, the ROM 50A corresponding to the symbol interval of the accumulation number -4 and the ROM 50I corresponding to the symbol interval of the accumulation number 4 each provide symbol data having a data length of 3 bits. D0 to D2 are output. Similarly, symbol data D0 to D3 having a data length of 4 bits are output from the ROM 50B corresponding to the symbol interval of the accumulation number -3 and the ROM 50H corresponding to the symbol interval of the accumulation number 3, respectively. Furthermore, symbol data D0 to D5 having a data length of 6 bits are output from the ROM 50C corresponding to the symbol interval of the accumulation number −2 and the ROM 50G corresponding to the symbol interval of the accumulation number 2 respectively. Furthermore, symbol data D0 to D8 having a data length of 9 bits are output from the ROM 50D corresponding to the symbol interval of the accumulation number -1 and the ROM 50F corresponding to the symbol interval of the accumulation number 1, respectively. Finally, symbol data D0 to D9 having a data length of 10 bits are output from the ROM 50E corresponding to the symbol interval of 0 stored.

  These filter output data are added by the adder 52 and converted into 10-bit digital signals DA0 to DA9. As shown in FIG. 1, the digital signals DA0 to DA9 are converted into analog signals by a digital / analog converter 80, and then sampled noise is removed by an LPF 90 and output as a modulated signal S (t). .

FIG. 17 is a diagram showing filter output waveforms read from each of the ROMs 50A to 50I shown in FIG. 13 and a combined waveform obtained by adding these filter output waveforms. As an example, an output waveform of one symbol period when the 16QAM modulation method is selected is shown.

  Further, similarly for the π / 4 shift QPSK modulation method and the BPSK modulation method (not shown), the output waveforms stored in the ROMs 50A to 50I are read out to form filter outputs.

  Referring to FIG. 13 again, nine mask circuits 50J to 50R are arranged between ROMs 50A to 50I and adder 52 corresponding to the output of each ROM. The mask circuits 50J to 50R are portions for temporarily masking the ROM output during burst transmission to prevent spurious generation.

  In burst transmission, since transmission is performed intermittently, there is a problem that spurious is increased due to steep rise and fall of the transmission signal, and the frequency band of the transmission signal is widened. For this reason, a method is known in which a certain ramp period is provided before and after the transmission of the modulation signal, and the level of the transmission signal rises and falls smoothly during this ramp period. This process is generally referred to as a ramp process. Mask circuits 50J to 50R are used to temporarily mask the transmission signal during the ramp period and smoothly increase or decrease the amplification factor of the transmission signal.

  FIG. 18 is a circuit diagram showing a configuration of mask circuits 50J-50R shown in FIG. Since the mask circuits 50J to 50R have the same basic configuration except that the number of input / output bits is different, the mask circuit 50J will be described below as a representative.

  Referring to FIG. 18, mask circuit 50J includes three AND circuits G51 to G53 that receive, as a first input, data for each bit of 3-bit data [D0; D2]. Further, when the AND circuit G51 to G53 receives the control signal from the mask control circuit 53 as the second input to the control input SE, the AND circuit G51 to G53 calculates the logical product of these two signals and outputs a 3-bit signal [B0; B2] is output.

  That is, the AND circuits G51 to G53 output 3-bit data [B0; B2] equal to the input data [D0; D2] when the control signal is at the “H” level. On the other hand, when the control signal SE is at the “L” level, the data [B0; B2] at the “L” level is output regardless of the input data.

  FIG. 19 is a circuit diagram showing a configuration of mask control circuit 53 that generates control signals for mask circuits 50J-50R in FIG.

  Referring to FIG. 19, mask control circuit 53 includes nine flip-flops 66 to 74 connected in cascade and AND circuits G54 to G57.

  When the burst input signal BIN is input from the CPU 10 (not shown), the flip-flops 66 to 74 sequentially hold the signals while delaying them for each symbol period in response to the clock signal CLK2, and control signals MC4 to MCM1, MCPM0, MCP1 MCP3 is output.

  Of the nine-stage flip-flops 66 to 74, the output signals of the first-stage and second-stage flip-flops 66 and 67 are input to the AND circuits G54 and G55 in the subsequent stage, respectively. The outputs Q of the flip-flop 68 at the third stage are further input to the AND circuits G54 and G55. The AND circuits G54 and G55 output control signals MCM4 and MCM3, respectively, as the operation results of the 2-input AND.

  Similarly, the output signals of the eighth-stage and ninth-stage flip-flops 73 and 74 are input to the AND circuits G56 and G57 in the subsequent stage, respectively. The AND circuit G56, G57 further receives the output signal MCP2 of the seventh-stage flip-flop 72. AND circuits G56 and G57 output control signals MCP4 and MCP3, respectively, as the operation results of the 2-input AND.

  Consider the case where the burst input signal BIN changes from “L” to “H” in accordance with the rise of burst transmission in the above configuration. In response to the burst input signal BIN becoming “H” level, the flip-flops 66 to 74 output “H” level control signals while being delayed by a symbol period. With respect to the first-stage and second-stage flip-flops 66 and 67, “H” level signals are output to AND circuits G 54 and G 55 in the first and second symbol periods. Here, since the output signal MCM2 of the third flip-flop 68 input to the AND circuits G54 and G55 changes to the “H” level in the third symbol period, the control signal output from the AND circuits G54 and G55. MCM4 and MCM3 and the control signal MCM2 output from the third flip-flop 68 are delayed by two symbol periods from the rising edge of the burst input signal BIN, and simultaneously change to the “H” level. Note that the fourth and subsequent flip-flops 69 to 74 sequentially change from the “L” level to the “H” level while being delayed by the symbol period.

  Next, consider a case where the burst input signal BIN changes from the “H” level to the “L” level in response to the falling of the burst transmission. In response to the burst input signal BIN becoming “L” level, the control signals output from the flip-flops 66 to 74 sequentially change to “L” level while being delayed by the symbol period. Here, when the control signal MCP2 output from the seventh flip-flop 72 input to the AND circuits G56 and G57 changes to “L” level after being delayed by 6 symbol periods from the falling edge of the burst input signal BIN, In the circuits G56 and G57, the control signals MCP4 and MCP3 change from the “H” level to the “L” level simultaneously with the control signal MCP2.

  Referring to FIG. 13 again, when mask circuits 50J-50R receive a control signal from mask control circuit 53, the data output is controlled in accordance with the logic.

  As described above, at the rising edge of burst transmission, the control signals MCM4, MCM3, and MCM2 become “H” level with a delay of two symbol periods from the rising edge of the burst input signal BIN. At 50J and 50K, the two symbol periods are masked and then sequentially output.

  At the fall of burst transmission, the control signals MCP2, MCP3, and MCP4 simultaneously change to the “L” level, so that the output data of the ROMs 50H and 50I are masked in the subsequent symbol periods.

  Thus, by sequentially masking the output data of the ROMs 50A to 50I at the rising and falling edges of burst transmission, the rising and falling edges of the output data signal can be smoothed, and the occurrence of transmission spurious can be suppressed. Can do. Further, since the above mask processing is performed by the control signal of the mask control circuit 53, it is not necessary to add a new ROM for storing the rising and falling waveforms, and an increase in ROM capacity is avoided. Can do.

  As described above, according to Embodiment 1 of the present invention, adaptive modulation among a plurality of modulation schemes can be easily realized.

  In addition, since the digital modulator can be configured with only slight changes to the conventional digital modulator, an increase in circuit scale and complexity associated with adaptive modulation can be avoided.

[Embodiment 2]
FIG. 20 is a block diagram showing a configuration of a digital modulator according to the second embodiment of the present invention. In the following embodiments, a configuration of a digital modulator for realizing adaptive modulation corresponding to the 8PSK modulation scheme and the 64QAM modulation scheme in addition to the modulation scheme corresponding to the first embodiment is proposed. In the following description, only parts different from the first embodiment will be described, and detailed description of the same parts will not be repeated.

  Referring to FIG. 20, the digital modulator is a CPU instead of CPU (central processing unit) 10, serial / parallel conversion circuit (S / P) 30, mapping circuit 40, and digital filter 50 in the first embodiment. (Central processing unit) 110, serial / parallel conversion circuit (S / P) 130, mapping circuit 140, and digital filter 150 are provided.

  The burst input signal BIN output from the CPU 110 is a signal given to the mask control circuit 53 in the digital filter 150, as will be described later.

  The CPU 110 determines, for each slot, which of BPSK, π / 4 shift QPSK, 8PSK, 16QAM, and 64QAM is used for transmission, and 3-bit mode selection signals MODSEL0 and MODSEL1 for designating the modulation system. , MODSEL2 is output. Specifically, the mode selection signals [MODSEL2, MODSEL1, MODSEL0] indicate [0, 0, 0] when selecting the BPSK modulation method, and [0, 0, 1 when selecting the π / 4 shift QPSK modulation method. [0, 1, 0] when the 8PSK modulation method is selected, [1, 1, 0] when the 16QAM modulation method is selected, and [0, 1, 0 when the 64QAM modulation method is selected. 1].

  FIG. 21 is a diagram showing the relationship between CLK1 output from the timing signal generation circuit 20 and the mode selection signals MODSEL1 and MODSEL0.

  As described above, the output pulse selected by the multiplexer 22 in the timing signal generation circuit 20 is sampled and held in the flip-flop 23 at the timing of the input clock signal CLK, and then output as the clock signal CLK1.

  Referring to FIG. 21, multiplexer 22 in timing signal generation circuit 20 outputs an output at the same speed as the symbol rate when the BPSK modulation method is designated (corresponding to [MODSEL1, MODSEL0] = [0, 0]). Select pulse A3. When the π / 4 shift QPSK modulation method is designated (corresponding to [MODSEL1, MODSEL0] = [0, 1]), the output pulse A2 having a speed twice the symbol speed is selected. When the 8PSK modulation method or the 16QAM modulation method is designated (corresponding to [MODSEL1, MODSEL0] = [1, 0]), the output pulse A1 having a rate four times the symbol rate is selected. When the 64QAM modulation method is designated (corresponding to [MODSEL1, MODSEL0] = [1,1]), the output pulse A0 having a rate eight times the symbol rate is selected.

  Referring to FIG. 20 again, serial / parallel conversion circuit 130 converts serial baseband signal AN received from CPU 110 into parallel 7-bit data (Nt, Mt, Lt, Kt) synchronized with clock signals CLK1, CLK2. , Jt, It, Ht).

  FIG. 22 is a circuit diagram showing a configuration of serial / parallel conversion circuit 130 shown in FIG.

  Referring to FIG. 22, serial / parallel conversion circuit 130 is connected in accordance with cascaded eight flip-flops 131 </ b> A to 138 </ b> A and outputs of flip-flops 131 </ b> A to 136 </ b> A and flip-flop 138 </ b> A. Including flip-flops 131B to 136B and flip-flop 138B.

  The flip-flop 131A samples and holds the serial baseband signal AN input via the input terminal at the timing of the clock signal CLK1 provided from the timing signal generation circuit 20, and outputs the sampled baseband signal AN. The flip-flop 132A samples and outputs the data received from the flip-flop 131A after one cycle of the clock signal CLK1. In this way, the flip-flops 131A to 138A hold the 8-bit baseband signal AN sampled at one cycle interval of the clock signal CLK1.

  Also, 7-bit parallel data (Nt−1, Mt−1, Lt−1, Kt−1, Jt−1, It−1) output from the flip flops 131A to 136A and the flip flop 138A at the timing of the clock signal CLK1. , Ht−1) are sampled and held by the flip-flops 131B to 136B and the flip-flop 138B at the timing of the clock signal CLK2 of the symbol period provided from the timing signal generation circuit 20, and are stored in 7-bit parallel data (Nt, Mt). , Lt, Kt, Jt, It, Ht).

  In this way, the serial baseband signal AN is converted into 7-bit parallel data. Here, as described above, the clock signal CLK1 that gives the timing at which the flip-flops 131A to 138A sample the serial baseband signal AN has a different speed for each modulation method.

  Therefore, the parallel data output from the serial / parallel conversion circuit 130 in each modulation method is as follows. The 4-bit parallel data (Nt, Mt, Lt, Kt) in the present embodiment is a replacement of the 4-bit parallel data (Wk, Vk, Yk, Xk) in the first embodiment. Accordingly, the 4-bit parallel data (Wk, Vk, Yk, Xk) of the BPSK, π / 4 shift QPSK, 16QAM modulation system has been described in the first embodiment, and therefore, the description thereof will not be repeated here.

  FIG. 23 is a timing chart for explaining parallel data output in the 8PSK modulation method.

  Referring to the figure, the data rate of serial baseband signal AN has a speed three times that of clock signal CLK2 having a symbol period. The clock signal CLK1 has a speed four times that of the clock signal CLK2 having a symbol period.

  As shown in the figure, 4-bit parallel data (Nt, Mt, Lt, Kt) sampled at the timing of CLK2 is (N0, N-1, N-1, N) during one cycle of the clock signal CLK2. -2) to (N3, N2, N2, N1). That is, the data of the baseband signal AN held in the flip-flops 131B to 134B is updated during one cycle of the clock signal CLK2.

  In the 8PSK modulation system, among the 4-bit parallel data (Nt, Mt, Lt, Kt) output from the flip-flops 131B to 134B, 3-bit parallel data (Nt, Mt, Kt) with no overlapping data is obtained. used. In this way, in the 8PSK modulation system, new 3-bit parallel data is sequentially output for each symbol period.

  FIG. 24 is a timing chart for explaining parallel data output in the 64QAM modulation system.

  Referring to the figure, the data rate of serial baseband signal AN has a speed six times that of clock signal CLK2 having a symbol period. The clock signal CLK1 has a speed eight times that of the clock signal CLK2 having a symbol period.

  As shown in the figure, 7-bit parallel data (Nt, Mt, Lt, Kt, Jt, It, Ht) sampled at the timing of CLK2 is (N0, N−1) during one cycle of the clock signal CLK2. , N-1, N-2, N-3, N-4, N-4, N-5) to (N6, N5, N5, N4, N3, N2, N2, N1). That is, the data of the baseband signal AN held in the flip-flops 131B to 136B and the flip-flop 138B is updated during one cycle of the clock signal CLK2. Here, UNUSED in the upper part of the figure is data output from the flip-flop 137A. Further, UNUSED in the lower part of the figure is data when it is assumed that the data output from the flip-flop 137A is held at the timing of the clock signal CLK2.

  In the 64QAM modulation system, of the 7-bit parallel data (Nt, Mt, Lt, Kt, Jt, It, Ht) output from the flip-flops 131B to 136B and the flip-flop 138B, 6-bit data not overlapping Parallel data (Nt, Mt, Kt, Jt, It, Ht) is used. In this way, in the 64QAM modulation system, new 6-bit parallel data is sequentially output every symbol period.

  Referring to FIG. 20 again, 7-bit parallel data (Nt, Mt, Lt, Kt, Jt, It, Ht) is transmitted to mapping circuit 140. The mapping circuit 140 maps 7-bit data according to the modulation method specified by the mode selection signals MODSEL0, MODSEL1, and MODSEL2 given from the CPU 110.

  25 to 28 are circuit diagrams showing configurations of respective parts of the mapping circuit 140 in the digital modulator shown in FIG. The mapping circuit 140 includes a mapping unit for the π / 4 shift QPSK modulation method shown in FIG. 25, a mapping unit for the 8PSK modulation method shown in FIG. 26, a mapping unit for the BPSK, 16QAM and 64QAM modulation methods shown in FIG. 28 is provided.

  The π / 4 shift QPSK modulation scheme mapping section shown in FIG. 25 receives 2-bit parallel data (Nt, Mt) from the serial / parallel conversion circuit 130, and is symbol mapping data for the π / 4 shift QPSK modulation scheme. Certain QPSK-I0, QPSK-I1, QPSK-Q0, and QPSK-Q1 are generated and output to the selection unit shown in FIG. Other configurations and operations are the same as those of the mapping unit for π / 4 shift QPSK modulation method in the mapping circuit 40 shown in FIG.

  Therefore, the mapping operation of the mapping unit for π / 4 shift QPSK modulation method shown in FIG. 25 is as shown in FIG. I2 and Q2 will be described later.

  The mapping unit for the 8PSK modulation method shown in FIG. 26 includes EXNOR circuits G141, G142, G144, and G145, and a NOT circuit G143.

  EXNOR circuits G141, G142, G144, G145 and NOT circuit G143 decode 3-bit parallel data (Nt, Mt, Kt) received from serial / parallel conversion circuit 130, and a 4-bit symbol for the 8PSK modulation system. The mapping data 8PSK-I0, 8PSK-I1, 8PSK-Q0, and 8PSK-Q1 are output to the selection unit shown in FIG.

  The arrangement of symbol points in the 8PSK modulation scheme is the same as the arrangement of symbol points in the π / 4 shift QPSK modulation scheme shown in FIG. However, in the π / 4 shift QPSK modulation method, as described above, 2-bit parallel data (Nt, Mt) is associated with one of the eight symbol points shown in FIG. In the 8PSK modulation system, 3-bit parallel data (Nt, Mt, Kt) is associated with one of the eight symbol points shown in FIG.

  Therefore, the mapping operation of the mapping unit for the 8PSK modulation method shown in FIG. 26 is as shown in FIG. I2 and Q2 will be described later.

  The mapping unit for BPSK, 16QAM, and 64QAM modulation methods shown in FIG. 27 includes a NOT circuit G146.

  Of the 7-bit parallel data (Nt, Mt, Lt, Kt, Jt, It, Ht) output from the serial / parallel conversion circuit 130, (Nt) is branched, and one of the branched data is input to the NOT circuit G146. The Based on the 7-bit parallel data (Nt, Mt, Lt, Kt, Jt, It, Ht), BPSK-I0, BPSK-I1, BPSK-Q0, and BPSK-Q1, which are symbol mapping data for the BPSK modulation method, 16Q-I0, 16Q-I1, 16Q-Q0, 16Q-Q1 as symbol mapping data for 16QAM modulation system, and 64Q-I0, 64Q-I1, 64Q-I2, as symbol mapping data for 64QAM modulation system 64Q-Q0, 64Q-Q1, and 64Q-Q2 are output to the selection unit shown in FIG.

  Here, among 7-bit parallel data (Nt, Mt, Lt, Kt, Jt, It, Ht), 1-bit data (Nt) is used in the BPSK modulation method, and 4-bit parallel data in the 16QAM modulation method. (Nt, Mt, Lt, Kt) is used, and 6-bit parallel data (Nt, Mt, Kt, Jt, It, Ht) is used in the 64QAM modulation system.

  The symbol points in the BPSK modulation scheme coincide with the symbol points 0 and 4 of the π / 4 shift QPSK modulation scheme shown in FIG.

  Therefore, the mapping operation in the BPSK modulation method is as shown in FIG. I2 and Q2 will be described later.

  The arrangement of symbol points in the 16QAM modulation system is shown in FIG. FIG. 33 shows the relationship between 4-bit parallel data (Nt, Mt, Lt, Kt) and symbol points in the 16QAM modulation system. The transmission data shown in FIG. 33 corresponds to 4-bit parallel data (Nt, Mt, Lt, Kt) in order from the left.

  Therefore, the mapping operation in the 16QAM modulation system is as shown in FIG. I2 and Q2 will be described later.

  The arrangement of symbol points in the 64QAM modulation system is shown in FIG. FIG. 36 shows the relationship between 6-bit parallel data (Nt, Mt, Kt, Jt, It, Ht) and symbol points in the 64QAM modulation system. The transmission data shown in FIG. 36 corresponds to 6-bit parallel data (Nt, Mt, Kt, Jt, It, Ht) in order from the left.

  Therefore, the mapping operation in the 64QAM modulation system is as shown in FIG.

  The selection unit illustrated in FIG. 28 includes multiplexers 142 to 147.

  Multiplexer 142 receives I0 data among the symbol mapping data received from the mapping units shown in FIGS. That is, multiplexer 142 receives BPSK-I0 as input D0, QPSK-I0 as input D2, 8PSK-I0 as input D4, 16Q-I0 as input D5, and 64Q-I0 as input D6. Similarly, multiplexer 143 receives I1 data, multiplexer 145 receives Q0 data, and multiplexer 146 receives Q1 data.

  The multiplexer 144 receives 64Q-I2, which is I2 data, of the symbol mapping data for the 64QAM modulation method received from the mapping unit shown in FIG. The multiplexer 147 receives 64Q-Q2, which is Q2 data, of the symbol mapping data for the 64QAM modulation system received from the mapping unit shown in FIG. Since symbol mapping data of BPSK, π / 4 shift QPSK, 8PSK and 16QAM modulation schemes does not have I2 and Q2, inputs D0, D2 and D4 corresponding to BPSK, π / 4 shift QPSK and 8PSK modulation schemes are at ground potential. Connected to. The input D5 corresponding to the 16QAM modulation system is connected to the fixed potential Vcc. Therefore, I2 and Q2 of symbol mapping data in the BPSK, π / 4 shift QPSK and 8PSK modulation systems are always 0 as shown in FIGS. 29 to 31, and I2 and Q2 of the symbol mapping data in the 16QAM modulation system are shown in FIG. As shown, it is always 1. This is to distinguish each modulation method in the digital filter 151 described later.

  Note that the inputs D1 and D3 that are not used in the multiplexers 142 to 147 are connected to the ground potential.

  Multiplexers 142 to 147 select one of input D0 to input D6 in accordance with MODSEL0 to MODSEL2 received from CPU 110 in the digital modulator shown in FIG. 20, and each of symbol mapping data I0 to I2 and Q0 to Q0, respectively. Output as Q2.

  FIG. 38 shows the relationship between MODSEL0 to MODSEL2 and symbol mapping data selected by multiplexers 142 to 147.

  Referring to FIG. 28, multiplexers 142 to 147 in the selection unit shown in FIG. 28 indicate that when the BPSK modulation method is designated (corresponding to [MODSEL2, MODSEL1, MODSEL0] = [0, 0, 0]). , D0 is selected. When the π / 4 shift QPSK modulation method is designated (corresponding to [MODSEL2, MODSEL1, MODSEL0] = [0, 0, 1]), D2 is selected. When the 8PSK modulation method is designated (corresponding to [MODSEL2, MODSEL1, MODSEL0] = [0, 1, 0]), D4 is selected. Further, when the 16QAM modulation method is designated (corresponding to [MODSEL2, MODSEL1, MODSEL0] = [1,1,0]), D5 is selected. When the 64QAM modulation system is designated (corresponding to [MODSEL2, MODSEL1, MODSEL0] = [0, 1, 1]), D6 is selected.

  As described above, the mapping circuit 140 generates symbol mapping data (I2, I1, I0, Q2, Q1, Q0) corresponding to each modulation method, and uses the mode selection signals MODSEL2, MODSEL1, and MODSEL0 that specify the modulation method. Output selectively. The output symbol mapping data is transmitted to the digital filter 150 in the digital modulator shown in FIG. The digital filter 150 band-limits the baseband signal given by the symbol mapping data (I2, I1, I0, Q2, Q1, Q0) and multiplies it with the carrier signal, and outputs digital data.

  FIG. 39 is a circuit diagram showing a configuration of digital filter 150 in the digital modulator shown in FIG.

  Referring to FIG. 39, digital filter 150 includes symbol mapping data storage circuit 151 and ROMs 150A to 150I instead of symbol mapping data storage circuit 51 and ROMs 50A to 50I in digital filter 50 shown in FIG. The digital filter 150 further includes an AND circuit G154 with respect to the digital filter 50 shown in FIG.

  When the symbol mapping data (I2, I1, I0, Q2, Q1, Q0) generated by the mapping circuit 140 in the digital modulator shown in FIG. 20 is input to the symbol mapping data storage circuit 151, a clock signal with a symbol period is input. At the timing of CLK2, data for 9 symbol sections is accumulated.

  Similarly to the symbol mapping data I1, I0, Q1, Q0 in the symbol mapping data storage circuit 51, the symbol mapping data storage circuit 151 responds to the I / Q switching signal I / Q in accordance with the I-phase symbol mapping data I2. The data for nine symbol sections and the data for nine symbol sections of the Q-phase symbol mapping data Q2 are alternately selected to obtain data (M42, M32, M22, M12, PM02, P12, P22, P32, P42). Output as.

  Other configurations and operations are the same as those of the symbol mapping data storage circuit 51 shown in FIG. Symbol mapping data storage circuit 151 has a configuration in which one circuit for symbol mapping data of I phase and Q phase is added to symbol mapping data storage circuit 51 shown in FIG. .

  As described above, in the symbol mapping data storage circuit 151, the I-phase symbol mapping data (I2, I1, I0) and the Q-phase symbol mapping data (Q2, Q1, Q0) are converted into the I / Q switching signal I / It is alternately output in response to Q. By adopting such a configuration, one digital filter can be used in a time-division multiplexed manner, so that it is not necessary to provide a digital filter for each of the I phase and the Q phase, and the circuit configuration is simplified. Can do.

  In the present embodiment, each ROM has a multiplication result in the π / 4 shift QPSK modulation method and a multiplication result in the 16QAM modulation method in order to support adaptive modulation among a plurality of modulation methods with a single digital filter. And the multiplication result in the 64QAM modulation system is stored. Note that the symbol mapping data, which is input digital data of the BPSK modulation method and the 8PSK modulation method, matches a part of the symbol mapping data of the π / 4 shift QPSK modulation method (symbol points on the IQ coordinate plane match). Therefore, the multiplication results of the π / 4 shift QPSK modulation method can be used as the multiplication results of the BPSK modulation method and the 8PSK modulation method. Therefore, each ROM has storage areas for the multiplication results of the three modulation schemes, and these storage areas are classified according to the input digital data address A6 and address A7 as described below.

  Referring to FIG. 39 again, when the I / Q switching signal I / Q is “0”, the data for nine symbol sections of the I-phase symbol mapping data (I2, I1, I0) is stored for each symbol section. To the corresponding ROMs 150A to 150I. On the other hand, when the I / Q switching signal I / Q is “1”, the data of nine symbol sections of the Q-phase symbol mapping data (Q2, Q1, Q0) is stored in the corresponding ROM 150A˜ 150I.

  The 4-bit time information A0 to A3 given from the timing signal generation circuit 120 in the digital modulator shown in FIG. 20 and the 3-bit symbol mapping data of the corresponding symbol section become the address inputs A0 to A6 of the ROMs 150A to 150I. Further, the output of the AND circuit G154 having MODSEL0 and MODSEL1 as inputs becomes the most significant address input A7 of the ROMs 150A to 150I.

  FIG. 40 shows the relationship between the address inputs of the ROMs 150A to 150I and the output multiplication result of the modulation method.

  When the address input [A6, A7] is [0, 0], the multiplication results of BPSK, π / 4 shift QPSK and 8PSK modulation are output from each ROM, and the address input [A6, A7] is [1, 0]. In this case, the multiplication result of the 16QAM modulation method is output from each ROM, and when the address input [A6, A7] is [X, 1], the multiplication result of the 64QAM modulation method is output from each ROM.

  Other configurations and operations are the same as those of the digital filter 50 shown in FIG.

  As described above, according to the second embodiment of the present invention, adaptive modulation corresponding to the 8PSK modulation method and the 64QAM modulation method can be easily realized in addition to the modulation method corresponding to the first embodiment.

  In addition, since the digital modulator can be configured with only slight changes to the conventional digital modulator, an increase in circuit scale and complication associated with adaptive modulation can be avoided.

[Embodiment 3]
In the first embodiment and the second embodiment, the digital filter mounted on the digital modulator calculates the filter output in advance and stores it in the ROM, and obtains the output waveform by using the input data as an address. The configuration realized by is proposed.

  In addition to the ROM type filter, the digital filter is realized by a software filter realized by software processing using a digital signal processor (DSP), and by hardware using a shift register, a multiplier, and an adder. There is a transversal filter.

  In the present embodiment, a configuration is proposed in which a digital filter is realized by a transversal filter. In the digital modulator according to the present embodiment, the portions other than the digital filter are the same as those described in the first embodiment, and thus detailed description will not be repeated.

  FIG. 41 is a schematic block diagram showing a configuration of a digital filter included in the digital modulator according to the third embodiment of the present invention.

  Referring to FIG. 41, the digital filter includes a shift register including cascaded eight-stage delay elements D1, D2,... D8, nine multipliers M0, M1,. And an adder A for adding the results.

  The input digital data is sequentially input to the shift register every sampling period (symbol period), and is sequentially held in each delay element while being delayed by the sampling period. The input of the first stage and the output of each stage of the shift register form nine tap outputs of the shift register.

  Corresponding to these nine tap outputs, nine tap coefficients h0, h1,..., H8 respectively corresponding to values at nine sampling points (not shown) of the impulse response waveform shown in FIG. In advance.

  The memory circuit is composed of a ROM, for example, and stores tap coefficients h0, h1,... H8 having time information A0 to A3 given from the timing signal generating circuit 20 shown in FIG. The tap coefficients h0, h1,... H8 are each composed of 16 values corresponding to the 16-valued addresses A0 to A3. Therefore, the nine tap coefficients h0, h1,... H8 are sequentially read out in response to the time information A0 to A3 being counted from 0 to 16 in one sampling period, and the corresponding multipliers M0, M1. ... given to M8.

  Then, in a certain sampling period, nine tap outputs when input digital data is held in the eight delay elements D1 to D8 constituting the shift register, and nine predetermined tap coefficients h0, h1,. h8 is respectively multiplied by the corresponding nine multipliers M0, M1... M8. The obtained nine multiplication results are calculated by the adder A and supplied as the output of the digital filter in the current sampling period.

Then, in the next sampling period, the digital data held in the eight stages of delay elements D1 to D8 is shifted to the next stage, and in that state, nine tap outputs and nine predetermined taps as described above. Multiplication with a coefficient and addition of the multiplication results are performed.

  The digital data having Nyquist characteristics free from intersymbol interference based on the impulse response waveform shown in FIG. 16 is obtained by repeating the digital data holding, multiplying the tap output by the tap coefficient, and adding the multiplication results in the sampling period. A filter output is obtained.

  As described above, according to the third embodiment of the present invention, since the digital filter is configured by a transversal filter, the same configuration can be used regardless of which modulation method the input digital data is based on. be able to.

  Therefore, unlike the ROM type filters of the first and second embodiments, it is not necessary to have a ROM corresponding to each modulation method, so that the circuit configuration can be further simplified, and the conventional digital modulator Adaptive modulation can be realized without increasing the circuit scale.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram which shows the structure of the digital modulator according to Embodiment 1 of this invention. FIG. 2 is a circuit diagram showing a configuration of a timing signal generation circuit 20 shown in FIG. 1. FIG. 2 is a circuit diagram showing a configuration of a serial / parallel conversion circuit 30 shown in FIG. 1. It is a timing diagram for demonstrating the parallel data output in a 16QAM modulation system. It is a timing diagram for demonstrating the parallel data output in a (pi) / 4 shift QPSK modulation system. It is a timing diagram for demonstrating the parallel data output in a BPSK modulation system. FIG. 2 is a circuit diagram showing a configuration of a mapping circuit 40 shown in FIG. 1. It is a figure which shows arrangement | positioning of the symbol point by (pi) / 4 shift DQPSK modulation system. It is a truth table for demonstrating the mapping operation | movement in a (pi) / 4 shift QPSK modulation system. It is a truth table for demonstrating the mapping operation | movement in a (pi) / 4 shift QPSK modulation system. It is a truth table for demonstrating the mapping operation | movement in a 16QAM modulation system. It is a truth table for demonstrating the mapping operation | movement in a BPSK modulation system. It is a circuit diagram which shows the structure of the digital filter 50 shown in FIG. 3 is a circuit diagram showing a detailed configuration of a symbol mapping data storage circuit 51. FIG. FIG. 6 is a timing chart for explaining the operation of the symbol mapping data storage circuit 51. It is an impulse response waveform of a digital filter realizing Nyquist characteristics. It is a figure which shows the filter output waveform read from each of ROM50A-50I, and the synthetic | combination waveform obtained by adding these filter output waveforms. It is a circuit diagram which shows the structure of the mask circuits 50J-50R shown in FIG. FIG. 19 is a circuit diagram showing a configuration of a mask control circuit 53 that generates control signals for the mask circuits 50J to 50R in FIG. It is a block diagram which shows the structure of the digital modulator according to Embodiment 2 of this invention. It is a figure which shows the relationship between CLK1 which the timing signal generation circuit 20 outputs, and the mode selection signal MODSEL. FIG. 21 is a circuit diagram showing a configuration of a serial / parallel conversion circuit 130 shown in FIG. 20. It is a timing diagram for demonstrating the parallel data output in an 8PSK modulation system. It is a timing diagram for demonstrating the parallel data output in a 64QAM modulation system. FIG. 21 is a circuit diagram illustrating a configuration of a mapping unit for the π / 4 shift QPSK modulation method in the mapping circuit 140 illustrated in FIG. 20. FIG. 21 is a circuit diagram illustrating a configuration of a mapping unit for the 8PSK modulation method in the mapping circuit 140 illustrated in FIG. 20. FIG. 21 is a circuit diagram showing a configuration of a mapping unit for BPSK, 16QAM, and 64QAM modulation schemes in mapping circuit 140 shown in FIG. 20. FIG. 21 is a circuit diagram illustrating a configuration of a selection unit in the mapping circuit 140 illustrated in FIG. 20. It is a figure which shows the mapping operation | movement of the mapping part for (pi) / 4 shift QPSK modulation systems. FIG. 27 is a diagram illustrating a mapping operation of a mapping unit for the 8PSK modulation method illustrated in FIG. 26. It is a figure which shows the mapping operation | movement in the BPSK modulation system of the mapping part shown in FIG. It is a figure which shows arrangement | positioning of the symbol point in a 16QAM modulation system. It is a figure which shows the relationship between 4-bit parallel data and a symbol point in a 16QAM modulation system. It is a figure which shows the mapping operation | movement in 16QAM modulation system of the mapping part shown in FIG. It is a figure which shows arrangement | positioning of the symbol point in a 64QAM modulation system. It is a figure which shows the relationship between 6-bit parallel data and a symbol point in a 64QAM modulation system. It is a figure which shows the mapping operation | movement in the 64QAM modulation system of the mapping part shown in FIG. It is a figure which shows the relationship between the mode selection signal MODSEL and the symbol mapping data which the multiplexers 142-147 in the selection part shown in FIG. 28 select. It is a circuit diagram which shows the structure of the digital filter 150 shown in FIG. It is a figure which shows the relationship between the address input of ROM150A-150I shown in FIG. 39, and the multiplication result of the modulation system output. It is a schematic block diagram which shows the structure of the digital filter contained in the digital modulator according to Embodiment 3 of this invention. It is a figure which shows arrangement | positioning of the symbol point by the (pi) / 4 shift QPSK modulation system on IQ plane coordinate. It is a figure which shows arrangement | positioning of the symbol point by 16QAM modulation system on IQ plane coordinate. It is a figure which shows arrangement | positioning of the symbol point by the BPSK modulation system on an IQ coordinate plane.

Explanation of symbols

  10, 110 CPU, 20 timing signal generation circuit, 21 counter circuit, 22 multiplexer, 23, 31-38, 55A-55D, 66-74, 131A-138A, 131B-136B, 138B flip-flop, 30, 130 serial / parallel Conversion circuit, 40,140 mapping circuit, 41 4-bit parallel register, 44 adder, 45-48, 56-65, 142-147 multiplexer, 50,150 digital filter, 50A-50I, 150A-150I ROM, 50J-50R Mask circuit, 51, 151 Symbol mapping data storage circuit, 52 Adder, 53 Mask control circuit, 54A-54D 8-bit shift register, 80 Digital / analog converter, 90 LPF, G20, G43, G4 , G143, G146 NOT circuit, G40 EXOR circuit, G41, G42, G44, G45, G141, G142, G144, G145 EXNOR circuit, G54-G57, G154 AND circuit, D1-D8 delay element, M0-M8 multiplier, A Adder.

Claims (7)

A digital modulator capable of supporting a plurality of modulation schemes having different multilevel values,
Upper processor means for generating a digital baseband signal;
Means for serial-parallel conversion of the baseband signal for each successive plurality of bits;
Mapping means for uniquely giving symbol mapping data composed of orthogonal in-phase and orthogonal phase for each of a plurality of consecutive bits;
Digital filter means for band-limiting the in-phase and quadrature-phase symbol mapping data and performing multiplication with a carrier signal in a time-division multiplexed manner;
Means for converting the output of the digital filter means into an analog modulation signal,
The upper processor means is
Means for generating a mode selection signal for selecting one modulation scheme from the plurality of modulation schemes;
The serial-to-parallel conversion means performs serial-to-parallel conversion for each of the plurality of bits corresponding to the number of bits that can be transmitted in the modulation method having the largest multi-level number among the plurality of modulation methods
When the mapping means receives the mode selection signal, the mapping means gives the symbol mapping data corresponding to the modulation scheme specified by the mode selection signal to the plurality of consecutive bits. Timing signal generating means for generating a first clock signal having a speed equal to or higher than the data rate of the modulation scheme specified by the mode selection signal and a second clock signal equal to the symbol period;
The serial-parallel conversion means includes
In response to the first clock signal, the baseband signal is latched, and in response to the second clock signal, the plurality of bits are serial-parallel converted and output,
The mapping means includes
The digital modulator according to claim 1, wherein the symbol mapping data is uniquely provided by latching the plurality of bits in response to the second clock signal. The timing signal generating means includes
3. The digital modulator according to claim 2, further comprising a switching signal generating means for switching said digital filter means between said in-phase symbol mapping data and said quadrature phase symbol mapping data in a time division multiplexed manner. The digital filter means includes
Means for storing each of the in-phase and quadrature-phase symbol mapping data in a time-division multiplexed manner corresponding to a plurality of symbol intervals in response to the switching signal;
A plurality of storage means provided corresponding to the plurality of symbol sections, each storing a multiplication result of symbol data passing through a predetermined impulse response waveform and a corresponding carrier wave signal;
Means for adding the multiplication results read from the plurality of storage means,
The digital modulator according to claim 3, wherein each of the plurality of storage units stores a plurality of multiplication results corresponding to each of the plurality of modulation schemes.   5. Each of the plurality of storage units stores a plurality of multiplication results corresponding to each of the plurality of modulation schemes, using the mode selection signal or a signal based on the mode selection signal as an upper address. Digital modulator. The upper processor is
Means for generating an instruction signal instructing rising and falling of the baseband signal in burst transmission;
The digital filter means includes
Output mask means for selectively reading out the multiplication results from the plurality of storage means;
6. The digital modulator according to claim 5, further comprising mask control means for controlling the output mask means in response to the instruction signal. The digital filter means includes
Shift register means having a predetermined number of tap outputs and holding each of the in-phase and quadrature-phase symbol mapping data sequentially delayed by a symbol period;
Memory means for holding tap coefficients corresponding to the predetermined number of sampling points set on a desired impulse response waveform;
Multiplying means for multiplying each of the predetermined number of tap outputs of the shift register means with each of the held tap coefficients;
The digital modulator according to claim 3, further comprising addition means for adding the multiplication results.

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