JP2005123965A - Solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CCD type solid-state image pickup device including an on-chip substrate bias control circuit for controlling a plurality of substrate biases. <P>SOLUTION: The CCD type solid-state image pickup device includes: a first conductive semiconductor substrate; a second conductive well formed on the semiconductor substrate; a number of first conductive charge accumulation regions and a substrate bias control circuit matrix-disposed on the well; a plurality of first conductive vertical charge transfer paths disposed along with the columns of the charge accumulation regions in the well; a first conductive horizontal charge transfer path which is coupled to one end of the vertical charge transfer paths for receiving and transferring charges from the vertical charge transfer paths; and a substrate bias control circuit including a plurality of resistor ladders wherein a plurality of resistors are connected in series, a fuse element connected in parallel with at least a part of the plurality of resistors and a switch circuit for selecting any one of the plurality of resistor ladders, the substrate bias control circuit being formed on the semiconductor substrate and capable of regulating a plurality of predetermined bias voltages applied to the first conductive semiconductor substrate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a CCD solid-state image pickup device, and more particularly to a CCD solid-state image pickup device having a shutter function for removing a substrate and capable of changing the number of display pixels according to a mode.

  In a CCD type solid-state imaging device, a p-type well is formed on an n-type silicon substrate, n-type charge storage regions constituting photoelectric conversion elements are formed in a matrix in the p-type well, and each column of the charge storage region is formed. An n-type vertical transfer path is formed along the vertical charge transfer path, and is coupled to one end of the vertical charge transfer path to form an n-type horizontal charge transfer path. The p-type well forms a potential barrier with respect to the n-type charge storage region. When a high voltage pulse of 20-30 V is applied to the n-type substrate, the potential barrier formed by the p-type well disappears, and the charge accumulated in the charge accumulation region can be extracted to the substrate (substrate extraction shutter).

  In a normal imaging state, a substrate bias of about 10-15 V is applied to the substrate so that the charge accumulation region has a desired charge accumulation capability (saturated charge amount). When electron-hole pairs are generated in response to incident light, electrons are accumulated in the n-type charge accumulation region. The amount of accumulated charge, and thus the output voltage, increases almost linearly in proportion to the amount of incident light, but eventually the rate of increase decreases and does not increase beyond a certain value (saturated charge amount).

  The saturation charge is a function of the substrate bias. Under a predetermined substrate bias, each charge storage region ideally exhibits a predetermined saturation charge amount. The vertical charge transfer path and the horizontal charge transfer path are designed so that a saturated charge amount can be transferred.

  Many CCD solid-state imaging devices have a movie mode for monitoring. In the movie mode, the number of display pixels is usually reduced to facilitate high-speed operation. In order to reduce the number of display pixels, thinning readout is performed to read out signal charges from only pixels in some rows to the vertical charge transfer path, or part of the signal charges once read out to the vertical charge transfer path is transferred horizontally. It can also be discarded when transported to the road.

  When thinning-out reading is performed, charges remain in the charge accumulation region from which charges have not been read out. Therefore, unnecessary charges need to be discarded by high-speed reading, a substrate removal shutter, or the like. In addition, the reproduced image with the read pixels reduced uses only a part of the light incident on the light receiving region, and thus it is difficult to avoid the deterioration of the image quality.

  In order to eliminate the charge discarding step and obtain a monitor screen with better image quality, it has been proposed to reduce the number of display pixels by reading out signal charges from all pixels and performing addition. The addition of the signal charge can be performed in the vertical charge transfer path and the horizontal charge transfer path.

JP 2000-350099 A JP 2001-57419 A JP 2002-64833 A JP 2002-112119 A

  When signal charges are added in the vertical charge transfer path and the horizontal charge transfer path, the amount of charge increases, so that there is a possibility that the charges overflow from the vertical charge transfer path and the horizontal charge transfer path. In order to prevent this phenomenon, in the monitor mode (movie mode), it is preferable to reduce the saturation charge amount in the charge accumulation region. In order to reduce the saturation charge amount, the substrate bias may be increased and the potential barrier lowered. A CCD solid-state imaging device that changes the substrate bias according to the operation mode has also been proposed.

JP 2000-101060 A

  The saturation charge amount in the charge accumulation region is affected by the manufacturing process of the CCD type solid-state imaging device, and exhibits some variation. However, in the region where the characteristics are linear before the output voltage with respect to the incident light quantity reaches saturation, the characteristics of the output voltage with respect to the incident light quantity are uniform regardless of the pixels. In order to ensure that a large number of pixels have uniform characteristics, the substrate bias is selected so that each pixel has a saturation charge amount equal to or higher than the desired saturation charge amount, and the output voltage is clipped at a certain level. In order to realize a desired saturation charge amount, the characteristics of the charge storage region are examined, and the substrate bias is determined based on the result.

  Conventionally, the substrate bias is determined based on the result of examining the characteristics of the solid-state imaging device after manufacturing. When two types of substrate bias are used, two voltages having a predetermined voltage difference such as 1 V are selected and supplied from the outside.

  In particular, for CCD digital cameras with built-in portable telephones, it is desirable to incorporate a substrate bias adjustment circuit on-chip in a solid-state imaging device in order to simplify the manufacturing and adjustment processes up to shipment and facilitate design changes. It is rare.

  An object of the present invention is to provide a CCD solid-state imaging device having on-chip a substrate bias adjustment circuit for adjusting a plurality of substrate biases.

  Another object of the present invention is to provide a CCD type solid-state imaging device having an on-chip substrate bias adjustment circuit that has a substrate removal shutter function, can change the number of display pixels depending on the mode, and adjusts a plurality of substrate biases. Is to provide.

  According to one aspect of the present invention, a first conductivity type semiconductor substrate, a second conductivity type well formed in the semiconductor substrate, and a plurality of first electrodes formed in the well and arranged in a matrix. A conductive type charge storage region; a plurality of first conductive type vertical charge transfer paths formed in the well and disposed along each column of the charge storage area; and one of the plurality of vertical charge transfer paths. A first conductive type horizontal charge transfer path coupled to the end for receiving and transferring charges from the vertical charge transfer path; and a predetermined plurality of applied to the first conductive type semiconductor substrate formed on the semiconductor substrate. A substrate bias adjustment circuit capable of adjusting a bias voltage, a plurality of resistor ladders each having a plurality of resistors connected in series, and a fuse element connected in parallel to at least a part of the plurality of resistors, The plurality of resistance ladders A substrate bias adjustment circuit and a switching circuit for-option, the CCD type solid-state imaging device having provided.

  By selectively cutting the fuse element and adjusting each of the plurality of resistance ladders, a desired plurality of substrate biases can be adjusted on-chip.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1A schematically shows a planar configuration of a CCD solid-state imaging device. A light receiving region 1 is demarcated by a p-type well at the center of the semiconductor chip 10, and a large number of n-type charge storage regions 5 are arranged in a matrix in the light receiving region. An n-type vertical charge transfer path 6 is disposed along each column of the charge accumulation region. An n-type horizontal charge transfer path 3 is coupled to one end of the plurality of vertical charge transfer paths 6. The output of the horizontal charge transfer path 3 is amplified by the output circuit 4 and output to the outside.

  On the right side of the light receiving region 1, a drive circuit unit 2 having a row drive signal wiring and the like is formed. A substrate bias adjustment circuit 7 capable of adjusting a plurality of substrate bias voltages is formed on the left side of the light receiving region 1. The substrate bias adjustment circuit 7 includes a plurality of resistance ladders as will be described later, and selects the resistance value of the resistance ladder by selectively cutting fuse elements connected in parallel to at least a part of the resistance ladder. The substrate bias adjustment circuit 7 also includes a transistor formed in the semiconductor chip 10 and is used as a switch.

  Bonding pads 9 are disposed on the upper and lower sides of the semiconductor chip 10. On the left side of the semiconductor chip 10, a pad 8 is disposed to apply a probe pin to examine the characteristics when examining the characteristics of the solid-state imaging device and to apply a voltage for cutting the fuse element.

  FIG. 1B schematically shows the configuration of a CCD camera. A mechanical shutter MS is disposed behind the imaging lens L, and a shutter SH is disposed on the upper surface or the front surface of the camera. Behind the imaging lens L, a chip 10 of a CCD type solid-state imaging device is disposed. The mode selector SEL selects operation modes such as dark field flash photography, backlight flash photography, and pixel number selection. A control circuit CTL is provided in the camera and controls the operation mode of the camera based on signals from the mode selector SEL, the shutter SH, and the like.

  For example, the shutter button SB has a half-press switch and a full-press switch. When the shutter button is half-pressed, imaging preparation operations such as automatic exposure adjustment and automatic ranging are performed. When the shutter button is fully pressed, the monitor mode is switched to the imaging mode, the driving of the solid-state imaging device 10 is switched, and the mechanical shutter MS is controlled to perform imaging. In the monitor mode and the imaging mode, the saturation charge amount in the charge accumulation region changes.

  FIG. 2A shows a configuration example of the substrate bias adjustment circuit 7. A plurality of resistance ladders 36-1, 36-2, 36-3 are connected in parallel between the power supply terminal 30 and the ground terminal via a reference resistor R1. Each of the resistance ladders 36-1, 36-2, and 36-3 is connected in series with switches 37-1, 37-2, and 37-3 formed of transistors. The interconnection point between the reference resistor R1 and the resistor ladder is connected to the emitter follower circuit 32, and the output of the emitter follower circuit is applied to the n-type substrate.

  For example, in the resistor ladder 36-1, resistors R11, R12, R13, and R14 are connected in series, and are connected to the switch 37-1 via the protective resistor R15. The resistor is formed of, for example, a polycrystalline silicon resistor on a silicon oxide field insulating film. A fuse F11 is connected in parallel to the resistor R11, a fuse F12 is connected in parallel to the resistor R12, and fuses F13 and F14 are connected in parallel to the resistors R13 and R14. The fuse can be formed of, for example, a polycrystalline silicon resistor or a metal resistor whose resistance value is significantly lower than the corresponding resistor.

  Both ends of each fuse are connected to pads P11 to P15, and the fuse can be selectively cut by selectively applying a voltage. Note that the fuse can be cut by laser beam irradiation or the like instead of voltage application.

  The resistance ladders 36-2 and 36-3 have the same configuration as the resistance ladder 36-1. The resistors belonging to the resistor ladder 36-2 are labeled as R21, R22, R23, R24, and R25. Similarly, the fuses are labeled as F21, F22, F23, and F24. The pads are denoted as P21, P22, P23, P24, and P25.

  In the resistor ladder 36-3, the resistors are labeled R31, R32, R33, R34, R35, the fuses are labeled F31, F32, F33, F34, and the pads are labeled P31, P32, P33, P34, P35. .

  In the state before adjustment, the resistance of the resistance ladder is short-circuited by a fuse except for the protective resistors R15, R25, and R35.

  The voltage divided by one of the reference resistor R1 and the resistor ladder 36-1, 36-2, 36-3 is applied to the semiconductor substrate via the source follower circuit 32, and the saturation charge amount in the charge accumulation region is adjusted. To do. The pad 33 is connected to the output of the emitter follower circuit 32. The substrate bias can be monitored with this pad. An external bias voltage may be introduced from the pad 33.

  FIG. 2B is a table showing the connection state of the substrate bias adjustment circuit according to the mode. In mode M1, the transistor 37-1 is turned on, and the resistor ladder 36-1 is connected between the reference resistor R1 and the ground potential. In mode M2, the transistor 37-2 is turned on, and the resistor ladder 36-2 is connected between the reference resistor R1 and the ground potential. In mode M3, the transistor 37-3 is turned on, and the resistor ladder 36-3 is connected between the reference resistor R1 and the ground potential.

  At the time of adjustment, for example, a substrate bias voltage selected from the ground side terminal (or power supply terminal) or the pad 33 is applied. The entire field is imaged in a bright field, and the saturation charge amount of each charge storage region is measured. The substrate bias voltage is changed, the saturation charge amount in each case is measured, and what voltage should be applied as the substrate bias is determined to obtain the desired saturation charge amount.

  When the reference resistor R1 and the resistance ladder 36-1 are connected between the power supply terminal 30 and the ground terminal, it is determined what resistance is selected as the resistance value of the resistance ladder 36-1, and then the fuses F11, F12, By selectively cutting F13 and F14, a desired resistance value is realized as the resistance ladder 36-1.

  For example, by setting R12 = 2R11, R13 = 2R12, R14 = 2R13, and R15 = 2R14, a desired resistance value can be selected from 15 types of resistors R11 to 15R11. The fuses F11, F12, F13, and F14 are selectively cut to realize a desired resistance value. For example, voltage 0 and voltage Vf are applied to both ends of the fuse to be cut, and voltage Vf / 2 is applied to the other pads. In this way, for example, the resistance value for realizing the substrate bias in the monitor mode is adjusted.

  In mode M2, the transistor 37-2 is turned on and the resistance value of the resistance ladder 36-2 is adjusted. For example, the resistance value is selected so as to realize an appropriate substrate bias in the still imaging mode.

  The operation mode is not limited to the monitor mode and the imaging mode. Any other mode can be adopted. Mode M3 is another mode. The transistor 37-3 is selected and the substrate bias of the resistance ladder 36-3 is adjusted. Other modes include, for example, a shooting mode in which the number of pixels is reduced for transfer via a communication line.

  Thus, by using a plurality of resistance ladders provided with switches, it is possible to adjust a plurality of substrate bias voltages according to the operation mode. The number of modes for changing the substrate bias is not limited to two or three, but may be four or more.

  3A and 3B are a plan view and a cross-sectional view of the light receiving unit of the solid-state imaging device.

  FIG. 3A shows a portion where the charge accumulation regions 5 and the vertical charge transfer paths 6 are alternately arranged in the horizontal direction. Transfer electrodes 14 and 15 are disposed above the vertical charge transfer path 6. Between the charge storage region 5 and the vertical charge transfer path 6, a gate region 18 for transferring charges is formed.

  FIG. 3B schematically shows a cross-sectional structure taken along line IIB-IIB in FIG. A p-type well 12 is formed on the surface portion of the n-type silicon substrate 11. An n-type region 5 constituting a large number of charge storage regions is formed in the p-type well 12, and a vertical charge transfer path 6 is formed along each column of the charge storage region 5. An n-type region 13 for applying a bias to the substrate 11 is formed outside the p-type well 12. The output voltage of the substrate bias voltage adjustment circuit 7 is applied to the n-type region 13.

  A first layer polycrystalline silicon electrode 14 and a second layer polycrystalline silicon electrode 15 are formed above the vertical charge transfer path 6 to constitute a transfer electrode. Above these electrodes, a light-shielding film 16 such as W is formed via an insulating film, and an opening is formed above the charge storage region 5. A planarization insulating layer 17 is formed on the light shielding film 16, and a color filter 18 is formed thereon. A microlens 20 is disposed on the color filter 18 via a planarizing film 19.

  FIG. 3C schematically shows the potential distribution of the charge accumulation region 5, the p-type well 12, and the n-type substrate 11. The charge storage region 5 forms a potential well, and the p-type well 12 forms a potential barrier. When a positive high voltage is applied to the substrate 11, the potential of the substrate 11 is lowered and the potential barrier of the p-type well 12 is adjusted.

  A curve p1 is, for example, a potential distribution in the still photographing mode, and has a high saturation charge amount. A curve p2 is a potential distribution in the monitor mode, for example, and the saturation charge amount is reduced. If the amount of saturation charge in each charge storage region 5 is reduced, the signal charge is transmitted from the vertical charge transfer path 6 and the horizontal charge transfer path 3 even if the signal charge is added in the vertical charge transfer path 6 and the horizontal charge transfer path 3. It can prevent overflowing.

  FIG. 3D is a graph showing the relationship between the output voltage due to charges accumulated in each charge accumulation region and the amount of incident light. A curve v indicates a change of the output voltage with respect to the light amount. As the amount of light increases, the output voltage increases almost linearly. When the amount of light increases more than a certain amount, the output voltage does not increase any more. The charge accumulated at this time is the saturation charge amount.

  The saturation charge amount varies to some extent due to variations in the manufacturing process of the solid-state imaging device. For this reason, the output voltage (saturation voltage) also varies. When imaging is performed with a difference in the amount of saturation charge, for example, a white-level reproduced image of the same color becomes bright and dark, and the image quality deteriorates. Therefore, clipping is performed so that the output voltage is saturated with a certain amount of light. Each charge storage region is selected so that signal charges until the clip voltage is reached can be stored.

  Thus, a uniform image can be realized by keeping the saturation charge amount constant. For this purpose, it is necessary to select an appropriate substrate bias voltage. By realizing an appropriate substrate bias voltage by the substrate bias adjustment circuit shown in FIG. 2A, uniform operation is guaranteed.

  In the above-described embodiment, a plurality of resistance ladders are arranged in parallel to adjust a desired plurality of substrate bias voltages. The method for adjusting the substrate bias voltage is not limited to the above.

  FIG. 4 shows another example of a substrate bias voltage adjustment circuit. In this configuration, no switch is connected to the resistance ladder 36-1. The resistance ladder 36-1 is always connected between the power supply terminal 30 and the ground terminal.

  FIG. 4B shows the states of the switches 37-2 and 37-3 in the three modes M1, M2, and M3. In the mode M1, the switches 37-2 and 37-3 are off, and only the resistance ladder 36-1 is connected in series to the reference resistor R1.

  In the mode M2, the switch 37-2 is turned on, and the parallel connection of the resistor ladder 36-1 and the resistor ladder 36-2 is connected in series with the reference resistor R1. In the mode M3, the switches 37-2 and 37-3 are both turned on, and the resistance ladders 36-1, 36-2, and 36-3 are connected in parallel and connected in series to the reference resistor R1.

  The resistance ladder 36-1 achieves the highest resistance value, and the resistance ladders 36-2 and 36-3 serve to lower the resistance value. Three types of resistance values are realized by the modes M1, M2, and M3, and desired voltage division is performed. The resistance value of mode M3 is the lowest, and the resistance value of mode M2 is an intermediate value between the resistance values of mode M1 and mode M3.

  FIG. 4C shows another example of connection of a resistance ladder. Modes M1 and M2 are the same as in the case of FIG. In mode M3, only switch 37-3 is turned on. In this case, a fourth mode can be set in which both the switch 37-2 and the switch 37-3 are turned on.

  In the substrate bias adjustment circuit of FIG. 4A, the resistor ladder 36-1 is always connected, and the resistor ladders 36-2 and 36-3 are used to reduce the resistance value of the divided resistors. Since one transistor constituting the switch is reduced, the configuration is simplified and the occupied area can be reduced.

  It is not necessary that the resistance ladder 36-1 and the resistance ladders 36-2 and 36-3 have the same standard, and the number of resistances of the resistance ladders 36-2 and 36-3 may be reduced from the resistance ladder 36-1. It will be possible.

  FIG. 5A shows another configuration example of the substrate bias adjustment circuit. In this configuration, the protective resistance R15 included in the resistance ladder 36-1 is also used in common for the resistance ladders 36-2 and 36-3. For this reason, an interconnection point between the resistors R15 and R14 is also introduced into the resistance ladders 36-2 and 36-3, and the resistance ladders 36-2 and 36-3 are provided between the interconnection point and the reference resistor R1. Is connected. The function of the circuit is the same as that in FIG. 4A, but the number of resistors can be reduced and the configuration can be simplified.

  5B and 5C show operation modes of the substrate bias adjustment circuit shown in FIG. These operation modes are the same as those in FIGS. 4B and 4C.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

  It can be used for a CCD type solid-state imaging device and a CCD type camera. In particular, it is suitable for application to a CCD solid-state imaging device with a built-in mobile phone.

1 is a plan view illustrating a planar configuration of a CCD solid-state imaging device according to an embodiment of the present invention, and a cross-sectional view schematically illustrating a configuration of a CCD camera. FIG. 2 is an equivalent circuit diagram and a table showing a configuration and an operation mode of the substrate bias adjustment circuit shown in FIG. 2A is a plan view showing a planar configuration of the solid-state imaging device shown in FIG. 1A, a sectional view showing a sectional structure, and a graph showing characteristics. FIG. It is the table | surface which shows the equivalent circuit schematic and operation mode of the board | substrate bias adjustment circuit by other Examples of this invention. It is a table | surface which shows the equivalent circuit schematic and operation mode of the board | substrate bias adjustment circuit by other Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Light reception area | region 2 Drive circuit part 3 Horizontal charge transfer path 4 Output circuit 5 Charge storage area 6 Vertical charge transfer path 7 Substrate bias adjustment circuit 8, 9 Pad 10 Semiconductor chip 11 n-type silicon substrate 12 p-type well 13 (Substrate bias application) N-type region 14 First layer polycrystalline silicon electrode 15 Second layer polycrystalline silicon electrode 16 Light shielding film 17 Flattening insulating layer 18 Color filter 19 Flattening film 20 Microlens L Imaging lens MS Mechanical shutter SH Shutter CTL control Circuit 30 Power supply voltage terminal 32 Emitter follower circuit 36-1, 36-2, 36-3 Resistance ladder 37-1, 37-2, 37-3 Transistor (switch)
P pad F fuse R resistance p1, p2 potential distribution v output voltage characteristics

Claims (5)

A first conductivity type semiconductor substrate;
A second conductivity type well formed in the semiconductor substrate;
A plurality of first conductivity type charge storage regions formed in the well and arranged in a matrix;
A plurality of first conductivity type vertical charge transfer paths formed in the well and disposed along each column of the charge storage region;
A horizontal charge transfer path of a first conductivity type coupled to one end of the plurality of vertical charge transfer paths and receiving and transferring charges from the vertical charge transfer paths;
A substrate bias adjustment circuit formed on the semiconductor substrate and capable of adjusting a plurality of predetermined bias voltages applied to the semiconductor substrate of the first conductivity type, wherein a plurality of resistors are connected in series. A substrate bias adjustment circuit comprising: a resistance ladder; a fuse element connected in parallel to at least some of the plurality of resistors; and a switch circuit for selecting the plurality of resistance ladders;
CCD type solid-state imaging device. The CCD solid-state imaging device according to claim 1, wherein the switch circuit includes a switch connected to each of the plurality of resistance ladders. 2. The CCD solid-state imaging device according to claim 1, wherein the switch circuit includes a switch connected to each of the remaining resistance ladders without connecting a switch to one of the plurality of resistance ladders. A first conductivity type semiconductor substrate; a second conductivity type well formed in the semiconductor substrate; a plurality of first conductivity type charge storage regions formed in the well and arranged in a matrix; A plurality of first-conductivity-type vertical charge transfer paths formed in the well and disposed along each column of the charge storage region, and coupled to one end of the plurality of vertical charge transfer paths, the vertical charge transfer A first conductivity type horizontal charge transfer path for receiving and transferring charges from the path, and a substrate formed on the semiconductor substrate and capable of adjusting a plurality of predetermined bias voltages applied to the first conductivity type semiconductor substrate. A bias adjustment circuit, wherein a plurality of resistance ladders each having a plurality of resistors connected in series, a fuse element connected in parallel to at least a part of the plurality of resistors, and the plurality of resistance ladders are selected. For switch times A CCD-type solid-state imaging device having a substrate bias adjustment circuit with bets;
Mode switching means for switching between at least the monitor mode and the still imaging mode and automatically switching the switch circuit;
CCD type camera having The CCD camera according to claim 4, wherein the mode switching means includes a shutter.

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