JP2005123271A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device wherein adhesive strength between a chip which is processed in the former process of a semiconductor manufacturing process and a substrate, property of the chip after substrate adhesion is equalized, and sufficient adhesive strength to the substrate can be obtained. <P>SOLUTION: Post electrodes 2 are formed on a semiconductor substrate 1 in which an integrated circuit is formed. Resin 3 such as epoxide resin is spread so that the post electrodes 2 and the surface of the semiconductor substrate 1 are covered. The surface of the resin 3 is ground by mechanical grinding which uses a back grind apparatus or the like, and tops of the post electrodes 2 are exposed on the surface. The resin 3 is etched by using chemicals such as H<SB>2</SB>SO<SB>4</SB>, side walls of the post electrodes 2 are exposed, and plating 4 is stuck on the exposed parts. Dicing of a wafer is performed to divide it into each chip, and a packaged semiconductor device is obtained. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a semiconductor device in WL-CSP (Wafer Level Chip Size Package). In particular, the present invention relates to a method of manufacturing a semiconductor device in which the bonding strength of the chip to the substrate and the characteristics of the chip when the chip is bonded to the substrate are improved in mounting the semiconductor device on the substrate.

  The semiconductor manufacturing process is largely divided into a pre-process for forming an integrated circuit (IC) on a wafer and a post-process for packaging a chip processed in the pre-process. There is WL-CSP as a technique used in the subsequent process. WL-CSP is a space-saving package that realizes the ultimate miniaturization, thickness reduction, and weight reduction, in which the package size is the same real chip size as the chip size. In WL-CSP, batch processing can be performed in a wafer state in the pre-process and the post-process.

  FIG. 3 shows a first method as a method for manufacturing a semiconductor device in a conventional WL-CSP. In the figure, each process is illustrated as a cross-sectional view. An integrated circuit is formed on the semiconductor substrate 1 in advance in the previous process, but is not shown in FIG. A photosensitive film is applied onto the semiconductor substrate 1, and exposure and development are performed to selectively form openings. And after making copper adhere to an opening part by electroplating, the photosensitive film is removed and the post electrode 2 for electrical connection with the exterior is formed.

Subsequently, in order to protect the post electrode 2 and the semiconductor substrate 1 from mobile ions such as alkali metal ions and moisture (humidity), a resin 3 such as an epoxy resin is applied so as to cover the surface of the post electrode 2 and the semiconductor substrate 1. When applied, the structure shown in FIG. 3A is formed. When the resin 3 is etched using a chemical solution such as H ₂ SO ₄ to expose the top of the post electrode 2, the structure shown in FIG. 3B is formed.

  Subsequently, when the chip is soldered to the substrate, in order to improve the wettability of the solder and increase the adhesion strength with the solder, the top and side portions of the exposed post electrode 2 are plated. When metal such as gold and nickel is attached to the post electrode 2, the structure shown in FIG. 3C is formed. At this time, plating is selectively performed only on the post electrode 2. Although not shown, the wafer is subsequently diced and divided into individual chips to complete a packaged semiconductor device. Each semiconductor device is soldered on a printed circuit board, for example. In this method, the side wall of the post electrode 2 is also plated, so that there is an advantage that a high adhesive force can be obtained when the chip is soldered to the substrate.

  There is also a second method in which the resin 3 is not etched. In this method, after the structure similar to that shown in FIG. 3A is formed, the surface of the resin 3 is polished by mechanical grinding using a back grinding apparatus or the like to expose the top of the post electrode 2 on the surface. At the same time, the height of the post electrode 2 is made uniform. Subsequently, as in the first method, metal is attached to the top of the post electrode 2 by plating, and dicing and soldering are performed.

  The semiconductor device manufactured by the above manufacturing method has high utility value as a semiconductor device for an electronic device that is required to be reduced in size and thickness. One example is a discrete semiconductor device such as a diode / transistor or a semiconductor integrated circuit. For example, when a p-type Si substrate is used as the semiconductor substrate 1 in FIG. 3 and impurities are implanted into the surface thereof to selectively form an n-type region, a lateral pn junction is formed. Then, post electrodes are formed on the p-type and n-type regions, respectively, and packaging is performed by the above-described method, thereby completing the diode.

In Patent Document 1, as in the first method described above, a post electrode is formed on a semiconductor substrate, the semiconductor substrate and the surface of the post electrode are covered with an insulating film, and then the insulating film is etched to post. A method of connecting a semiconductor device that exposes an electrode is described. In Patent Document 2, as in the second method described above, a post electrode is formed on a semiconductor substrate, the semiconductor substrate and the post electrode are covered with a fluororesin, and then the surface of the fluororesin is polished. A method for manufacturing a semiconductor device in which a post electrode is exposed is described.
JP 10-340923 A JP-A-53-83462

  However, in the first method described above, the post electrode tends to be high at the wafer peripheral portion where the electric field density becomes high during electrolytic plating, and tends to be low at the center portion of the wafer, and the height of the post electrode is not uniform. Therefore, when the chip is soldered, there is a problem that a difference in the adhesive strength of the chip occurs depending on the height of the post electrode. In addition, since the chip receives a stress corresponding to the height of the post electrode, the resistance of the chip (for example, Si) changes according to the stress, resulting in a difference in the characteristics of the chip, and the yield is not stable. was there. In the second method, the height of the post electrode can be made uniform, but since the plating is performed only on the top of the post electrode, sufficient adhesion strength is obtained when the chip is soldered to the substrate. There was a problem that could not be obtained.

  The present invention has been made in view of the above-described problems, and uniformizes the bonding strength between the semiconductor device and the substrate and the characteristics of the chip after bonding to the substrate, and obtains sufficient bonding strength to the substrate. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of performing

  The present invention has been made to solve the above problems, and the invention according to claim 1 includes a step of forming a post electrode on a semiconductor substrate, and a protective film for protecting the semiconductor substrate and the post electrode. Forming on the semiconductor substrate, polishing the protective film until the post electrode is exposed, and etching the protective film to expose a side wall of the post electrode. A method for manufacturing a semiconductor device.

  According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, after the step of etching the protective film to expose the side wall of the post electrode, the surface of the post electrode is subjected to a plating process. The method further includes a step.

  According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first or second aspect, in the step of etching the protective film to expose a side wall of the post electrode, the protection is performed using a chemical solution. The film is etched.

  According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first or second aspect, in the step of etching the protective film to expose the side wall of the post electrode, dry etching using plasma And etching the protective film.

  According to this invention, a post electrode and a protective resin film are formed on a semiconductor substrate, the resin film is polished until the post electrode is exposed, the protective film is subsequently etched, and the exposed post electrode surface is plated. Since the treatment is performed, the height of the post electrode becomes uniform, and the exposed sidewall of the post electrode is also plated. Therefore, it is possible to obtain an effect that the bonding strength between the semiconductor device and the substrate and the characteristics of the chip after bonding to the substrate can be made uniform and sufficient bonding strength to the substrate can be obtained.

  The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 is a schematic process diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, each process is illustrated as a cross-sectional view. In the figure, reference numeral 1 denotes a semiconductor substrate such as silicon. Note that an integrated circuit is formed in advance on the semiconductor substrate 1 in the previous step of the semiconductor manufacturing process, but is not shown in FIG. A photosensitive film is applied onto the semiconductor substrate 1, and exposure and development are performed to selectively form openings. A photoresist may be used instead of the photosensitive film.

  Then, after making copper adhere to an opening part by electroplating, the photosensitive film is removed and the post electrode 2 for electrical connection with the outside is formed. The height of the post electrode 2 is, for example, about 100 μm. Then, in order to protect the post electrode 2 and the semiconductor substrate 1 from mobile ions such as alkali metal ions and moisture (humidity), a resin 3 such as an epoxy resin is applied so as to cover the surface of the post electrode 2 and the semiconductor substrate 1. Then, the structure shown in FIG. 1A is formed. Note that a metal such as gold, nickel, or palladium may be used as the post electrode 2. Further, a polyimide resin may be used as the resin 3.

  In the application of the resin 3, a liquid resin is quantitatively dropped onto the semiconductor substrate 1, and spin coating is performed using a spinner (rotation speed: 1000 rpm to 3000 rpm). After the application, the resin 3 is pre-baked on a hot plate at 80 ° C. for 2 hours, followed by baking at 150 ° C. for 3 to 6 hours to cure the resin 3. The rotation speed of the spinner and the temperature / time when the resin 3 is baked are merely examples, and the present invention is not limited thereto. As a method for forming the resin 3, a dispenser or a printing technique may be used instead of the above-described spinner. Further, regarding the baking of the resin 3, a clean oven or the like may be used instead of the hot plate.

  Subsequently, when the surface of the resin 3 is polished by mechanical grinding using a back grinding apparatus or the like, and the top of the post electrode 2 is exposed to the surface, the structure shown in FIG. 1B is formed. Note that mechanical / chemical polishing using a CMP (Chemical Mechanical Polishing) apparatus may be performed as polishing of the resin 3.

Subsequently, when the resin 3 is etched using a chemical solution such as H ₂ SO ₄ to expose the side wall of the post electrode 2, the structure of FIG. 1C is formed. The height of the exposed portion of the post electrode 2 is, for example, 10 to 15 μm. Subsequently, when the chip is soldered to the substrate, in order to improve the wettability of the solder and increase the adhesion strength with the solder, the top and side portions of the exposed post electrode 2 are plated. When a metal such as gold and nickel is attached to the post electrode 2, the structure shown in FIG. At this time, plating is selectively performed only on the post electrode 2. The thickness of the metal attached to the post electrode 2 by the plating process is, for example, about 1 μm. Although not shown, the wafer is subsequently diced and divided into individual chips to complete a packaged semiconductor device. Each semiconductor device is soldered on a printed circuit board, for example.

FIG. 2 shows the etching rate of chemical etching when the resin 3 is an epoxy resin. When diluted sulfuric acid (H ₂ SO ₄ : H ₂ O = 1: 1, temperature 110 ° C.) is used, an etching rate of 5 μm / min is obtained, and when concentrated sulfuric acid (temperature 32 ° C.) is used. An etching rate of 12 μm / min was obtained. When a mixed solution of sulfuric acid and hydrogen peroxide (H ₂ SO ₄ : H ₂ O ₂ = 1: 1, temperature 90 ° C.) was used, an etching rate of 20 μm / min was obtained. In addition to the above, as a chemical solution used for etching, hydrochloric acid is used, an organic solvent such as acetone or ethanol is used, or a basic solution such as a mixed solution of ammonia water and hydrogen peroxide (ammonia hydrogen peroxide) is used. May be.

When a commercially available epoxy resin is used as the resin 3, granular silica (SiO ₂ ) is added to the epoxy resin in order to improve heat dissipation during heat generation and match the thermal expansion coefficient of the resin 3 with the semiconductor substrate 1. There may be. In this case, if the resin 3 is etched using sulfuric acid or the like as described above and the etching proceeds to a certain extent, there is a phenomenon that the etching is blocked by the silica appearing on the surface of the resin 3 and the etching rate is lowered. In order to prevent this, the resin 3 is etched to some extent using sulfuric acid or the like, then the surface of the resin 3 is washed with pure water, and then the silica is etched by immersing the resin 3 in dilute hydrofluoric acid or buffered hydrofluoric acid. By doing so, the silica on the surface of the resin 3 can be removed. The resin 3 can be etched by alternately performing etching of the resin 3 with sulfuric acid or the like and etching of silica with dilute hydrofluoric acid or the like.

Note that dry etching by plasma may be performed as etching of the resin 3. For example, O ₂ plasma can be used as the plasma. Even when an epoxy resin containing silica is used as the resin 3 and the resin 3 is etched by dry etching, the etching rate decreases due to the silica that appears on the surface of the resin 3 when the etching proceeds to a certain extent. In order to prevent this, the resin 3 is etched to some extent by dry etching, and then the surface of the resin 3 is washed with pure water, and then the resin 3 is diluted with dilute hydrofluoric acid or buffered hydrofluoric acid. Soak the silica to etch. The resin 3 can be etched by alternately performing dry etching of the resin 3 and silica etching with dilute hydrofluoric acid or the like.

  Note that values such as the height of the post electrode 2, the height of the exposed portion of the post electrode 2, and the thickness of the plating 4 are examples, and are not limited to the values described above. With the manufacturing method described above, various semiconductor devices such as the diode described above can be manufactured. In particular, since the package size is the same as the chip size and is suitable for miniaturization, thinning, and weight reduction, it is suitable for manufacturing a semiconductor device to be mounted on a small electronic device.

It is a schematic process drawing which shows the manufacturing method of the semiconductor device by one Embodiment of this invention. It is a figure which shows the etching rate of the resin 3 in the embodiment. It is a schematic process drawing which shows the manufacturing method of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Post electrode, 3 ... Resin, 4 ... Plating.

Claims (4)

Forming a post electrode on the semiconductor substrate;
Forming a protective film on the semiconductor substrate for protecting the semiconductor substrate and the post electrode;
Polishing the protective film until the post electrode is exposed;
Etching the protective film to expose the sidewalls of the post electrodes;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of plating the surface of the post electrode after the step of etching the protective film to expose the side wall of the post electrode.   3. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of etching the protective film to expose the side wall of the post electrode, the protective film is etched using a chemical solution. 4. 3. The semiconductor device manufacturing method according to claim 1, wherein in the step of etching the protective film to expose the sidewall of the post electrode, the protective film is etched by dry etching using plasma. Method.

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