JP2005123217A - Quantum well type infrared detector - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the quantum efficiency of an infrared detector having a multilayered quantum well layer and, in addition, to reduce the crosstalk between pixels. <P>SOLUTION: A lower contact layer 1, a lower multilayered quantum well layer 2 formed by alternately laminating pluralities of barrier layers and well layers upon another, intermediate contact layer 3, upper multilayered quantum well layer 4 having the same constitution as that of the lower multilayered quantum well layer 2, and upper contact layer 5, are successively laminated on a semiconductor substrate 10. A separating groove 7 having such a depth that exposes the lower contact layer 1 is formed along the boundary of a pixel area. Then the lower contact layer 1 and the upper contact layer 5 exposed in the separating groove 7 are connected to each other through a metallic layer 24 formed on an insulating layer 21 on the side face of the groove 7, and a groove having such a depth that exposes the intermediate contact layer 3 is formed at the central part of the pixel area. In addition, a bump 26 which becomes the output terminal corresponding to pixels is provided on the intermediate contact layer 3 in the groove. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a quantum well-type infrared detection device that has a multiple quantum well layer made of a compound semiconductor layer and that converts infrared light into an electrical signal.

  Various configurations of a quantum well infrared detector having a multiple quantum well layer made of a compound semiconductor layer have already been proposed. For example, as shown in FIG. 6, a lower contact layer 101, a multiple quantum well layer 102, an upper contact layer 103, and a reflective layer 105 are formed on a semi-insulating semiconductor substrate 104 of GaAs, and a separation groove is formed. 109, the pixel-corresponding element 110 is separated, electrodes 107 and 108 are formed, other portions are protected by the protective insulating layer 106, a voltage is applied between the electrodes 107 and 108, and infrared rays are transmitted from the semiconductor substrate 104 side. Incident light can be processed and an output current corresponding to the detection element 110 can be processed to perform infrared detection.

  FIG. 7 is an explanatory diagram of the multiple quantum well layer in FIG. 6. As shown in FIG. 7A, the well layers 132 a to 132 m are interposed between the lower contact layer 121 and the upper contact layer 123. It has an infrared absorption layer 122 in which barrier layers 131a to 131n are alternately stacked. 7B shows the energy band diagram of the multiple quantum well layer. The same reference numerals as those in FIG. 7A correspond to the same parts, and Ec shows the conduction band. Therefore, when a voltage is applied between the lower contact layer 121 and the upper contact layer 123 and infrared rays are incident, electrons in the well layers 132a to 132m flow beyond the barrier layers 131a to 131n.

  FIG. 8 is an explanatory diagram of a two-dimensional arrangement, in which infrared detection elements 110 are two-dimensionally arranged, and electrodes 108 of each detection element 110 and an input gate 116 of a multiplexer 115 formed on a Si substrate. Are connected by In bumps 117, and the output signal of the detection element 110 corresponding to one pixel is sequentially processed by the multiplexer 115 to output infrared image data.

  FIG. 9 shows an essential part of the input part of the multiplexer, 110 is an infrared detection element, 141 is a transistor constituting the input gate of the multiplexer, 142 is a reset transistor, 143 is a storage capacitor, and 144 and 145 are control terminals. Reference numeral 146 denotes a reset voltage terminal, and reference numeral 147 denotes an output terminal connected to the changeover switch and the amplifier.

  When the reset transistor 142 is turned on, the storage capacitor 143 is charged up to a constant voltage by the voltage from the terminal 146 to be in a reset state, the transistor 142 is turned off, and the transistor 141 as an input gate is turned on. A voltage from the capacitor 143 is applied to the element 110, and a current corresponding to the infrared energy incident on the infrared detection element 110 flows. Accordingly, since the terminal voltage of the storage capacitor changes corresponding to the incident infrared energy, infrared image data can be obtained by sequentially switching the two-dimensional array of detection elements 110 by a subsequent circuit (not shown). it can.

  Also, infrared light is incident on the first multiple quantum well layer and the second multiple quantum well layer having a detection wavelength sensitivity different from that of the first multiple quantum well layer through the grating layer. As a configuration having a detection element, an infrared detection device that expands the wavelength range of infrared detection is known (see, for example, Patent Document 1). In addition, in the configuration shown in FIGS. 6 and 7, there is known an infrared detecting device that increases the effect of barriers against electrons in other barrier layers by reducing at least one barrier layer among a plurality of barrier layers, thereby reducing dark current. (For example, refer to Patent Document 2).

Infrared detectors that detect infrared rays in a desired wavelength band by controlling the voltages applied to the first and second multiple quantum well layers, each having a different wavelength sensitivity, with a switch are known. (For example, refer to Patent Document 3). Compared with the upper multiple quantum well layer, the lower multiple quantum well layer increases the energy barrier of the barrier layer and increases the impurity concentration of the well layer to reduce dark current and improve infrared detection sensitivity. Infrared detectors are known (see, for example, Patent Document 4).
JP-A-5-29643 Japanese Patent Laid-Open No. 10-341028 JP 2000-196133 A JP 2000-323742 A

  The quantum efficiency of the infrared detecting element having a multiple quantum well structure depends on the electric field strength applied to the infrared absorbing portion and the number of well layers stacked. Generally, as the electric field strength is increased and the number of stacked layers is increased, the quantum efficiency is increased and the infrared detection signal level can be increased. The applied voltage in this case is limited by the operating voltage of peripheral circuits such as multiplexers, etc. In order to increase the electric field strength while keeping the applied voltage constant, it is necessary to reduce the number of well layers stacked. . Therefore, there is a problem that the quantum efficiency cannot be improved.

  Further, as shown in FIG. 6, the detection elements 110 corresponding to pixels of the conventional infrared detection apparatus are separated by the separation groove 109, but the detection elements 110 are arranged close to each other to increase the resolution of the infrared image. Therefore, there is a problem in that the infrared rays scattered by the reflective layer 105 are incident on the detection element of the adjacent pixel and the crosstalk becomes large. Such problems are not raised in the above-mentioned Patent Documents 1 to 4, and no solution is suggested.

  An object of the present invention is to improve the quantum efficiency of infrared detection and to reduce crosstalk between pixels.

  In the infrared detection device of the present invention, a contact layer and a multiple quantum well layer in which a plurality of barrier layers and well layers are alternately stacked are alternately stacked on a semiconductor substrate, and the semiconductor substrate is formed from the uppermost contact layer. The lowermost contact layer and every other contact layer on the upper layer side from the lowermost contact layer are formed on the insulating layer on the side surface in the separation groove at the boundary of the pixel region reaching the uppermost lower layer contact layer. Providing a metal layer to be connected, connecting the metal layer to a common terminal, and insulating a side surface in a groove reaching from the uppermost contact layer in the pixel region to a contact layer one above the lowermost contact layer On the layer, a metal layer for connecting a contact layer on one of the lowermost contact layers and every other contact layer on the upper side from the contact layer is provided, and an output terminal corresponding to a pixel is provided on the metal layer. Become a bump And it has a digit configuration.

  Also, a lower contact layer, a lower multiple quantum well layer in which a plurality of barrier layers and well layers are alternately stacked, an intermediate contact layer, an upper multiple quantum well layer having the same configuration as the lower multiple quantum well layer, and an upper contact layer Are sequentially stacked on a semiconductor substrate, and the lower contact layer and the upper contact layer are formed on an insulating layer on a side surface in an isolation trench of a pixel region exposing a part of the lower contact layer from the upper contact layer. A metal layer connecting between the two, and connecting the metal layer to a common terminal of all the pixels, and in a groove exposing a part of the intermediate contact layer from the upper contact layer at a substantially central position of the pixel region. A bump is connected to the intermediate contact layer to serve as an output terminal corresponding to a pixel.

  Further, the ohmic electrode provided in the lower contact layer exposed in the isolation groove of the pixel region and the common terminal of all the pixels are connected by the metal layer, and the exposed in the groove at a substantially central position of the pixel region. A bump as an output terminal corresponding to a pixel is connected to an ohmic electrode provided in the intermediate contact layer, and a voltage is applied between the selected bump and the common terminal.

  Since one pixel has a configuration in which a plurality of detection elements each including a contact layer and a multiple quantum well layer are connected in parallel, the infrared detection sensitivity can be improved. In addition, the crosstalk can be reduced by shielding the scattered infrared rays from leaking to the adjacent pixel side by the metal layer in the separation groove in the pixel region.

  Referring to FIG. 1, a lower contact layer 1, a lower multiple quantum well layer 2 in which a plurality of barrier layers and well layers are alternately stacked, an intermediate contact layer 3, and a lower multiple quantum on a semiconductor substrate 10. In the structure in which the upper multiple quantum well layer 4 having the same configuration as the well layer 2 and the upper contact layer 5 are sequentially stacked, the separation groove 7 having a depth exposing the lower contact layer 1 from the upper contact layer 5 is formed in the pixel region. A metal layer 24 formed on the insulating layer 21 on the side surface of the separation groove 7 between the lower contact layer 1 exposed in the separation groove 7 and the upper contact layer 5 in the pixel region. A groove having a depth exposing the intermediate contact layer 3 from the upper contact layer 5 is formed at a position substantially in the center of the pixel region, and a bump 26 serving as an output terminal corresponding to the pixel is formed in the intermediate contact layer 3 in the groove. Is provided.

  FIG. 1 is an explanatory diagram of a main part of Embodiment 1 of the present invention, and includes an n-GaAs lower contact layer 1, a lower multiple quantum well layer 2, and an intermediate contact on a semiconductor substrate 10 such as semi-insulating GaAs. Layer 3, upper multiple quantum well layer 4, and upper contact layer 5 are sequentially stacked, and isolation groove 7 for defining a pixel region is formed so that lower contact layer 1 is exposed. A groove is formed so that the intermediate contact layer 3 is exposed at a position of the metal layer 24, and a metal layer 24 surrounding the periphery of the pixel 6 and connecting the lower contact layer 1 and the upper contact layer 5 is provided on the insulating layer 21. The bump 26 connected to the exposed portion of the intermediate contact layer 3 is formed. 9, 20 and 23 are ohmic electrodes, 21 is an insulating layer such as SiON, and 22 is a reflective layer.

  The lower multiple quantum well layer 2 and the upper multiple quantum well layer 4 have the same configuration, and have a configuration in which a plurality of well layers and barrier layers are alternately stacked as in the conventional example. Then, when the bump 26 is used as an output terminal corresponding to the pixel 6 and the ohmic electrode 23 is connected to each other by the metal layer 24 or the like so as to be a common electrode for all pixels, a voltage is applied between the ohmic electrode 23 and the bump 26. A voltage is applied to the lower multiple quantum well layer 2 via the lower contact layer 1 and the intermediate contact layer 3, and to the upper multiple quantum well layer 4 via the upper contact layer 5 and the intermediate contact layer 3. A voltage is applied. Therefore, the same voltage is applied to the detection element by the lower multiple quantum well layer 2 and the detection element by the upper multiple quantum well layer 4 in the region of one pixel 6, and the multiple quantum well layers are stacked, The electric field strength when the number of layers is increased can be maintained as in the conventional example.

  The infrared absorption rate by the multiple quantum well layers is several percent or less, and the amount of infrared rays incident on the upper and lower multiple quantum well layers may be regarded as almost the same. And since it is set as the structure which connected the detection element which comprises 1 pixel by the lower multiple quantum well layer 2 and the upper multiple quantum well layer 4 in parallel, the detection sensitivity of the infrared corresponding to a pixel can be improved. . The infrared rays incident from the substrate 10 side are redirected by an optical coupling structure (not shown) and incident on the lower multiple quantum well layer 2 and the upper quantum well layer 4, and are reflected by the reflective layer 22 on the upper contact layer 5. The light is reflected in a random direction and is incident on the upper quantum well layer 4 and the lower quantum well layer 2 again. Then, the infrared light scattered in each of the multiple quantum well layers 2 and 4 and the infrared light scattered by the reflection layer 22 leak to the adjacent pixel side by the metal layer 24 on the insulating layer 21 on the side surface of the separation groove 7. Can be prevented, and crosstalk can be reduced.

2 and 3 are explanatory diagrams of the manufacturing process of the infrared detecting device according to the first embodiment of the present invention shown in FIG. 1, and schematically show the manufacturing process for an area corresponding to one pixel. FIG. 2A shows a schematic configuration of a cross section of an epitaxial wafer. From an n-GaAs having a film thickness of 1,000 nm and an impurity concentration of 5 × 10 ¹⁷ cm ⁻³ on a semi-insulating GaAs semiconductor substrate 10. The lower contact layer 1 is formed, and a barrier layer made of i-Al _0.3 Ga _0.7 As having a thickness of 40 nm and an n− having an impurity concentration of 5 × 10 ¹⁷ cm ⁻³ having a thickness of 5 nm are formed thereon. A lower multiple quantum well layer 2 is formed by alternately laminating well layers made of GaAs for 20 periods, and an intermediate contact layer 3 made of n-GaAs having a thickness of 500 nm and an impurity concentration of 5 × 10 ¹⁷ cm ⁻³ is formed thereon. An upper multiple quantum well layer 4 having the same configuration as the lower multiple quantum well layer 2 is formed thereon, and n-GaAs having a film thickness of 500 nm and an impurity concentration of 5 × 10 ¹⁷ cm ⁻³ is formed thereon. Upper part Showing a state of forming a Ntakuto layer 5. Each layer on the substrate 10 can be formed by a MOCVD (Metal Organic Chemical Deposition) method or an MBE (Molecular Beam Epitaxy) method.

  Next, as shown in FIG. 2B, the upper contact layer 5 and the upper multiple quantum well layer 4 are selectively etched to correspond to the position of the boundary of the region of the pixel 6 and substantially the center of the pixel 6. The separation groove 7 and the intermediate contact groove 8 reaching the intermediate contact layer 3 are formed at the positions. Next, as shown in FIG. 6C, the intermediate contact layer 3 and the lower multiple quantum well layer 2 are selectively etched to position the boundary of the region of the pixel 6 so that the lower contact layer 1 is exposed. A separation groove 7 is formed in In this case, the selective etching can be performed by applying a wet etching method to form the separation groove 7 and the intermediate contact groove 8 in a tapered shape.

  Next, as shown in FIG. 3A, an insulating layer 21 of SiON is formed on the entire surface, and the lower contact layer 1 in the separation groove 7, the intermediate contact layer 3 in the intermediate contact groove 8, and the upper contact The insulating layer 21 is selectively removed so that a part of the layer 15 is exposed. Then, ohmic electrodes 9, 20, and 23 made of Au / Ge / Ni are formed on the exposed upper contact layer 5, intermediate contact layer 3, and lower contact layer 1, respectively. These ohmic electrodes 9, 20, and 23 can be formed by applying, for example, a lift-off method used in the manufacturing process of a semiconductor device. Next, a reflective layer 22 made of Au / Ti is formed on the upper contact layer 4. The reflective layer 22 can also be formed by applying a lift-off method.

  Next, as shown in FIG. 3B, a metal layer 24 made of Au / Ti is formed on the side insulating layer 21 in the separation groove 7 to connect the ohmic electrodes 9 and 23 together. A bump base electrode 25 made of Au / Ti is formed on the insulating layer 21 on the tapered surface of the intermediate contact groove 8 while being connected to the ohmic electrode 20. The bump base electrode 25 can be formed simultaneously with the metal layer 24 by applying, for example, a lift-off method. A bump 26 made of In is formed on the bump base electrode 25.

  This In bump 26 becomes an output terminal of the pixel 6, and the metal layer 24 is connected to a common terminal (not shown) for each pixel. Then, by applying a voltage between the In bump 26 and the common terminal, the voltage is applied in a state where the detection elements of the lower multiple quantum well layer 2 and the upper multiple quantum well layer 4 are connected in parallel. A signal corresponding to the intensity of infrared light incident from the side can be output from the In bump 26. At that time, the infrared light irregularly reflected by the reflective layer 22 is shielded by the metal layer 24 and does not leak to the adjacent pixels, so that crosstalk can be reduced.

  In the above manufacturing process, for example, in addition to the epitaxial growth layer in FIG. 2A, an etching stop layer for selective etching and a buffer layer for preventing deterioration of the characteristics of the epitaxial growth layer. However, for the sake of simplicity, the processing steps and illustration are omitted. An optical coupling structure such as a concavo-convex structure for changing the direction of infrared rays incident on the substrate 10 from the vertical direction is also provided, but the processing steps and illustrations are also omitted. Moreover, it can be set as the structure which forms and protects a protective film other than the board | substrate 10 side into which infrared rays enter.

  FIG. 4 is an explanatory diagram of a main part of the input portion of the multiplexer according to the first embodiment of the present invention. Reference numerals 40a and 40b denote a detection element including the lower multiple quantum well layer 2 and a detection element including the upper multiple quantum well layer 4, Reference numeral 41 denotes a transistor constituting an input gate, 42 denotes a reset transistor, 43 denotes a storage capacitor, 44 and 45 denote control terminals, 46 denotes a reset voltage terminal, and 47 denotes an output terminal connected to the changeover switch and the amplifier.

  One pixel has a configuration in which the detection elements 40a and 40b of the multiple quantum well layers 2 and 4 in the pixel region are connected in parallel, and the bump 26 is connected to the transistor 41 forming the input gate of the multiplexer, and the metal layer The common terminal which mutually connected 24 becomes a circuit structure which is earth | grounded. Then, when the reset transistor 42 is turned on, the storage capacitor 43 is charged up with a constant voltage from the terminal 46 to be in a reset state, the transistor 42 is turned off, and the pixel selection transistor 41 is turned on. The voltage from the capacitor 43 is applied to the detection elements 40a and 40b connected in parallel, a current corresponding to the infrared energy incident on the detection elements 40a and 40b flows, and the terminal voltage of the storage capacitor 43 changes. This change in the terminal voltage is processed by a subsequent circuit (not shown) connected to the output terminal 47, and the pixels in the two-dimensional array are sequentially switched by the transistors 41 and 42 corresponding to the respective pixels, whereby two-dimensional Infrared image data can be obtained.

  FIG. 5 is an explanatory diagram of the main part of the second embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same components, and the lower multiple quantum well layer 2 is the first multiple quantum well layer and the upper multiple quantum well layer 4 is the same. The second multiple quantum well layer, the lower contact layer 1, the intermediate contact layer 3 and the upper contact layer 5 as the first, second and third contact layers, respectively, 31 is the third multiple quantum well layer, and 32 is the second Four contact layers are used. Reference numeral 33 denotes an ohmic electrode, and 34 denotes a metal layer. The first to third multiple quantum well layers 2, 4, and 31 have the same configuration in which a plurality of well layers and barrier layers are stacked. That is, a plurality of contact layers and multiple quantum well layers are alternately stacked on the semiconductor substrate 10. In FIG. 1, the multiple quantum well layer has a two-layer structure, and in FIG. The case of a layer structure is shown.

  That is, in FIG. 5, the first contact layer 1, the first multiple quantum well layer 2, the second contact layer 3, and the second multiple quantum well layer are formed on a semiconductor substrate 10 such as semi-insulating GaAs. 4, the third contact layer 5, the third multiple quantum well layer 31, and the fourth contact layer 32 are sequentially laminated to form three multiple quantum well layers. Then, the separation groove 7 that defines the region of the pixel 6 is formed so that the lowermost first contact layer 1 is exposed from the uppermost fourth contact layer 32 side, and substantially corresponds to the center of the region of the pixel 6. A groove is formed at the position from the uppermost fourth contact layer 32 side so that the second contact layer 3 above the lowermost contact layer is exposed, and an insulating layer 21 is formed on the entire surface. The layer 21 is selectively etched to expose the first contact layer 1 in the isolation trench 7, the second contact layer 3 in the trench in the center of the region of the pixel 6, and the fourth contact layer 32. The electrodes 9, 20, 23, 33 are formed, the ohmic electrodes 23, 9 are connected by the metal layer 24 on the insulating layer 21, and the ohmic electrodes 20, 33 are connected as the bump underlayer 25 on the insulating layer 21. Connected by metal layer, bump Bumps 26 are provided on the ground layer 25, the reflective layer 22 is formed on the fourth contact layer 32, the metal layer 34 similar to the metal layer 24 is formed, and the insulating layer 21 is formed on the third multiple quantum well layer 31 on the separation groove 7 side. Formed through.

  Accordingly, the first contact layer 1 and the third contact layer 5 are connected by the metal layer 24, and the second contact layer 3 and the fourth contact layer 32 are connected by the metal layer as the bump underlayer 25, When a voltage is applied between the metal layer 24 connected to the common terminal and the bump 26 corresponding to the pixel, the same voltage is applied to the first to third multiple quantum well layers 2, 4, and 31 in the pixel 6. In addition, with respect to the infrared light incident from the substrate 10 side, a configuration in which three detection elements are connected in parallel is detected, and the detection sensitivity can be improved.

  It is also possible to improve the infrared detection sensitivity by further stacking multiple quantum well layers to increase the number of detection elements corresponding to pixels. In this case, the connection structure between the contact layers using the separation groove of the pixel becomes complicated.

It is principal part explanatory drawing of Example 1 of this invention. It is explanatory drawing of the manufacture process of Example 1 of this invention. It is explanatory drawing of the manufacture process of Example 1 of this invention. It is principal part explanatory drawing of the input part of the multiplexer of Example 1 of this invention. It is principal part explanatory drawing of Example 2 of this invention. It is explanatory drawing of a prior art example. It is explanatory drawing of a multiple quantum well layer. It is explanatory drawing of a two-dimensional arrangement | sequence. It is principal part explanatory drawing of the input part of a multiplexer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lower contact layer 2 Lower multiple quantum well layer 3 Intermediate contact layer 4 Upper multiple quantum well layer 5 Upper contact layer 6 Pixel 7 Separation groove 9 Ohmic electrode 10 Semiconductor substrate 20 Ohmic electrode 21 Insulating layer 22 Reflective layer 23 Ohmic electrode 24 Metal layer 25 Bump underlayer 26 Bump

Claims (3)

A plurality of contact layers and multiple quantum well layers in which a plurality of barrier layers and well layers are alternately stacked are alternately stacked on a semiconductor substrate, and the uppermost contact layer is changed to a lowermost contact layer on the semiconductor substrate. A metal layer connecting the lowermost contact layer and every other contact layer on the upper layer side from the lowermost contact layer is provided on the insulating layer on the side surface in the separation groove at the boundary of the pixel region reaching, A metal layer is connected to a common terminal, on the insulating layer on the side surface in the trench reaching from the uppermost contact layer in the pixel region to the contact layer on the lowermost contact layer, the lowermost layer It has a configuration in which a metal layer for connecting a contact layer on one of the contact layers and every other contact layer on the upper layer side from the contact layer is provided, and bumps serving as output terminals corresponding to pixels are provided on the metal layer. Special Infrared detection device. A lower multiple quantum well layer in which a plurality of lower contact layers, barrier layers and well layers are alternately stacked; an intermediate contact layer; an upper multiple quantum well layer having the same configuration as the lower multiple quantum well layer; and an upper contact layer; Are sequentially stacked on a semiconductor substrate, and the lower contact layer and the upper contact layer are formed on an insulating layer on a side surface in an isolation trench of a pixel region exposing a part of the lower contact layer from the upper contact layer. Providing a metal layer for connecting the metal layer, connecting the metal layer to a common terminal of all pixels, and exposing the part of the intermediate contact layer from the upper contact layer at a position substantially in the center of the pixel region. An infrared detecting device having a configuration in which bumps serving as output terminals corresponding to pixels are provided connected to an intermediate contact layer.   The ohmic electrode provided in the lower contact layer exposed in the isolation groove of the pixel region and a common terminal of all the pixels are connected by the metal layer, and the intermediate portion exposed in the groove at a substantially central position of the pixel region. 3. The infrared ray according to claim 2, wherein a bump as an output terminal corresponding to a pixel is connected to an ohmic electrode provided in the contact layer, and a voltage is applied between the selected bump and the common terminal. Detection device.

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