JP2005117459A - Input circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an input circuit which outputs a prescribed output level when an input is open and where current is not made to flow from an input terminal to a power source when the maximum value of an input signal is larger than power supply voltage. <P>SOLUTION: By previously setting a relation between an output level of a push-pull type detection stage composed of P channel and N channel transistors provided in a current mirror relation to P channel and N channel transistors a push-pull type output stage of an operational amplifier with a reverse input terminal and an output terminal subjected to imaginary short circuit and a circuit threshold of a gate circuit in a prescribed relation, a prescribed output level is outputted from the gate circuit in an input open state. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an input circuit, and more particularly to an input circuit that detects a high level and a low level of a signal input from an input terminal and outputs a predetermined level when the input terminal is open.

  Some electronic information devices receive data or the like from an external device via a connector. Such an input circuit of an electronic information device needs to detect whether an input signal is at a high level or a low level when a connector is connected, and output a signal having an output level corresponding to the input signal. . In addition, when the connector is not connected, the input circuit needs to output a predetermined output level in order to prevent malfunction of the internal circuit of the electronic information device in a so-called input open state.

  FIG. 7 is a circuit diagram of a conventional example configured to satisfy the above functions. This conventional example corresponds to a circuit in which a capacitor provided for noise removal is omitted from the input circuit described in Patent Document 1, for example.

  In the input circuit of FIG. 7, the positive phase input terminal of the comparator C1 is connected to the input terminal Vi via the resistor Ri, and the positive phase input terminal is connected to the power source Vdd via the resistor R3. The reference voltage Vref is supplied to the negative phase input terminal of the comparator C1.

  If the resistance value of the resistor R3 is set to a value much larger than the resistance value of the resistor Ri, the comparator C1 is set to the high level at the output terminal Vo when the level of the input signal from the input terminal Vi is higher than Vref. When the level of the input signal from the input terminal Vi is smaller than Vref, the comparator C1 outputs a low level to the output terminal Vo. When the input terminal is in the open state, it is pulled up by the resistor R3 and the voltage of the power supply Vdd is supplied to the positive phase input terminal of the comparator C1, so that the comparator C1 has a predetermined output level when the input is open. A high level is output to the output terminal Vo.

Japanese Patent Laid-Open No. 3-64117 (especially FIG. 4)

  However, the conventional input circuit of FIG. 7 has a problem that current flows from the input terminal Vi to the power supply Vdd when the maximum value of the signal input from the input terminal Vi is larger than the voltage of the power supply Vdd. There is. Depending on the external device connected via the connector, the maximum value of the input signal may be several times the power supply voltage. In such a case, the power supply voltage fluctuates.

  An object of the present invention is to detect whether an input signal is high level or low level and output a signal of an output level corresponding to each of the input signals, and at the time of an input open state, outputs a predetermined output level, To provide an input circuit in which no current flows from an input terminal to a power supply even when the maximum value of the input signal is larger than the power supply voltage.

  The input circuit of the present invention includes an input terminal, an output terminal, an input resistor having one end connected to the input terminal, a reference voltage supplied to the positive phase input terminal, and a negative phase input terminal to the other end of the input resistance. An amplification stage connected to amplify the input of the reverse phase input terminal, output the first internal output signal from the first output terminal, and output the second internal output signal from the second output terminal, and the source is the first A P-channel first transistor and drain connected to a power source and supplied with the first internal output signal to the gate are connected to the drain of the first transistor and become an output terminal, and the second internal output is connected to the gate. A push-pull output stage having an N-channel second transistor supplied with a signal and having a source connected to a second power supply; and a source connected to the first power supply and a gate connected to the first power supply. 1 The P-channel third transistor and drain to which the internal output signal is supplied are connected to the drain of the third transistor, become an output terminal, and the second internal output signal is supplied to the gate and the source is grounded A detector comprising: a push-pull type detection stage having a fourth transistor; and a gate circuit having an input terminal connected to an output terminal of the push-pull type detection stage and an output terminal connected to the output terminal; And an output terminal of the push-pull output stage of the operational amplifier and a negative phase input terminal of the amplifier stage are connected.

  The input circuit may include a pull-down resistor provided between the output terminal of the push-pull type detection stage and the second power source in the detector, or the push-pull type detection stage in the detector. A pull-up resistor provided between the output terminal and the first power supply may be further provided.

  The input circuit of the present invention has a predetermined output from the gate circuit when the input is open by setting the relationship between the output level of the detection stage of the detector and the circuit threshold of the gate circuit so as to satisfy a predetermined relationship in advance. It is configured to output the level. For this reason, the input circuit according to the present invention does not require a resistor for pulling up the input terminal to the power supply as in the conventional example, so even when the maximum value of the input signal is larger than the power supply voltage, a current flows from the input terminal to the power supply. The power supply voltage fluctuation due to the input signal can be prevented without flowing.

  An input circuit according to the present invention includes an operational amplifier and a detector in which an anti-phase input terminal and an output terminal are imaginarily short-circuited, and a current mirror in the detector with respect to the P-channel and N-channel transistors of the push-pull output stage of the operational amplifier. The relationship between the output level of the push-pull type detection stage composed of P-channel and N-channel transistors provided with the above relationship and the circuit threshold value of the gate circuit of the output stage receiving this is set to a predetermined relationship in advance. Thus, a predetermined output level is output from the gate circuit in the input open state. When the input signal is input to the negative phase input terminal via a resistor and the gate circuit is an inverter, for example, a high level is output from the gate circuit when the input signal is high level, and the gate circuit when the input signal is low level Outputs a low level.

  Preferred embodiments of the present invention will be described below in detail with reference to the drawings. In addition, the following examples are illustrations of examples suitable for deepening the understanding of the present invention, and the present invention is not limited only to the following examples.

  FIG. 1 is a circuit diagram of a first embodiment of the present invention. The output circuit 1 of the present invention includes an input terminal Vi, an input resistor Ri, an operational amplifier 11, a detector 12, and an output terminal Vo.

  The operational amplifier 11 includes an amplification stage A1 and a push-pull type output stage including a P-channel transistor T1 and an N-channel transistor T2 connected in series, and performs class AB operation.

  In the amplification stage A1, the positive phase input terminal is connected to the reference voltage source Vref, the negative phase input terminal is connected to the input terminal Vi of the input circuit 1 through the input resistor Ri, and the input of the negative phase input terminal is amplified. The first internal output signal S1 is output from the first output terminal, and the second internal output signal S2 is output from the second output terminal.

  The push-pull output stage of the operational amplifier 11 has a P-channel first transistor T1 whose source is connected to the power supply Vdd (first power supply) and whose gate is supplied with the first internal output signal S1, and whose drain is the first. An N-channel second transistor T2 which is connected to the drain of the first transistor and becomes the output terminal N1 of the operational amplifier 11 and to which the second internal output signal S2 is supplied to the gate and the source is connected to the ground (second power supply). Consists of. The output terminal N1 of the operational amplifier 11 is connected to the negative phase input terminal of the amplification stage A1.

  The detector 12 includes a push-pull type detection stage composed of a P-channel transistor T3 and an N-channel transistor T4 connected in series, and an output stage gate circuit G1.

  The push-pull detection stage includes a P-channel third transistor T3 having a source connected to the power supply Vdd and a gate supplied with the first internal output signal S1, and a drain connected to the drain of the third transistor. The output terminal N2 of the push-pull detection stage is constituted by an N-channel fourth transistor T4 to which the second internal output signal S2 is supplied to the gate and the source is grounded. In this embodiment, the P-channel transistor T1 and the P-channel transistor T3 have the same channel length, the N-channel transistor T2 and the N-channel transistor T4 have the same channel length, and the P-channel transistor T1 When the channel width is WT1, the channel width of the P-channel transistor T3 is WT3, the channel width of the N-channel transistor T2 is WT2, and the channel width of the N-channel transistor T4 is WT4, (WT3 / WT1) = (WT4 / WT2).

  Although the logic function of the gate circuit G1 is not limited, in this embodiment, an inverter is used. Its input terminal is connected to the output terminal N2 of the push-pull type detection stage, and its output terminal is connected to the output terminal Vo. It is connected. The circuit threshold voltage, which is an input voltage whose output is inverted with respect to the input of the gate circuit G1, is set so as to have a predetermined relationship with the reference voltage Vref. Here, it is assumed that the circuit threshold voltage of the gate circuit G1 is set to a value larger than the reference voltage Vref (the circuit threshold voltage is set to Vref + α).

  Next, the operation of this embodiment will be described with reference to FIG. 2 which is an operation timing chart.

  First, the case where the input terminal Vi is in an open state will be described. Since the operational amplifier 11 is in an imaginary short state because the output terminal N1 and the negative phase input terminal are directly connected, when the input terminal Vi is open, the voltage at the output terminal N1 is the reference voltage Vref supplied to the positive phase input terminal. Is equal to The transistor of the push-pull type detection stage of the detector 12 has a current mirror relationship with the transistor of the push-pull type output stage of the operational amplifier 11, and is set to (WT3 / WT1) = (WT4 / WT2). The voltage at the output terminal N2 of the push-pull type detection stage is equal to the reference voltage Vref as is the voltage at the output terminal N1.

  On the other hand, since the circuit threshold voltage of the gate circuit G1 is set to (Vref + α), the input to the gate circuit G1 is detected as a low level and a high level is output to the output terminal Vo. That is, also in this embodiment, when the input terminal is in an open state, a high level that is a predetermined output level when the input is open is output to the output terminal Vo, as in the conventional example of FIG.

  Next, a case where an input signal is applied to the input terminal Vi will be described. Also in this case, since the operational amplifier 11 is in an imaginary short state because the output terminal N1 and the negative phase input terminal are directly connected, the voltage at the output terminal N1 of the push-pull type output stage, that is, the negative phase input terminal of the amplification stage A1. The voltage always operates to maintain a voltage equal to the reference voltage Vref.

  When the input signal voltage at the input terminal Vi decreases and is equal to the reference voltage Vref, the first internal output signal S1 and the second internal output signal S2 at the amplification stage A1 are the same voltage as when the input terminal Vi is open. The voltage at the output terminal N2 of the push-pull detection stage in the detector 12 is equal to the reference voltage Vref. Since the reference voltage Vref is smaller than (Vref + α) which is the circuit threshold voltage of the gate circuit G1, a high level is output to the output terminal.

  When the input signal voltage at the input terminal Vi is larger than the reference voltage Vref, the voltage at the opposite phase input terminal of the amplification stage A1 is pulled to the high side, so that the first internal output signal S1 and the second internal output signal at the amplification stage A1 are pulled. The output signal S2 has a larger value than the voltage in the input open state. As a result, the current flowing through the P-channel transistor T1 decreases, the current flowing through the N-channel transistor T2 increases, and the voltage at the output terminal N1, that is, the voltage at the negative phase input terminal of the amplification stage A1, is pulled back to the reference voltage Vref. At this time, a current flows from the input terminal Vi to the ground through the input resistor Ri, the push-pull output stage output terminal N1, and the N-channel transistor T2. In this state, the push-pull detection stage P-channel transistor T3 in the detector 12 is current-mirror connected to the P-channel transistor T1, and the N-channel transistor T4 is current-mirror connected to the P-channel transistor T2. The voltage is smaller than the reference voltage Vref. Since the voltage at the output terminal N2 is smaller than the circuit threshold voltage (Vref + α) of the gate circuit G1, a high level is output to the output terminal.

  When the input signal voltage at the input terminal Vi is smaller than the reference voltage Vref, the voltage at the opposite phase input terminal of the amplification stage A1 is pulled to the low side, so that the first internal output signal S1 and the second internal output signal at the amplification stage A1 The output signal S2 has a smaller value than the voltage in the input open state. As a result, the current flowing through the P-channel transistor T1 increases, the current flowing through the N-channel transistor T2 decreases, and the voltage at the output terminal N1, that is, the voltage at the negative phase input terminal of the amplification stage A1, is pulled back to the reference voltage Vref. At this time, a current flows from the power supply Vdd to the input terminal Vi through the P-channel transistor T1, the output terminal N1 of the push-pull type output stage, and the input resistance Ri. In this state, the voltage at the output terminal N2 of the push-pull detection stage in the detector 12 is higher than the reference voltage Vref, but the output terminal Vo is high while it is lower than the circuit threshold voltage (Vref + α) of the gate circuit G1. Remain in level. When the input signal voltage further decreases and the voltage at the output terminal N2 of the push-pull type detection stage becomes higher than the circuit threshold voltage (Vref + α) of the gate circuit G1, a low level is output to the output terminal Vo.

  That is, if the input signal voltage when the voltage at the output terminal N2 of the push-pull type detection stage becomes (Vref + α) is Vt1 (<Vref), a low level is output to the output terminal Vo at an input signal voltage lower than Vt1. When the input signal voltage is higher than Vt1, a high level is output to the output terminal Vo.

  As described above, the input circuit according to the first embodiment detects whether the input signal is at the high level or the low level, and outputs an output level signal corresponding to each of the input signals. The high level can be output as in the conventional example. Further, since the circuit of the first embodiment does not have a current path from the input terminal Vi to the power supply Vdd, even when the maximum value of the input signal is larger than the power supply voltage, the input terminal Vi is connected to the power supply Vdd as in the conventional example. Current can be prevented from flowing, and power supply voltage fluctuation due to an input signal does not occur.

  Next, a second embodiment of the present invention will be described. The second embodiment is different from the first embodiment only in that the circuit threshold voltage of the gate circuit G1 is smaller than the reference voltage Vref, and the other configuration is the same as that of the first embodiment. The circuit threshold voltage of the gate circuit G1 is set to (Vref−α).

  With this change, in the second embodiment, a low level is output to the output terminal Vo when the input is open. When an input signal is supplied to the input terminal Vi, the voltage at the output terminal N2 of the push-pull detection stage is equal to the circuit threshold voltage of the gate circuit G1 at the voltage Vt2 where the input signal voltage is larger than the reference voltage Vref ( Therefore, when the input signal voltage is lower than Vt2, a low level is output to the output terminal Vo, and when the input signal voltage is higher than Vt2, a high level is output to the output terminal Vo. Since other operations and effects are the same as those in the first embodiment, description thereof will be omitted.

  Next, a third embodiment of the present invention will be described. The third embodiment relates to the channel width WT1 of the P-channel transistor T1, the channel width WT3 of the P-channel transistor T3, the channel width WT2 of the N-channel transistor T2, and the channel width WT4 of the N-channel transistor T4 in the first embodiment (WT4 / WT2)> (WT3 / WT1), and the voltage at the output terminal N2 of the push-pull detection stage in FIG. 1 when the input terminal Vi is in the open state is reduced to (Vref−ΔV). Only the point that the circuit threshold voltage of the gate circuit G1 is set larger than the voltage is different from that of the first embodiment, and other configurations are the same as those of the first embodiment. Considering the manufacturing variation of the circuit threshold voltage of the gate circuit G1, it is easy to make a large difference between the circuit threshold voltage of the gate circuit G1 and the voltage of the output terminal N2 when the input is open. Greatly effective in prevention.

  Due to this change, in the third embodiment, when the input is open, a high level is output to the output terminal Vo as in the first embodiment. When an input signal is supplied to the input terminal Vi, the voltage at the output terminal N2 of the push-pull detection stage is equal to the circuit threshold voltage of the gate circuit G1 at the voltage Vt3 where the input signal voltage is larger than the reference voltage Vref ( Vref−ΔV + α), an input signal voltage lower than Vt3 outputs a low level to the output terminal Vo, and an input signal voltage higher than Vt3 outputs a high level to the output terminal Vo. Since other operations and effects are the same as those in the first embodiment, description thereof will be omitted.

  Next, a fourth embodiment of the present invention will be described. The fourth embodiment relates to the channel width WT1 of the P-channel transistor T1, the channel width WT3 of the P-channel transistor T3, the channel width WT2 of the N-channel transistor T2, and the channel width WT4 of the N-channel transistor T4 of the second embodiment (WT3 / WT1)> (WT4 / WT2), and when the input terminal Vi is in an open state, the voltage at the output terminal N2 of the push-pull detection stage in FIG. 1 is increased to (Vref + ΔV). However, only the point that the circuit threshold voltage of the gate circuit G1 is set to be small is different from the second embodiment, and the other configuration is the same as that of the second embodiment. Considering the manufacturing variation of the circuit threshold value of the gate circuit G1, it is easy to make a large difference between the circuit threshold voltage of the gate circuit G1 and the voltage of the output terminal N2 when the input is open. The effect is great.

  Due to this change, in the fourth embodiment, when the input is open, a low level is output to the output terminal Vo as in the second embodiment. When an input signal is supplied to the input terminal Vi, the voltage at the output terminal N2 of the push-pull detection stage is equal to the circuit threshold voltage of the gate circuit G1 at the voltage Vt4 where the input signal voltage is smaller than the reference voltage Vref ( Vref + ΔV−α), an input signal voltage lower than Vt4 outputs a low level to the output terminal Vo, and an input signal voltage higher than Vt4 outputs a high level to the output terminal Vo. Since other operations and effects are the same as those of the second embodiment, description thereof will be omitted.

  Next, a fifth embodiment of the present invention will be described. In the fifth embodiment, the detector 12 in the circuit of the third embodiment (same as FIG. 1) is replaced with the detector 12a of FIG. The detector 12a is obtained by adding a pull-down resistor R1 between the output terminal N2 of the push-pull type detection stage of the detector 12 and the ground. The structure of the other parts of the fifth embodiment is the same as that of the third embodiment, but the channel width of the transistor is preferably set to (WT4 / WT2) = (WT3 / WT1). In the fifth embodiment, by passing a current to the ground through the resistor R1, the voltage at the output terminal N2 of the push-pull detection stage when the input terminal Vi is in the open state as in the third embodiment is (Vref−ΔV ) Can be reduced. The circuit threshold voltage of the gate circuit G1 is set to a value (Vref−ΔV + α) larger than (Vref−ΔV). In the fifth embodiment, as in the third embodiment, it is possible to take a large difference from the voltage of the output terminal N2 when the input is opened in consideration of the manufacturing variation of the circuit threshold value of the gate circuit G1. This is very effective in preventing the occurrence of malfunction due to. Since other operations and effects are the same as those of the third embodiment, description thereof will be omitted.

  Note that the pull-down resistor R1 in FIG. 3A may be replaced with an N-channel transistor RT1 set in a conductive state as shown in the detector 12b in FIG.

  Next, a sixth embodiment of the present invention will be described. In the sixth embodiment, the detector 12 in the circuit of the fourth embodiment (same as in FIG. 1) is replaced with the detector 12c in FIG. 4 (a). The detector 12c is obtained by adding a pull-up resistor R2 between the output terminal N2 of the push-pull type detection stage of the detector 12 and the power supply Vdd. The configuration of the other parts of the sixth embodiment is the same as that of the fourth embodiment, but the channel width of the transistor is preferably set to (WT4 / WT2) = (WT3 / WT1). In the sixth embodiment, by passing a current from the power source Vdd through the resistor R2, the voltage at the output terminal N2 of the push-pull type detection stage when the input terminal Vi is in the open state as in the fourth embodiment is (Vref + ΔV). Can be large. The circuit threshold voltage of the gate circuit G1 is set to a value (Vref + ΔV−α) smaller than (Vref + ΔV). Also in the sixth embodiment, as in the fourth embodiment, it is possible to take a large difference from the voltage at the output terminal N2 when the input is opened in consideration of the manufacturing variation of the circuit threshold value of the gate circuit G1. This is very effective in preventing the occurrence of malfunction due to. Since other operations and effects are the same as those in the fourth embodiment, description thereof will be omitted.

  Note that the pull-up resistor R2 in FIG. 4A may be replaced with a P-channel transistor set in a conductive state as shown in the detector 12d in FIG. 4B.

  Next, a seventh embodiment of the present invention will be described. In the seventh embodiment, the detectors 20a and 20b in FIG. 5 are provided in place of the detector 12 in the circuit (FIG. 1) of the first embodiment.

  The detector 20a includes a push-pull detection stage including a P-channel transistor T31 and an N-channel transistor T41 connected in series, a pull-down resistor R11, and a gate circuit G11.

  The detector 20b includes a push-pull detection stage including a P-channel transistor T32 and an N-channel transistor T42 connected in series, a pull-down resistor R12, and a gate circuit G12.

  The push-pull detection stage of the detector 20a includes a P-channel transistor T31 having a source connected to the power supply Vdd and a gate supplied with the first internal output signal S1, and a drain connected to the drain of the P-channel transistor T31. The output terminal N21 of the push-pull type detection stage is constituted by an N-channel transistor T41 having a gate supplied with the second internal output signal S2 and a source grounded.

  One end of the pull-down resistor R11 of the detector 20a is connected to the output end N21 of the push-pull detection stage, and the other end is grounded.

  Although the logic function of the gate circuit G11 of the detector 20a is not limited, an inverter is used in this embodiment, and its input terminal is connected to the output terminal N21 of the push-pull detection stage, and the output terminal is Connected to the output terminal Vo1.

  The push-pull detection stage of the detector 20b includes a P-channel transistor T32 whose source is connected to the power supply Vdd and whose gate is supplied with the first internal output signal S1, and whose drain is connected to the drain of the P-channel transistor T32. The output terminal N22 of the push-pull type detection stage is constituted by an N-channel transistor T42 to which the second internal output signal S2 is supplied to the gate and the source is grounded.

  One end of the pull-down resistor R12 of the detector 20b is connected to the output end N22 of the push-pull detection stage, and the other end is grounded.

  Although the logic function of the gate circuit G12 of the detector 20b is not limited, in the present embodiment, an inverter is used similarly to the gate circuit G11 of the detector 20a, and its input terminal is a push-pull type detection stage. The output terminal N22 is connected, and the output terminal is connected to the output terminal Vo2.

  Preferably, transistors having the same channel length and channel width are used for P-channel transistor T31 and P-channel transistor T32, and transistors having the same channel length and channel width are used for N-channel transistor T41 and N-channel transistor T42. Use.

  The resistance value of the first pull-down resistor R11 in the detector 20a is set larger than the second pull-down resistor R12 in the detector 20b. As a result, the voltage at the output terminal N21 of the push-pull detection stage of the detector 20a when the input terminal Vi is in an open state (and when a voltage equal to the reference voltage Vref is input as an input signal) is (Vref−ΔV1). The voltage at the output terminal N22 of the push-pull detection stage of the detector 20b is (Vref−ΔV2) (ΔV2> ΔV1).

  The circuit threshold voltages of the gate circuit G11 of the detector 20a and the gate circuit G12 of the detector 20b are the same voltage (which is larger than the voltage of the output terminal N21 of the push-pull detection stage of the detector 20a when the input terminal Vi is open). Vref−ΔV1 + α).

  In the seventh embodiment configured as described above, when the input terminal Vi is in an open state, a high level is output to both the output terminals Vo1 and Vo2. When an input signal is supplied to the input terminal Vi, when the input signal drops from a large voltage level and the input voltage becomes Vt71, the voltage at the output terminal N21 of the push-pull detection stage of the detector 20a is first (Vref−ΔV1 + α). ) And the gate circuit G11 of the detector 20a detects and the output terminal Vo1 outputs a low level. When the input signal further decreases and the input voltage becomes Vt72, the voltage at the output terminal N22 of the push-pull detection stage of the detector 20b becomes (Vref−ΔV1 + α), and the gate circuit G12 of the detector 20b detects and outputs the output terminal Vo2. Outputs a low level. Therefore, in this embodiment, it is possible to detect whether the input voltage at the input terminal Vi is greater than Vt71, between Vt71 and Vt72, or smaller than Vt72.

  In the present embodiment, the case where there are two detectors has been described. However, the present invention is not limited to this, and a configuration using three or more detectors is also possible. Also in this embodiment, there is no current path from the input terminal Vi to the power source Vdd as in the other embodiments, so that the current from the input terminal Vi to the power source Vdd is also present when the maximum value of the input signal is greater than the power supply voltage. Does not flow, and power supply voltage fluctuation due to the input signal does not occur.

  Next, an eighth embodiment of the present invention will be described. In the eighth embodiment, the detectors 21a and 21b in FIG. 6 are provided in place of the detector 12 in the circuit of the first embodiment (FIG. 1).

  The detector 21a has a pull-up resistor R21 having one end connected to the output end N21 of the push-pull type detection stage and the other end connected to the power source Vdd instead of the pull-down resistor R11 in the detector 20a of FIG. . The detector 21b has a pull-up resistor R22 having one end connected to the output end N22 of the push-pull type detection stage and the other end connected to the power supply Vdd instead of the pull-down resistor R12 in the detector 20b of FIG. .

  The resistance value of the pull-up resistor R21 of the detector 21a is set larger than the pull-up resistor R22 of the detector 21b. As a result, the voltage at the output terminal N21 of the push-pull detection stage of the detector 21a when the input terminal Vi is in an open state (and when a voltage equal to the reference voltage Vref is input as an input signal) becomes (Vref + ΔV1). The voltage of the output terminal N22 of the push-pull detection stage 21b is (Vref + ΔV2) (ΔV2> ΔV1).

  The circuit threshold voltages of the gate circuit G11 of the detector 21a and the gate circuit G12 of the detector 21b are the same voltage (less than the voltage of the output terminal N21 of the push-pull detection stage of the detector 21a when the input terminal Vi is in the open state ( Vref + ΔV1−α).

  In the eighth embodiment configured as described above, when the input terminal Vi is in an open state, a low level is output to both the output terminals Vo1 and Vo2. When an input signal is supplied to the input terminal Vi, when the input signal rises from a small voltage level and the input voltage becomes Vt81, first, the voltage at the output terminal N21 of the push-pull detection stage of the detector 21a is (Vref + ΔV1-α). ), The gate circuit G11 of the detector 21a detects and the output terminal Vo1 is inverted to a high level. When the input signal further increases and the input voltage becomes Vt82, the voltage at the output terminal N22 of the push-pull detection stage of the detector 21b becomes (Vref + ΔV1-α), and the gate circuit G12 of the detector 21b detects and outputs it. The terminal Vo2 is inverted to high level. Therefore, in this embodiment, it is possible to detect whether the input voltage at the input terminal Vi is smaller than Vt81, between Vt81 and Vt82, or larger than Vt82.

  In the present embodiment, the case where there are two detectors has been described. However, the present invention is not limited to this, and a configuration using three or more detectors is also possible. Also in this embodiment, there is no current path from the input terminal Vi to the power source Vdd as in the other embodiments, so that the current from the input terminal Vi to the power source Vdd is also present when the maximum value of the input signal is greater than the power supply voltage. Does not flow, and power supply voltage fluctuation due to the input signal does not occur.

It is a circuit diagram of one Example of the input circuit of this invention. It is an operation | movement timing diagram of 1st Example. (A), (b) is a circuit diagram of the detector in 5th Example. (A), (b) is a circuit diagram of a detector in the sixth embodiment. It is a circuit diagram of the some detector in a 7th Example. It is a circuit diagram of the some detector in an 8th Example. It is a circuit diagram of a conventional example.

Explanation of symbols

1 input circuit 11 operational amplifier 12, 12a, 12b, 12c, 12d, 20a, 20b, 21a, 21b detectors T1, T3, T31, T32 P-channel transistors T2, T4, T41, T42 N-channel transistors Vi input terminals Vo, Vo1 , Vo2 output terminal

Claims (11)

An input terminal, an output terminal,
An input resistor having one end connected to the input terminal;
A reference voltage is supplied to the positive phase input terminal, the negative phase input terminal is connected to the other end of the input resistor, the input of the negative phase input terminal is amplified and output from the first output terminal as the first internal output signal. An amplifier stage for outputting a second internal output signal from the output terminal of the first channel, a P-channel first transistor having a source connected to a first power supply and the gate supplied with the first internal output signal, and a drain A push-pull output having an N-channel second transistor connected to the drain of the first transistor and serving as an output terminal to which the second internal output signal is supplied to the gate and the source is connected to the second power source An operational amplifier including a stage;
A third transistor and drain of a P-channel, whose source is connected to the first power supply and the first internal output signal is supplied to the gate, are connected to the drain of the third transistor and serve as an output terminal to the gate. A push-pull detection stage having an N-channel fourth transistor to which a second internal output signal is supplied and whose source is grounded, and an input terminal is connected to an output terminal of the push-pull detection stage, and an output terminal is A gate circuit connected to the output terminal, and a detector,
An input circuit, wherein an output terminal of the push-pull output stage of the operational amplifier is connected to a negative phase input terminal of the amplification stage.   The input circuit according to claim 1, wherein a circuit threshold voltage of the gate circuit of the detector is set to a voltage higher than the reference voltage.   2. The input circuit according to claim 1, wherein a circuit threshold voltage of the gate circuit of the detector is set to a voltage smaller than the reference voltage.   When the channel width of the first transistor is WT1, the channel width of the second transistor is WT2, the channel width of the third transistor is WT3, and the channel width of the fourth transistor is WT4 (WT4 / 2. The input circuit according to claim 1, wherein the channel width of each transistor is set so as to satisfy WT2)> (WT3 / WT1).   When the channel width of the first transistor is WT1, the channel width of the second transistor is WT2, the channel width of the third transistor is WT3, and the channel width of the fourth transistor is WT4 (WT4 / 2. The input circuit according to claim 1, wherein the channel width of each transistor is set so as to satisfy WT2) <(WT3 / WT1).   The input circuit according to claim 1, further comprising a pull-down resistor provided between an output terminal of the push-pull type detection stage and the second power source in the detector.   The input circuit according to claim 6, wherein an N-channel transistor set to be in a conductive state is used as the pull-down resistor.   The input circuit according to claim 1, further comprising a pull-up resistor provided between an output terminal of the push-pull type detection stage and the first power source in the detector.   9. The input circuit according to claim 8, wherein a P-channel transistor set to be in a conductive state is used as the pull-up resistor.   The input circuit according to claim 6, further comprising at least one detector provided in parallel with the detector and having a pull-down resistance value different from that of the detector. The input circuit according to claim 8, further comprising one or more detectors provided in parallel with the detector and having a pull-up resistance value different from that of the detector.

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