JP2005109294A - Semiconductor integrated circuit, method and apparatus for designing the semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing the chip area and improving the noise resistance. <P>SOLUTION: In the semiconductor integrated circuit having a feeder 301 for feeding power to circuit elements, a ground line 302, and a signal line 303 which is disposed away from the feeder 301 and the ground line 302 and propagates signals, the semiconductor integrated circuit comprises extension parts 304, 305 which are connected to the feeder 301 and the ground line 302 and extend to the neighborhood of the signal line 303. The extension parts 304, 305 are connected to the feeder 301 and the ground line 302, are extended to the neighborhood of the signal line 303, and fill the space within the semiconductor integrated circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, a method for designing a semiconductor integrated circuit, and a processing apparatus.

  Conventionally, semiconductor integrated circuits such as LSI (Large Scale Integrated Circuit) have been used for various electronic devices.

  Conventionally, a structure called DWF (Dense Wire Fabric), in which power supply lines (feeding lines and ground lines) are always run side by side on both sides of the signal line, solves noise problems in deep sub-micron designs and reduces parasitic parameters. Improvement of extraction accuracy and improvement of manufacturability have been proposed (see Non-Patent Documents 1 and 2).

  In addition, as a design method for a semiconductor integrated circuit, a CPA (Cross Point Assignment) method is employed (see, for example, Non-Patent Documents 3 and 4). When designing a semiconductor integrated circuit using the CPA method, for example, when performing wiring processing between two terminals, the wiring processing area of the semiconductor chip is divided into a plurality of small wiring processing areas (small wiring areas) Schematic wiring that connects the two terminals through the plurality of small wiring processing areas is determined (global wiring processing), and at the boundary of each small wiring area through which wiring passes by the CPA method based on the schematic wiring Wiring processing of a semiconductor integrated circuit by determining a detailed position (virtual pin) and performing detailed wiring processing (detailed wiring processing) in a small wiring region that is lacking in a state where the condition of passing through the detailed position is satisfied Is completed.

Even using this CPA method, a semiconductor integrated circuit having a DWF structure can be designed.
Cross-talk noise Immune VSLI Design using Regular Layout Fabrics, Sunil Khatri, Robert Brayton, Alberto Sangiovanni-Vincentelli, 2001 Kluwer Academic Publishers (2001 Kluwer Academic Publishers) 1999 Conference on Automatic Wiring “Application of New VLSI Layout Structure to Submicron” (Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Alberto Sangiovanni-Vincentelli, Ralph HJM Otten 鄭 Novel VLSI Layout Fabric for Deep Sub-Micron Applications / Design Automation conference 1999) “Assignment of crosspoints with global wiring” published in the Journal of the Institute of Electrical and Electronics Engineers of Japan on CAD for semiconductor integrated circuits and systems (March 1995, Vol14, No3, pages 576-584) (Wen-Chung Kao and Tai -Ming Parn, "Cross Point Assignment with Global Routing", IEEE Transaction on Computer-Aided Design Of Integrated Circuits and System, Vol.14, No3, pp576-584, March 1995) "VLSI with crosstalk noise resistance using PLA network embedded in regular layout structure" at an international conference on CAD (Sunil P. Khatri, Alberto Sangiovanni-Vincentelli 鼎 ross-Talk Noise Immune in a Regular Layout Fabric / ICCAD2000)

  The conventional DWF structure has a very high noise resistance, and it is easy to compensate for the operational integrity of the IC. However, as described above, a power supply line and a ground line are always required on both sides of the signal line. There is a big problem in practical use.

  Special designs such as PLA (Programmable Logic Array) can reduce overhead, but ordinary ASIC (Application Specific IC) and cell-based designs such as processors do not meet the cost and constitute a major barrier. .

  An object of the present invention is to provide a semiconductor integrated circuit capable of reducing a chip area and improving noise resistance.

  Another object of the present invention is to provide a semiconductor integrated circuit design method capable of designing an integrated circuit capable of reducing the chip area and improving the noise resistance.

  According to the present invention, in a semiconductor integrated circuit having a power supply line for supplying power to a circuit element and a signal line that is spaced apart from the power supply line and propagates a signal, the power supply line A semiconductor integrated circuit characterized by comprising an extended portion connected and extending to the vicinity of the signal line is applied. The extending portion is connected to the power supply line, extends to the vicinity of the signal line, and fills the space in the semiconductor integrated circuit.

  Here, the power supply line and the signal line may be arranged in a direction intersecting each other, and the extending portion may be extended to the vicinity of the end portion of the signal line.

  The signal line and the extending portion may be arranged on the same layer.

  According to the present invention, the cell placement processing step in which the computer determines the placement of the cell using the netlist information, the design rule, the technology information, the cell information, the placement information, and the wiring characteristic information stored in the storage means. A power line generation processing step for generating a power line, a global wiring processing step for determining an approximate position of the wiring including the extending portion passing through each cell, and a detailed position through which the wiring passes by the CPA method. A CPA processing step for determining a virtual pin position; and a detailed wiring processing step for generating a signal line and a power supply line in each cell and generating an extended portion connected to the power supply line and extending to the vicinity of the signal line; A method for designing a semiconductor integrated circuit is provided.

  The computer uses the net list information, design rules, technology information, cell information, placement information and wiring characteristic information stored in the storage means to determine a cell placement processing step for determining the placement of the cell, and a power supply for generating the power supply line. A line generation processing step, a global wiring processing step for determining an approximate position of the wiring including the extending portion passing through each cell, and a CPA processing for determining a virtual pin position representing a detailed position through which the wiring passes by the CPA method And a detailed wiring processing step of generating a signal line and a power line in each cell and generating an extended portion connected to the power line and extending to the vicinity of the signal line.

  Here, the power supply line and the signal line may be arranged in a direction intersecting each other, and the extending portion may be extended to the vicinity of the end portion of the signal line.

  The semiconductor integrated circuit according to the present invention can reduce the chip area and improve the noise resistance.

  Further, according to the semiconductor integrated circuit design method of the present invention, it is possible to design an integrated circuit that can reduce the chip area and improve the noise resistance.

  FIG. 1 is a block diagram of a computer used in the embodiment of the present invention, and constitutes a semiconductor integrated circuit design apparatus.

  In FIG. 1, a semiconductor integrated circuit design apparatus constituted by a computer 100 includes an input device 101 constituted by a keyboard, a mouse, etc. and constituting an input means, a central processing unit (CPU) 102 constituting a design processing means, and a display means. A display device 103, a main storage device 104 constituted by a semiconductor memory, and an external storage device 105 constituted by a magnetic disk are provided.

  In the external storage device 105, a netlist information storage unit 107 that stores netlist information in advance, a design rule storage unit 108 that stores design rules such as line widths in advance, the number of layers, the height of layers, the dielectric constant, etc. A technology information storage unit 109 that stores technology information in advance, a cell information storage unit 110 that stores cell information related to cells such as cell types in advance, and an arrangement information storage unit 111 that stores arrangement information in advance are included.

  The net list information, design rules, technology information, cell information, and arrangement information constitute design information. The external storage device 105 also stores a semiconductor integrated circuit design processing program executed by the CPU 102. The main storage device 104 and the external storage device 105 constitute design information storage means.

  FIG. 2 is a flowchart showing a method for designing a semiconductor integrated circuit according to the present embodiment. The computer 100 develops a design processing program stored in advance in the external storage device 105 in the main storage device 104 and executes the program. The process performed by doing is shown.

  FIG. 3 is a diagram showing a wiring structure of the semiconductor integrated circuit according to the present embodiment, and shows a wiring structure designed by the design method of FIG. In FIG. 3, the power supply line includes a power supply line 301 having a positive potential or a negative potential, and a ground line 302 having a ground potential. The feeder line 301 and the ground line 302 are arranged in parallel to each other. A signal line 303 is arranged in a direction crossing the power supply line (a direction orthogonal in the present embodiment).

  In the power supply line 301, a conductive extension 304 is integrally formed by a via 306. In addition, a conductive extension 305 is integrally formed on the ground line 302 by a via 307. In FIG. 3, vias are indicated by squares.

  Conductive extensions 304 and 305 formed integrally with the power supply line are formed on the same layer as the signal line 303. The extending portions 304 and 305 are formed so as to extend to the vicinity of the end portion of the signal line 303.

  Hereinafter, the semiconductor integrated circuit and the method for designing the semiconductor integrated circuit according to the present embodiment will be described in detail with reference to FIGS.

  First, when a user (for example, a semiconductor integrated circuit designer) operates the input device 101, the computer 100 reads design information stored in the external storage device 105 into the main storage device 104. That is, the CPU 102 stores netlist information from the netlist information storage unit 107, design rules from the design rule storage unit 108, technology information from the technology information storage unit 109, cell information from the cell information storage unit 110, and arrangement information storage. The placement information is read from the unit 111, the wiring route information is read from the general wiring information storage unit 112, and the restriction information is read from the restriction information storage unit 113.

  Next, the computer 100 determines the detailed arrangement of the cells using the net list information, cell information, and technology information in the design information (step S201: cell arrangement processing step). Next, the computer 100 generates a mesh-shaped power supply line using the technology information (step S202: power supply line generation processing step). Next, the computer 100 performs global wiring (outline wiring) processing at a cell level using netlist information, technology information, arrangement information, and cell information, and performs wiring (extension part, power supply line, The approximate position of the signal line is determined (step S203: global wiring processing step).

  Next, the computer 100 determines a virtual pin position representing a detailed position through which the wiring passes by a known CPA method using the wiring path information and the cell information (step S204: CPA processing step). Thereby, the passage position of the wiring at the boundary position of each Gcell is indicated by the virtual pin.

  The computer 100 uses the technology information and the constraint information for compensation of signal integrity in each Gcell so that the signal line and the power supply line satisfy the boundary condition that each wiring passes through the virtual pin. And an extension portion connected to the power supply line and extending to the vicinity of the signal line is generated to fill the space of the semiconductor integrated circuit with the extension portion (step S205: detailed wiring processing step).

  The computer 100 temporarily stores the design information (Gcell information) of the semiconductor integrated circuit obtained as described above in the main storage device 104, and then stores the file in the external storage device 105 (or other storage means). It is output and stored as (for example, DEF format) (step S206).

  In this way, design information (Gcell information) of the semiconductor integrated circuit as shown in FIG. 3 is obtained. The power supply line (feed line 301 and ground line 302) and the signal line 303 are arranged in a direction crossing each other (for example, a direction orthogonal to each other), and the extended portions 304 and 305 extend to the vicinity of the end of the signal line 303. . Further, the signal line 303 and the extending portions 304 and 305 are disposed on the same layer.

  According to the semiconductor integrated circuit configured as described above, since the extended portions 304 and 305 are provided in the space region of the semiconductor integrated circuit chip, the chip area can be reduced.

  Conventionally, since the floating wiring is provided between the signal lines, noise resistance performance and the like have been unstable. However, in this embodiment, the conductive extensions 304 and 305 connected to the power supply line are used. Therefore, an excellent shielding effect can be obtained, and a decoupling capacitor can be formed, so that a semiconductor integrated circuit having excellent noise resistance can be configured.

  Further, it is possible to improve the yield during polishing by CMP (Chemical Mechanical Polising).

  Further, according to the method for designing a semiconductor integrated circuit according to the present embodiment, it is possible to design a semiconductor integrated circuit having excellent noise resistance as described above.

It is a block diagram of a computer used for an embodiment of the invention. It is a flowchart which shows the process of the design method of the semiconductor integrated circuit which concerns on embodiment of this invention. It is a figure which shows the wiring structure of the semiconductor integrated circuit which concerns on embodiment of this invention.

Explanation of symbols

101 ... Input device constituting input means 102 ... CPU constituting design processing means
103 ... Display device 104 constituting display means ... Main storage device 105 constituting design information storage means ... External storage device 107 constituting design information storage means ... Netlist information storage unit 108 Design rule storage unit 109 ... Technology information storage unit 110 ... Cell information storage unit 111 ... Placement information storage unit 112 ... Outline wiring information storage unit 113 ... Restriction information storage unit 301 ... Power supply line 302 constituting the power supply line ... Ground line 303 constituting the power supply line ... Signal lines 304, 305 ... Extending portions 306, 307 ... vias

Claims (6)

In a semiconductor integrated circuit having a power supply line for supplying power to a circuit element, and a signal line disposed apart from the power supply line for propagating a signal,
A semiconductor integrated circuit comprising: an extension portion connected to the power supply line and extending to the vicinity of the signal line.   2. The semiconductor integrated circuit according to claim 1, wherein the power supply line and the signal line are arranged in a direction crossing each other, and the extending portion extends to the vicinity of an end portion of the signal line.   3. The semiconductor integrated circuit according to claim 1, wherein the signal line and the extending portion are disposed on the same layer.   Cell placement processing step for determining cell placement using netlist information, design rules, technology information, cell information, placement information and wiring characteristic information stored in storage means, and power supply line creation processing for generating power supply lines A global wiring processing step for determining an approximate position of the wiring including an extending portion passing through each cell, a CPA processing step for determining a virtual pin position representing a detailed position through which the wiring passes by a CPA method, And a detailed wiring processing step for generating a signal line and a power line in each cell and generating an extended portion connected to the power line and extending to the vicinity of the signal line. Circuit design method.   5. The method of designing a semiconductor integrated circuit according to claim 4, wherein the power supply line and the signal line are arranged in a direction intersecting each other, and the extending portion extends to the vicinity of an end portion of the signal line. Storage means for storing netlist information, design rules, technology information, cell information, placement information and wiring characteristic information;
Cell placement processing means for determining cell placement using netlist information, design rules, technology information, cell information, placement information and wiring characteristic information stored in the storage means;
Power line generation processing means for generating a power line;
A global wiring processing means for determining an approximate position of wiring including an extending portion passing through each cell;
CPA processing means for determining a virtual pin position representing a detailed position through which the wiring passes by a CPA method;
In each of the cells, a semiconductor integrated circuit comprising: detailed wiring processing means for generating a signal line and a power supply line and generating an extended portion connected to the power supply line and extending to the vicinity of the signal line Circuit design equipment.