JP2005108085A - Interlock device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interlock device making only a specific signal effective for surely prohibiting overlapping action when a plurality of signals are inputted. <P>SOLUTION: This interlock device 2 is provided with a setting means 21, which sets an interlock condition allowing output of a predetermined input signal according to a combination of a plurality of condition signals, and an interlock means 22 outputting the predetermined input signal when the interlock condition in the setting means 21 is satisfied and prohibiting output of the predetermined input signal when the interlock condition is not satisfied. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an interlock device, and more particularly to an interlock device capable of prohibiting output of a signal input according to a combination condition of a plurality of condition input signals.

  In various production sites and the like, a manufacturing apparatus is configured by electromagnetic valves, motors, and other electric devices. Such an electric device is generally connected to and controlled by a PLC (Programmable Logic Controller), a personal computer (hereinafter referred to as a personal computer) or the like via a signal line (hereinafter simply referred to as a signal line) such as a network or a conductive wire. For this reason, there is a risk of various malfunctions. That is, a malfunction caused by a human operation error, a malfunction of a CPU of a PLC or a personal computer, a malfunction due to a bug in a program, a malfunction caused by a network or the like due to noise superimposed on a signal line, or the like. Furthermore, there are many scenes where improvement in safety is required by preventing malfunction such as control of gas that is dangerous when mixed, such as in the manufacturing site of semiconductor devices.

  Conventionally, in order to prevent such a malfunction, an interlock device is configured by software on a program of a PLC or a personal computer (see Patent Document 1). The interlock device is a circuit that prevents the output from being turned on until a certain condition is satisfied, and is intended to protect the device and ensure the safety of the operator. It is used to control the forward and reverse rotation of the motor and the double solenoid solenoid valve. However, the PLC, the CPU of the personal computer, and the program (hereinafter referred to as PLC etc.) themselves may malfunction. In addition, when noise is superimposed on a signal line that connects a PLC or the like and an electric device or the like, information (control signal) output from the PLC or the like may not be accurately given to the controlled device side. Therefore, even the current interlock device cannot completely prevent malfunction. An interlock device that detects output information using hardware such as a switch, a relay, and a general-purpose logic IC has been proposed (see Patent Document 2). However, if the amount of information to be detected is large, the installation space becomes large. .

  In addition to the purpose of preventing such malfunctions, the interlock device is used for the purpose of prohibiting other operations during certain work in order to ensure safety, such as prohibiting the unlocking of the guard lock of the device during operation. Sometimes. As an interlock device used for such a purpose, a safety switch with a solenoid, a safety plug, and the like are already known. However, since the safety switch and the safety plug are made for a specific (individual) application, the place of use, the purpose of use, and the method of use have been limited. A safety device called a safety relay module has also been proposed. However, this is a safety circuit for the purpose of surely operating an emergency stop button, a safety switch, etc. or detecting a failure, and is different from an interlock device for preventing malfunction.

  Furthermore, there is no interlock device that has a plurality of inputs and outputs corresponding to each of them and outputs only the first input channel (control signal).

Therefore, the applicant of the present application has previously proposed an interlock device that enables only a specific signal (channel or control signal) to be effectively prohibited when a plurality of signals are input, and can reliably prevent duplicate operations. (See Patent Document 3).
JP 59-70052 A Japanese Patent Laid-Open No. 5-322951 Japanese Patent Laid-Open No. 2003-223201

  According to the interlock device described in Patent Document 1, the possibility of malfunction can be extremely reduced, and the effective range of interlock can be freely set for many control signals with a relatively simple configuration. it can.

  However, this interlock device validates only one specific signal among a plurality of signals and invalidates the remaining signals. Therefore, it is not assumed that a certain signal is validated when the condition is satisfied by a combination of a plurality of condition signals, and the signal is invalidated when the condition is not satisfied. Further, according to the interlock device, it is not assumed that a predetermined signal is received from the outside and an error is forcibly generated based on the predetermined signal.

  An object of the present invention is to provide an interlock device capable of prohibiting the output of a signal input according to a combination of a plurality of condition input signals.

  The interlock device of the present invention includes a setting unit that sets an interlock condition for permitting output of a predetermined input signal by a combination of a plurality of condition signals, and an interlock condition of the setting unit when an input signal is input. Interlock means for outputting the predetermined input signal when the condition is satisfied and prohibiting the output of the predetermined input signal when the condition is not satisfied.

  According to the interlock device of the present invention, a predetermined input signal is output when an interlock condition determined by a combination of a plurality of condition signals is satisfied, and the output of the predetermined input signal is prohibited when the interlock condition is not satisfied. be able to. Therefore, by providing the interlock device of the present invention between the control-side output device and the controlled-side load (electric device), there is a possibility of malfunction of PLC, PC CPU, program (PLC, etc.), In addition, the possibility of malfunction due to noise superimposed on the signal line or the like can be suppressed to a very low level, and it is possible to more reliably prevent human operation errors or the like or electrical malfunctions on the control side. In addition, the interlock condition can be set using a combination of multiple condition signals with a relatively simple configuration, and it can operate regardless of the place of use, purpose of use, and method of use, in addition to the purpose of preventing malfunction. It can be used for the purpose of prohibiting other operations during certain work to ensure safety, such as prohibiting the unlocking of the guard lock of the inside device.

  FIG. 1 is a block diagram of an interlock system, showing a configuration of an interlock system using the interlock device of the present invention.

  The interlock device 2 is inserted between an output device 11 of a control device (or network) 1 such as a computer and a load (controlled device or electric device) 3 to prevent malfunction. They are connected to each other by signal lines 41 and 42 such as conducting wires. As a result, a final output signal (control signal) for the load 3 is output from the interlock device 2. That is, for a plurality of input signals on the signal line 41, the output of input signals that should not be output simultaneously with (or after) the input signal currently being output (or output in the past) on the signal line 42 is prohibited. After that, an input signal that can be output is output on the signal line 42. This prevents malfunction of the electric device 3 due to the output device 11 and the signal line 41 side.

  The interlock device 2 in this example is connected to the input device 12 of the control device 1 via the signal line 43. A plurality of condition signals input from the interlock condition input unit 5 to the interlock device 2 are directly input from the interlock device 2 (condition signal output means 24) to the input device 12.

  Further, the interlock condition input unit 5 and the external error signal input unit 6 are connected to the interlock device 2 of this example via signal lines 44 and 45, respectively. The interlock condition input unit 5 inputs a plurality of condition signals for setting the interlock condition in the setting means 21 to the interlock device 2 (the setting means 21 and the condition signal output means 24). The external error signal input unit 6 inputs an external error signal for forcing the interlock device 2 to output an error signal to the interlock device 2 (the error output means 23 thereof).

  As shown in FIG. 1, the interlock device 2 includes a setting unit 21, an interlock unit 22, an error output unit 23, a condition signal output unit 24, and an error detection unit 25. The error detection means 25 is provided in the error output means 23 (or the interlock means 22).

  The setting means 21 sets an interlock condition that permits the output of a predetermined input signal by a combination of a plurality of condition signals. The plurality of condition signals are input from the interlock condition input unit 5 via the signal line 44. The setting means 21 determines which one of a plurality of condition signals is used by means such as a circuit configuration, a combination of switches, or a command input. In this example, the plurality of condition signals include sensor signals output from a plurality of sensors (for example, pressure sensors) that detect the state of the electrical device 3 to which the signal output from the interlock device 2 is input. That is, eight (8 channels) pressure signals No. 1-8.

  When the input signal is input, the interlock unit 22 outputs a predetermined input signal when the interlock condition of the setting unit 21 is satisfied, and prohibits the output of the predetermined input signal when the input signal is not satisfied. The input signal is input from the output device 11 via the signal line 41. Thereby, when the input signal is input from the output device 11, the interlock device 2 outputs a predetermined input signal when the interlock condition of the setting unit 21 is satisfied, and operates by the input signal, for example. The output of the input signal is permitted when the conditions under which the electrical device 3 can operate safely are satisfied, and the output is forcibly prohibited when the conditions are dangerous when the electrical equipment 3 operates.

  The error output means 23 outputs an error based on the error detection by the error detection means 25. That is, the error detection unit 25 detects a failure in the interlock unit 22. Thereby, the error output means 23 generates and outputs an error signal when the error detection means 25 detects a failure of the interlock means 22, and stops the output of the interlock device 2. For example, the error detection unit 25 detects a failure of the output transistor of the interlock unit 22. In addition, the error output means 23 can turn off the load 3 by a relay. As a result, it is possible to prevent malfunction due to a failure of the interlock device 2 itself, and to improve safety.

  Further, the error output means 23 outputs an error based on an external error signal input from the outside of the interlock device 2. That is, the external error signal input unit 6 inputs an external error signal. For example, the external error signal input unit 6 is an error signal for the entire device that is output from a device or the like in which the interlock device 2 is incorporated, and the interlock device 2 is operated under conditions other than the failure of the interlock device 2 itself. Output when you want to forcibly stop. As a result, the error output means 23 generates and outputs an error signal in a predetermined case, stops the output of the interlock device 2, turns off the load 3 with a relay as described above, and further improves safety. Can be improved.

  The condition signal output unit 24 directly outputs a plurality of condition signals (pressure signals No. 1 to 8) input from the interlock condition input unit 5 for setting the interlock condition in the setting unit 21 to the outside of the interlock device 2. Output to. The plurality of condition signals output from the condition signal output means 24 are input to the input device 12 that constitutes the control device 1 together with the output device 11 that inputs a plurality of input signals to the interlock device 2 via the signal line 43. Is done. As a result, the condition signal used to set the interlock condition can be output as it is and used for other purposes.

  Since the interlock device 2 operates by itself, it is possible to prevent malfunction on the output device 11 side such as a PLC, a personal computer, or a network. In addition, the interlock device 2 can be used regardless of the type of the output device 11 and the load 3, and the interlock signal can be freely combined by the interlock disable switch to disable the interlock. For this reason, versatility can be made very high.

  2 and 3 are block diagrams of the interlock device, and show an example in which the interlock device 2 of the present invention is configured using a PLD (Programmable Logic Device) and is downsized. In particular, FIG. 2 shows the connection relationship of the interlock device 2, and FIG. 3 shows the configuration of the interlock device 2. In this example, the setting means 21 and other means are configured by hardware.

  In this example, the input signals (IN1 to IN8) and the output signals (OUT1 to OUT8) to the interlock device 2 are respectively No. 1 to 8 (8 channels), for example, 8 electromagnetic valves are controlled by the output signal. No. 1 to 8 input signals are signals to be interlocked. Depending on the state of the condition signal (in this example, pressure signals No. 1 to 8), No. The input signal of 1 is set as a valid output, or the output is prohibited (interlocked). In FIG. 3, various Nos. 1 shows the configuration of signal 1.

  No. input from the output device 1 to the interlock device 2. The 1 input signal (IN1) is inverted by the inverter (signal in1) and then input to the AND gate circuit AND1. The AND gate circuit AND1 is No. 1 corresponding to one input signal.

  Interlock disable switch (hereinafter referred to as disable switch) SW1 is No. 1 corresponding to one input signal. The disable switch SW1 is No. The range of the condition signal used for one input signal is determined. For this reason, no. Individual switches 1 to 8 corresponding to condition signals 1 to 8 are provided. Pull-up resistors are connected to the output terminals of the individual switches 1 to 8, respectively. For example, when individual switch 1 is opened (turned off), No. No. 1 condition signal is used, and when it is closed (turned on), No. 1 It is determined that the 1 condition signal is not used. The output of the individual switch 1 is SW1-1. SW1-1 is inverted and then input to the corresponding OR gate circuit OR1-1. Similarly, the other SW1-2 to SW1-8 are also input (not shown) to corresponding OR gate circuits OR1-2 to OR1-8 (not shown).

  Therefore, no. When one input signal is considered, eight OR gate circuits OR1-1 to OR1-8 are provided. The outputs SW1-1 to SW1-8 of the individual switches 1 to 8 are input to one input terminal of each of the eight OR gate circuits OR1-1 to OR1-8. The other input terminal of each of the eight OR gate circuits OR1-1 to OR1-8 has a pressure signal No. as a condition signal. Signals formed based on 1 to 8 (output signals of exclusive OR (gate circuits) EXOR1 to EXOR8) are input.

  No. 2 in FIG. 1 is a condition signal input to the interlock device 2 from the pressure sensor 1. 1 is input to one input terminal of the corresponding exclusive OR EXOR1 through the protection circuit. The exclusive OR EXOR1 is the pressure signal No. 1 is provided. The protection circuit is configured by connecting a Zener diode and a resistor in parallel. 1 to prevent an excessive current from flowing through the pressure sensor. Similarly, the pressure signal No. Corresponding to 2-8, although not shown, eight protection circuits and exclusive ORs EXOR2-8 are provided.

  The polarity switch PSW is a pressure signal No. used as a condition signal. 1-No. The polarity of each of 8 is defined. Therefore, the polarity switch PSW is connected to the pressure signal No. 1-No. 1 corresponding to the pressure signal No. Individual switches 1 to 8 corresponding to 1 to 8 are provided. Pull-up resistors are connected to the output terminals of the individual switches 1 to 8, respectively. The output terminals of the individual switches 1 to 8 are input to the other input terminals of the exclusive ORs EXOR1 to EXOR8, respectively.

  Thereby, for example, when the individual switch 1 is opened (turned off), the pressure signal No. It is determined that a high level is output from the exclusive OR EXOR1 in response to a low level of 1 and is closed (turned on). It is determined that a high level is output from the exclusive OR EXOR1 according to a high level of 1 (the reverse may be true). That is, the pressure signal No. A polarity of 1 is defined. Similarly, the other individual switches 2 to 8 have the pressure signal No. Define a polarity of 2-8.

  Therefore, in this example, eight pressure signals No. 8 corresponding to 1 to 8 and 8 exclusive ORs EXOR1 to 8 and 8 pressure signals No. The setting means 21 is composed of one polarity switch PSW including the individual switches 1 to 8 corresponding to 1 to 8. Further, the pressure sensor No. 1 shown in FIG. 1 to 8 are used as the interlock condition input unit 5.

  As described above, the outputs of the eight exclusive ORs EXOR1 to EXOR1 to 8 are input to the other input terminals of the eight OR gate circuits OR1-1 to OR1-8 corresponding to the disable switch SW1. Thereby, for example, when the individual switch 1 is opened (turned off), the pressure signal No. 1 is output (validated) from the OR gate circuit OR1-1 and closed (turned on) when the pressure signal No. 1 is output. A high level is output from the OR gate circuit OR1-1 regardless of the output of the exclusive OR EXOR1 based on 1 (the signal based on the pressure signal No. 1 is invalidated). The same applies to the outputs of the other OR gate circuits OR1-2 to OR1-8. Accordingly, the individual switches 1 to 8 of the disable switch SW1 cause the pressure signal No. as a condition signal. Which of 1 to 8 is used as an interlock condition is determined.

  The outputs of the eight OR gate circuits OR1-1 to OR1-8 are input to the AND gate circuit AND1. An error signal err is input to the AND gate circuit AND1. The output out1 of the AND gate circuit AND1 is input to the base of the output transistor T (O) 1, inverted, and output as the output OUT1. The output transistor T (O) 1 is connected to an AND gate circuit AND1, that is, No. 1. 1 corresponding to one input signal.

  In summary, the interlock means 22 of this example is No. It consists of eight unit circuits corresponding to each of eight input signals 1 to 8. One unit circuit is No. As for the input signal 1, it comprises a disable switch SW 1, an inverter, an AND gate circuit AND 1, an output transistor T (O) 1, and eight OR gate circuits OR 1-1 to OR 1-8 corresponding to the disable switch SW 1. Other unit circuits have the same configuration. Accordingly, in the eight unit circuits, for example, the OR signal OR. The output of the exclusive OR EXOR1 based on 1 is input. The same applies to the other OR gate circuits OR1-2 to OR1-8.

  On the other hand, in the setting means 21, for example, the pressure signal No. 1 is input to the base of the output transistor T (S) 1 after being inverted by the inverter through the protection circuit of the setting means 21 and output after being inverted. That is, the same pressure signal No. as the original signal. 1 is obtained as an output. Pressure signal No. which is another condition signal. 2-No. The same applies to 8. Therefore, in this example, the condition signal output means 24 has the pressure signal No. 8 which is eight condition signals. 1-No. In order to correspond to 8, eight inverters and output transistor T (S).

  Further, from the interlock means 22, no. For the input signal of 1, the output out1 of the AND gate circuit AND1 and the inverted signal of the output of the output transistor T (O) 1 are input to the exclusive OR EXOR (ER) 1. Therefore, when the output out1 and the inverted signal of the output of the output transistor T (O) 1 do not match, the failure of the output transistor T (O) 1 is detected by the high level of the output of the exclusive OR EXOR (ER) 1. Is done. The output of the exclusive OR EXOR (ER) 1 is input to the OR gate circuit OR. No. 2-No. Similarly, for the input signal 8, the outputs of the exclusive ORs EXOR (ER) 2 to EXOR (ER) 8 (none of which are shown) are input to the OR gate circuit OR. An external error signal from the external error signal input unit 6 is input to the OR gate circuit OR.

  The output ERR of the OR gate circuit OR is input to the base of the error signal output transistor T (ERR), inverted (output as an error signal ERR), and output. Thereby, an electric current flows into the error indicator ERRLED which consists of LED, and LED light-emits. Further, a current also flows through the relay (NC), the circuit is cut off, and the supply of 24V power (to the electrical equipment 3) is cut off. As a result, even if a failure occurs in the interlock device 2 (actually, the output transistors T (O) 1 to T (O) 8), the load 3 can be turned off to further improve safety. it can. Similarly, the error signal ERR is output (forcedly) according to the high level of the external error signal, the LED emits light, and the supply of power to the electrical device 3 is cut off.

  The output ERR of the OR gate circuit OR is inverted by the inverter and input to the AND gate circuit AND1 as the signal err. Therefore, when the output ERR is high, the AND gate circuit AND1 is closed by the low level signal err, and the output of the output transistor T (O) 1 is prohibited. Similarly, the signals err are input to the other AND gate circuits AND2 to AND8. As a result, the output of the other output transistors T (O) 2 to T (O) 8 is prohibited.

  As described above, the error detection means 25 in this example is No. 1-No. Eight exclusive ORs EXOR (ER) 1 to EXOR (ER) 8 corresponding to eight input signals of eight, eight inverters forming inputs to these, one OR gate circuit OR, And an inverter receiving the output of one OR gate circuit OR. In addition to the error detection means 25, the error output means 23 in this example includes one error signal output transistor T (ER), one error indicator ERRLED, and one relay.

  3 generates a power supply voltage of 5V from a power supply of 24V. This 5 V power supply voltage is supplied to each gate circuit and pull-up resistor.

  The interlock operations realized by the interlock device 2 of the present invention described above are summarized as follows.

  In the following examples, for example, No. 1 input signal, the pressure signal No. 2 and no. 3, the other pressure signal No. 1, no. 4-No. The interlock condition is determined without using 8. The interlock condition is the pressure signal No. 2 and no. 3 are output together (high level). For example, as shown in FIG. 2 and no. No. 3 corresponding to the input signals (IN2 and IN3) of No.3. 2 and no. If the solenoid valves 2 and 3 are not opened by the output signals (OUT2 and OUT2) of No. 3, no. No. 1 corresponding to the input signal (IN1). This is a case where the solenoid valve 1 should not be opened by an output signal (OUT1) of 1.

  First, the initial state of the interlock device 2 is set. That is, the individual switches 2 and 3 of the disable switch SW1 are opened (turned off), and the pressure signal No. 2 and no. 3 is used, and individual switches 1 and 4 to 8 are closed (turned on). 1, no. 4-No. 8 specifies that the condition signal is not used. Also, the individual switches 2 and 3 of the polarity switch PSW are opened (turned off), and the pressure signal No. 2 and no. It is determined that a high level is output from the exclusive ORs EXOR2 and EXOR3 according to the high level of 3.

  Thereafter, the operation of the interlock device 2 and the like is started. At first, if all the eight solenoid valves 1 to 8 are closed, the pressure signal No. 2 and no. 3 is a low level. Accordingly, when the individual switches 2 and 3 of the polarity switch PSW are turned off, the outputs of the exclusive ORs EXOR2 and EXOR3 become low level. Accordingly, when the individual switches 2 and 3 of the disable switch SW1 are turned off, the outputs of the OR gate circuits OR1-2 and OR1-3 become low level. Further, when the individual switches 1, 4 to 8 of the disable switch SW1 are turned on, the pressure signal No. 1, no. 4-No. Regardless of 8, the outputs of the OR gate circuits OR1-1, OR1-4 to OR1-8 are at a high level.

  Since no error has occurred at this time, the signal ERR output from the OR gate circuit OR is at the low level, and the signal err is at the high level. Therefore, no. Regardless of the value of the input signal 1, the output of the AND gate circuit AND 1 is at a low level, the output transistor T (O) 1 is not turned on, No input signal of 1 is output. That is, no. 1 is the pressure signal No. 2 and no. 3 Interlocked (by low level).

  Next, the solenoid valves 2 and 3 are opened and the pressure signal No. 2 and no. 3 becomes a high level, and the outputs of the exclusive ORs EXOR2 and EXOR3 also become a high level. Accordingly, the outputs of the OR gate circuits OR1-2 and OR1-3 are at a high level. The outputs of the OR gate circuits OR1-1 and OR1-4 to OR1-8 are at a high level.

  Thereby, since the signal err is at a high level, the AND gate circuit AND1 is opened. That is, no. For an input signal of 1, the interlock state is released. Therefore, the output of the AND gate circuit AND1 is No. 1 is inverted by the output transistor T (O) 1, and the output OUT1 is No.1. 1 input signal is output.

  In any of the above states, the pressure signal No. 1-No. 8 is connected to the pressure signal No. 8 via the output transistors T (S) 1 to T (S) 8. 1-No. 8 is output as it is. At this time, the output delay may be ignored.

  If the input and output of the output transistor T (O) 1 do not match after the AND gate circuit AND1 is opened, the output of the exclusive OR EXOR (ER) 1 becomes high level. As a result, the output ERR of the OR gate circuit OR becomes high level, the error signal output transistor T (ER) is turned on, the LED emits light, and the supply of power to the electrical device 3 is interrupted. The same applies before the AND gate circuit AND1 is opened. Further, the error signal ERR is similarly output according to the high level of the external error signal, the LED emits light, and the supply of power to the electrical device 3 is cut off.

  FIG. 4 is another block diagram of the interlock device, and shows an example in which the interlock device 2 of FIGS. 1 to 3 is configured by using a photo moss relay (a relay composed of a photodiode and a MOSFET) to reduce the size.

  The photo MOS relay shown in FIG. 4 is an A contact type. When the power is turned on, the photo MOS err is turned on because the err input is the B contact. In FIG. 3-No. No. 7 photo moss is No. 7. 1, no. 2, No. Since it is the same structure as 8 photomoss, illustration is abbreviate | omitted.

  When the signal in1 is input in this state, at this time, the pressure sensor No. 1-No. Since No. 8 is off, photo moss no. 1-No. 8 is also off. Therefore, even if the signal in1 is input, it is not output to the output out1. Next, pressure sensor No. 1-No. When all 8 are turned on at the same time, photo moss no. 1-No. Since 8 is also turned on, the signal in1 is output to the output out1. Here, when an error occurs, the B contact of the err input is turned off, the photo moss err is turned off, and the signal in1 is not output to the output out1. Since the on / off signal of the pressure sensor can be invalidated by making the photo moss conductive using the invalid switch, the interlock condition of the signal in1 can be set.

  FIG. 5 is another block diagram of the interlock device, and shows an example in which the interlock device 2 of the present invention is configured by a program executed on a microcomputer. That is, in this example, the interlock processing unit 26 is configured by configuring the setting unit 21 and other units by software.

  Even when the interlock processing unit 26 is realized by a program, it is desirable that the disable switches SW1 to SW8 and the polarity switch PSW are individually provided as hardware outside the interlock processing unit 26. This makes it possible to change the interlock condition or change the polarity of the condition signal without changing the program.

  FIG. 6 shows an interlock processing flow executed by the interlock processing unit 26 in the interlock device 2 of FIG.

  The initialization state of the microcomputer constituting the interlock device 2 (or the interlock processing unit 26) is set, the input / output pins (terminals), the disable switches SW1 to SW8 and the polarity switch PSW are set (step S10). The first input signal is read (held) (step S11), and it is checked whether or not the input has changed from the previous state (step S12). If not, step S12 is repeated. If there is a change, after chattering is avoided (step S13), it is checked again whether there is a change in input (step S14). If there is a change in input from step S12, it is determined as noise, Step S12 is repeated. If there is no change in input from step S12, an interlock process is performed according to the settings of the disable switches SW1 to SW8 and the polarity switch PSW (step S15), and an input signal is output accordingly (step S16).

  As mentioned above, although this invention was demonstrated according to the embodiment, this invention can be variously deformed in the range of the main point.

  For example, the interlock device 2 can be configured by various methods other than the above-described means. For example, it can be realized by a switch or a relay, and can also be realized by a logic IC.

  The interlock device 2 of the present invention can also be applied to a system that does not use a control device. For example, the present invention can be applied to a system that does not use a control device such as a PLC or a personal computer or a network, and includes only an output device 11 such as a switch or a sensor and an electric device 3 such as a motor or a solenoid valve. It is. Therefore, it can be used as a simple interlock device 2 without creating a program or designing a complicated circuit.

  The interlock device 2 of the present invention can also be applied to a system using a control device. For example, in a system using a network such as a fieldbus for FA, which is controlled using a PLC or a personal computer, the interlock device 2 is inserted between the network output unit and the output device 11. Alternatively, when the network is not used, the interlock device 2 can be used immediately before the output device 11 as an interlock filter that prevents human, electrical, and software malfunctions of the control system. Furthermore, by supplying the condition signal output from the interlock device 2 to a PLC, a personal computer, etc., the (hardware) interlock by the interlock device 2 and the (software) interlock by the PLC, personal computer, etc. Thus, it is possible to interlock double.

  As described above, according to the present invention, in the interlock device, a predetermined input signal is output when an interlock condition defined by a combination of a plurality of condition signals is satisfied, and a predetermined input is input when the interlock condition is not satisfied. Signal output can be prohibited. Therefore, by providing the interlock device of the present invention between the control-side output device and the controlled-side load (electric device), there is a possibility of malfunction of PLC, PC CPU, program (PLC, etc.), In addition, the possibility of malfunction due to noise superimposed on the signal line or the like can be suppressed to a very low level, and it is possible to more reliably prevent human operation errors or the like or electrical malfunctions on the control side. In addition, the interlock condition can be set using a combination of multiple condition signals with a relatively simple configuration, and it can operate regardless of the place of use, purpose of use, and method of use, in addition to the purpose of preventing malfunction. It can be used for the purpose of prohibiting other operations during certain work to ensure safety, such as prohibiting the unlocking of the guard lock of the inside device.

It is an interlock system block diagram. It is an interlock device block diagram. It is an interlock device block diagram. It is another interlock device block diagram. It is another interlock device block diagram. It is an interlock process flow.

Explanation of symbols

1 Control equipment 2 Interlock device 3 Electrical equipment (load)
5 Interlock Condition Input Unit 6 External Error Signal Input Unit 21 Setting Unit 22 Interlock Unit 23 Error Output Unit 24 Condition Signal Output Unit 25 Error Detection Unit

Claims (6)

Setting means for setting an interlock condition that permits output of a predetermined input signal by a combination of a plurality of condition signals;
An interlock unit that outputs the predetermined input signal when an interlock condition of the setting unit is satisfied and an output of the predetermined input signal is not satisfied when the input signal is input; An interlock device comprising: In claim 1, further comprising:
An interlock device comprising: condition signal output means for outputting the plurality of condition signals as they are. In claim 1,
The plurality of condition signals output from the condition signal output means are input to an input device that constitutes a control device together with an output device that inputs the plurality of input signals to the interlock device. . In claim 1,
The interlock device is characterized in that the plurality of condition signals include sensor signals output from a plurality of sensors that detect a state of an electric device to which a signal output from the interlock device is input. In claim 1, further comprising:
Error detection means for detecting a failure in the interlock means;
An interlock device comprising error output means for outputting an error based on error detection by the error detection means. In claim 1, further comprising:
An interlock device comprising error output means for outputting an error based on an external error signal input from the outside.

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