JP2005101647A5 - - Google Patents
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- JP2005101647A5 JP2005101647A5 JP2004335811A JP2004335811A JP2005101647A5 JP 2005101647 A5 JP2005101647 A5 JP 2005101647A5 JP 2004335811 A JP2004335811 A JP 2004335811A JP 2004335811 A JP2004335811 A JP 2004335811A JP 2005101647 A5 JP2005101647 A5 JP 2005101647A5
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前記メモリセル選択用ＭＩＳＦＥＴおよび前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴを覆い、かつその表面が平坦化された第１絶縁膜を形成する工程、
前記メモリセルアレイ領域の前記第１絶縁膜上にビット線を、前記周辺回路領域または前記ロジック回路領域の前記第１絶縁膜上に前記ビット線と同一の材料からなる第１層配線を形成する工程、
前記ビット線および前記第１層配線を覆い、かつその表面が平坦化された第２絶縁膜を前記メモリセルアレイ領域および前記周辺回路領域または前記ロジック回路領域上に形成する工程、
前記メモリセルアレイ領域の前記第２絶縁膜の上部にストッパ膜を形成する工程、
前記ストッパ膜上に第３絶縁膜を形成する工程、
前記メモリセルアレイ領域の前記第３絶縁膜に情報蓄積用容量素子の下部電極、前記下部電極を覆う容量絶縁膜および上部電極を形成する工程、
前記情報蓄積用容量素子上および前記周辺回路領域または前記ロジック回路領域上に表面が平坦化された第４絶縁膜を形成する工程、
を含み、
前記ストッパ膜は、前記情報蓄積用容量素子の前記下部電極を形成する際のエッチングストッパとして機能することを特徴とする半導体集積回路装置の製造方法。 Forming a memory cell selection MISFET in the memory cell array region on the main surface of the semiconductor substrate, and forming a peripheral circuit MISFET or a logic circuit MISFET in the peripheral circuit region or logic circuit region of the semiconductor substrate;
Step said memory cell selecting MISFET and the not covering the peripheral circuit MISFET or MISFET for the logic circuit, and having a surface forming a first insulating film is flattened,
Forming a bit line on the first insulating film in the memory cell array region and forming a first layer wiring made of the same material as the bit line on the first insulating film in the peripheral circuit region or the logic circuit region; ,
Forming a second insulating film covering the bit line and the first layer wiring and having a planarized surface on the memory cell array region and the peripheral circuit region or the logic circuit region;
Forming a stopper film on the second insulating film in the memory cell array region ;
Forming a third insulating film before kissing stopper film,
Forming a lower electrode of an information storage capacitor element, a capacitor insulating film covering the lower electrode, and an upper electrode on the third insulating film in the memory cell array region;
Step surface before Symbol information on storage capacitor and the peripheral circuit region or the logic circuit region to form a fourth insulating film having a flattened,
Including
Before kissing stopper film, a method of manufacturing a semiconductor integrated circuit device, characterized in that it functions as an etching stopper when forming the lower electrode of the information storage capacitor.
前記メモリセル選択用ＭＩＳＦＥＴおよび前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴを覆い、かつその表面が平坦化された第１絶縁膜が形成され、
前記メモリセルアレイ領域の前記第１絶縁膜上にビット線が、前記周辺回路領域または前記ロジック回路領域の前記第１絶縁膜上に前記ビット線と同一の材料からなる第１層配線が形成され、
前記ビット線および前記第１層配線を覆い、かつその表面が平坦化された第２絶縁膜が前記メモリセルアレイ領域および前記周辺回路領域または前記ロジック回路領域上に形成され、
ストッパ膜が前記メモリセルアレイ領域の前記第２絶縁膜の上部に形成され、
前記ストッパ膜上に絶縁膜が形成され、
前記メモリセルアレイ領域の前記絶縁膜に情報蓄積用容量素子の下部電極、前記下部電極を覆う容量絶縁膜および上部電極が形成され、
前記絶縁膜は前記情報蓄積用容量素子上および前記周辺回路領域または前記ロジック回路領域上に表面が平坦化されて形成され、
前記ストッパ膜は、前記情報蓄積用容量素子の前記下部電極を形成する際のエッチングストッパとして機能することを特徴とする半導体集積回路装置。 A memory cell selection MISFET is formed in the memory cell array region of the main surface of the semiconductor substrate, and a peripheral circuit MISFET or a logic circuit MISFET is formed in the peripheral circuit region or the logic circuit region of the semiconductor substrate, respectively.
The first insulating film for a memory cell selection MISFET and said not covering the peripheral circuit MISFET or MISFET for the logic circuit, and its surface is planarized is formed,
A bit line is formed on the first insulating film in the memory cell array region, and a first layer wiring made of the same material as the bit line is formed on the first insulating film in the peripheral circuit region or the logic circuit region,
A second insulating film covering the bit line and the first layer wiring and having a planarized surface is formed on the memory cell array region and the peripheral circuit region or the logic circuit region;
Scan stopper film is formed on the second insulating film of the memory cell array area,
Insulation film is formed before kissing stopper film,
The lower electrode of the information storage capacitor before Kize' edge film of the memory cell array region, wherein the capacitor insulating film covering the lower electrode and the upper electrode are formed,
Before Kize' Enmaku surface is formed is flattened to the information on the storage capacitor and the peripheral circuit region or the logic circuit region,
Before kissing stopper film, a semiconductor integrated circuit device, characterized in that it functions as an etching stopper when forming the lower electrode of the information storage capacitor.
前記メモリセル選択用ＭＩＳＦＥＴおよび前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴを覆い、かつその表面が平坦化された第１絶縁膜を形成する工程、
前記メモリセルアレイ領域の前記第１絶縁膜上にビット線を、前記周辺回路領域または前記ロジック回路領域の前記第１絶縁膜上に前記ビット線と同一の材料からなる第１層配線を形成する工程、
前記ビット線および前記第１層配線を覆い、かつその表面が平坦化された第２絶縁膜を前記メモリセルアレイ領域および前記周辺回路領域または前記ロジック回路領域上に形成する工程、
前記メモリセルアレイ領域の前記第２絶縁膜の上部にストッパ膜を形成する工程、
前記ストッパ膜上に第３絶縁膜を形成する工程、
前記メモリセルアレイ領域の前記第３絶縁膜および前記ストッパ膜をエッチングして溝を形成する工程、
前記溝の内壁および底部上に情報蓄積用容量素子の下部電極を形成する工程、
前記第３絶縁膜をエッチングして前記下部電極を露出させる工程、
前記下部電極を覆う容量絶縁膜および上部電極を形成する工程、
前記第３絶縁膜上、前記情報蓄積用容量素子上および前記周辺回路領域または前記ロジック回路領域上に表面が平坦化された第４絶縁膜を形成する工程、
を含み、
前記第３絶縁膜をエッチングして下部電極を露出させるとき、前記ストッパ膜は、エッチングストッパとして機能し、前記下部電極の下には前記ストッパ膜が存在せず、前記下部電極の側壁に接する領域に前記ストッパ膜が存在することを特徴とする半導体集積回路装置の製造方法。 Forming a memory cell selection MISFET in the memory cell array region on the main surface of the semiconductor substrate, and forming a peripheral circuit MISFET or a logic circuit MISFET in the peripheral circuit region or logic circuit region of the semiconductor substrate;
Step said memory cell selecting MISFET and the not covering the peripheral circuit MISFET or MISFET for the logic circuit, and having a surface forming a first insulating film is flattened,
Forming a bit line on the first insulating film in the memory cell array region and forming a first layer wiring made of the same material as the bit line on the first insulating film in the peripheral circuit region or the logic circuit region; ,
Forming a second insulating film covering the bit line and the first layer wiring and having a planarized surface on the memory cell array region and the peripheral circuit region or the logic circuit region;
Forming a stopper film on the second insulating film in the memory cell array region ;
Forming a third insulating film before kissing stopper film,
Forming a trench by etching the third insulating film and before kiss stopper film of the memory cell array area,
Forming a lower electrode of the information storage capacitor before Kimizo inner wall and bottom on,
Exposing the pre-Symbol lower electrode by etching the third insulating film,
Forming a capacitive insulating film and an upper electrode covering the lower electrode;
Forming a fourth insulating film having a planarized surface on the third insulating film, on the information storage capacitive element, and on the peripheral circuit region or the logic circuit region;
Including
When exposing the lower electrode by etching the third insulating film, said stopper film functions as or falling edge of quenching stopper, is below the lower electrode does not exist the stopper film, region in contact with the sidewall of the lower electrode A method of manufacturing a semiconductor integrated circuit device , wherein the stopper film is present on the substrate .
前記第４絶縁膜の表面を研磨法で平坦化した後、前記周辺回路領域または前記ロジック回路領域の前記平坦化された前記第４絶縁膜および前記第２絶縁膜に溝を前記第１層配線を露出するように形成し、前記溝の内部を含む前記第４絶縁膜上に導電層を堆積し、前記第４絶縁膜の表面上の前記導電層を除去して、前記溝内に前記導電層からなる導電部を、前記第１層配線に接続するように形成する工程、
を更に含むことを特徴とする半導体集積回路装置の製造方法。 According to claim 3,
After flattening polishing method of the surface of the fourth insulating film, the peripheral circuit region or the first layer of the planarized fourth insulating film Contact and groove on the second insulating film in the logic circuit region It formed so as to expose the wiring, before depositing the conductive layer on the fourth insulating film including the inside of Kimizo, and divided the previous Kishirube conductive layer on the surface of the fourth insulating film, before a conductive portion made of pre Kishirube conductive layer in Kimizo, forming so as to be connected to the first layer wiring,
A method for manufacturing a semiconductor integrated circuit device, further comprising:
前記メモリセル選択用ＭＩＳＦＥＴおよび前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴを覆い、かつその表面が平坦化された第１絶縁膜が形成され、
前記メモリセルアレイ領域の前記第１絶縁膜上にビット線が、前記周辺回路領域または前記ロジック回路領域の前記第１絶縁膜上に前記ビット線と同一の材料からなる第１層配線が形成され、
前記ビット線および前記第１層配線を覆い、かつその表面が平坦化された第２絶縁膜が前記メモリセルアレイ領域および前記周辺回路領域または前記ロジック回路領域上に形成され、
ストッパ膜が前記メモリセルアレイ領域の前記第２絶縁膜の上部に形成され、
前記ストッパ膜上に絶縁膜が形成され、
前記絶縁膜に情報蓄積用容量素子の下部電極、前記下部電極を覆う容量絶縁膜および上部電極が形成され、
前記絶縁膜は、前記情報蓄積用容量素子上および前記周辺回路領域または前記ロジック回路領域上に表面が平坦化されて形成され、
前記周辺回路領域または前記ロジック回路領域の前記絶縁膜および前記第２絶縁膜に溝が前記第１層配線を露出するように形成され、
前記溝内に導電層からなる導電部が、前記第１層配線に接続するように形成され、
前記ストッパ膜は、前記下部電極を形成する際のエッチングストッパとして機能し、
前記下部電極は内面及び外面を有する側壁を有し、
前記下部電極の下には前記ストッパ膜が存在せず、前記下部電極の側壁に接する領域に前記ストッパ膜が存在し、
前記下部電極の側壁の内面及び外面上に容量絶縁膜、前記容量絶縁膜上に前記上部電極が形成されていることを特徴とする半導体集積回路装置。 A memory cell selection MISFET is formed in the memory cell array region of the main surface of the semiconductor substrate, and a peripheral circuit MISFET or a logic circuit MISFET is formed in the peripheral circuit region or the logic circuit region of the semiconductor substrate, respectively.
The first insulating film for a memory cell selection MISFET and said not covering the peripheral circuit MISFET or MISFET for the logic circuit, and its surface is planarized is formed,
A bit line is formed on the first insulating film in the memory cell array region, and a first layer wiring made of the same material as the bit line is formed on the first insulating film in the peripheral circuit region or the logic circuit region,
A second insulating film covering the bit line and the first layer wiring and having a planarized surface is formed on the memory cell array region and the peripheral circuit region or the logic circuit region;
Scan stopper film is formed on the second insulating film of the memory cell array area,
Insulation film is formed before kissing stopper film,
The lower electrode of the information storage capacitor in the insulating film, the capacitor insulating film covering the lower electrode and the upper electrode are formed,
The insulating film is formed by planarizing the surface on the information storage capacitor element and the peripheral circuit region or the logic circuit region,
A groove is formed in the peripheral circuit region or the logic circuit region in the insulating film and the second insulating film so as to expose the first layer wiring;
Conductive portion made of a conductive layer in said groove is formed so as to be connected to the first layer wiring,
Before kissing stopper film functions as an etching stopper in forming the pre-Symbol lower electrode,
The lower electrode has a sidewall having an inner surface and an outer surface,
The stopper film does not exist under the lower electrode, and the stopper film exists in a region in contact with the side wall of the lower electrode,
A semiconductor integrated circuit device , wherein a capacitor insulating film is formed on an inner surface and an outer surface of a side wall of the lower electrode, and the upper electrode is formed on the capacitor insulating film .
前記メモリセル選択用ＭＩＳＦＥＴおよび前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴを覆い、かつその表面が平坦化された第１絶縁膜を形成する工程、Forming a first insulating film covering the memory cell selecting MISFET and the peripheral circuit MISFET or the logic circuit MISFET and having a planarized surface;
前記メモリセルアレイ領域の前記第１絶縁膜上にビット線を、前記周辺回路領域または前記ロジック回路領域の前記第１絶縁膜上に前記ビット線と同一の材料からなる第１層配線を形成する工程、Forming a bit line on the first insulating film in the memory cell array region and forming a first layer wiring made of the same material as the bit line on the first insulating film in the peripheral circuit region or the logic circuit region; ,
前記ビット線および前記第１層配線を覆い、かつその表面が平坦化された第２絶縁膜を前記メモリセルアレイ領域および前記周辺回路領域または前記ロジック回路領域上に形成する工程、Forming a second insulating film covering the bit line and the first layer wiring and having a planarized surface on the memory cell array region and the peripheral circuit region or the logic circuit region;
前記メモリセルアレイ領域の前記第２絶縁膜の上部にストッパ膜を形成する工程、Forming a stopper film on the second insulating film in the memory cell array region;
前記ストッパ膜上に第３絶縁膜を形成する工程、Forming a third insulating film on the stopper film;
前記メモリセルアレイ領域の前記第３絶縁膜および前記ストッパ膜をエッチングして溝を形成する工程、Etching the third insulating film and the stopper film in the memory cell array region to form a groove;
前記溝の内壁および底部上に情報蓄積用容量素子の下部電極を形成する工程、Forming a lower electrode of an information storage capacitive element on the inner wall and bottom of the groove;
前記第３絶縁膜をエッチングして前記下部電極を露出させる工程、Etching the third insulating film to expose the lower electrode;
前記下部電極を覆う容量絶縁膜および上部電極を形成する工程、Forming a capacitive insulating film and an upper electrode covering the lower electrode;
前記第３絶縁膜上、前記情報蓄積用容量素子上および前記周辺回路領域または前記ロジック回路領域上に表面が平坦化された第４絶縁膜を形成する工程、Forming a fourth insulating film having a planarized surface on the third insulating film, on the information storage capacitive element, and on the peripheral circuit region or the logic circuit region;
を含み、Including
前記第３絶縁膜をエッチングして下部電極を露出させるとき、前記ストッパ膜は、エッチングストッパとして機能し、前記下部電極の下には前記ストッパ膜が存在せず、前記下部電極の側壁に接する領域に前記ストッパ膜が存在し、When the lower electrode is exposed by etching the third insulating film, the stopper film functions as an etching stopper, and the stopper film does not exist under the lower electrode and is in contact with the side wall of the lower electrode The stopper film exists in
前記第１絶縁膜に前記メモリセル選択用ＭＩＳＦＥＴの半導体領域に接続されるシリコン膜からなる第１プラグが形成され、A first plug made of a silicon film connected to the semiconductor region of the memory cell selection MISFET is formed in the first insulating film;
前記第１絶縁膜に前記第１プラグが露出する開口が形成され、前記ビット線は、前記開口を介して前記第１プラグに接続され、An opening through which the first plug is exposed is formed in the first insulating film, and the bit line is connected to the first plug through the opening,
前記第１絶縁膜に、前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴの半導体領域を露出する第１接続孔が形成され、前記第１層配線は前記第１接続孔内に形成された金属膜に接続されることを特徴とする半導体集積回路装置の製造方法。A first connection hole that exposes a semiconductor region of the peripheral circuit MISFET or the logic circuit MISFET is formed in the first insulating film, and the first layer wiring is a metal film formed in the first connection hole A method for manufacturing a semiconductor integrated circuit device, comprising:
前記第４絶縁膜の表面を研磨法で平坦化した後、前記周辺回路領域または前記ロジック回路領域の前記平坦化された前記第４絶縁膜および前記第２絶縁膜に溝を前記第１層配線を露出するように形成し、前記溝の内部を含む前記第４絶縁膜上に導電層を堆積し、前記第４絶縁膜の表面上の前記導電層を除去して、前記溝内に前記導電層からなる導電部を、前記第１層配線に接続するように形成する工程、After planarizing the surface of the fourth insulating film by a polishing method, a trench is formed in the flattened fourth insulating film and the second insulating film in the peripheral circuit region or the logic circuit region. The conductive layer is deposited on the fourth insulating film including the inside of the groove, the conductive layer on the surface of the fourth insulating film is removed, and the conductive film is formed in the groove. Forming a conductive portion made of a layer so as to be connected to the first layer wiring;
を更に含むことを特徴とする半導体集積回路装置の製造方法。A method for manufacturing a semiconductor integrated circuit device, further comprising:
前記メモリセル選択用ＭＩＳＦＥＴおよび前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴを覆い、かつその表面が平坦化された第１絶縁膜が形成され、Forming a first insulating film covering the memory cell selection MISFET and the peripheral circuit MISFET or the logic circuit MISFET and having a flattened surface;
前記メモリセルアレイ領域の前記第１絶縁膜上にビット線が、前記周辺回路領域または前記ロジック回路領域の前記第１絶縁膜上に前記ビット線と同一の材料からなる第１層配線が形成され、A bit line is formed on the first insulating film in the memory cell array region, and a first layer wiring made of the same material as the bit line is formed on the first insulating film in the peripheral circuit region or the logic circuit region,
前記ビット線および前記第１層配線を覆い、かつその表面が平坦化された第２絶縁膜が前記メモリセルアレイ領域および前記周辺回路領域または前記ロジック回路領域上に形成され、A second insulating film covering the bit line and the first layer wiring and having a planarized surface is formed on the memory cell array region and the peripheral circuit region or the logic circuit region;
ストッパ膜が前記メモリセルアレイ領域の前記第２絶縁膜の上部に形成され、A stopper film is formed on the second insulating film in the memory cell array region,
前記ストッパ膜上に絶縁膜が形成され、An insulating film is formed on the stopper film;
前記絶縁膜に情報蓄積用容量素子の下部電極、前記下部電極を覆う容量絶縁膜および上部電極が形成され、A lower electrode of an information storage capacitive element, a capacitive insulating film and an upper electrode covering the lower electrode are formed on the insulating film,
前記絶縁膜は、前記情報蓄積用容量素子上および前記周辺回路領域または前記ロジック回路領域上に表面が平坦化されて形成され、The insulating film is formed by planarizing the surface on the information storage capacitor element and the peripheral circuit region or the logic circuit region,
前記周辺回路領域または前記ロジック回路領域の前記絶縁膜および前記第２絶縁膜に溝が前記第１層配線を露出するように形成され、A groove is formed in the peripheral circuit region or the logic circuit region in the insulating film and the second insulating film so as to expose the first layer wiring;
前記溝内に導電層からなる導電部が、前記第１層配線に接続するように形成され、A conductive portion made of a conductive layer is formed in the groove so as to be connected to the first layer wiring,
前記ストッパ膜は前記下部電極を形成する際のエッチングストッパとして機能し、The stopper film functions as an etching stopper when forming the lower electrode,
前記下部電極は内面及び外面を有する側壁を有し、The lower electrode has a sidewall having an inner surface and an outer surface,
前記下部電極の下には前記ストッパ膜が存在せず、前記下部電極の側壁に接する領域に前記ストッパ膜が存在し、The stopper film does not exist under the lower electrode, and the stopper film exists in a region in contact with the side wall of the lower electrode,
前記下部電極の側壁の内面及び外面上に容量絶縁膜、前記容量絶縁膜上に前記上部電極が形成され、A capacitor insulating film is formed on the inner and outer surfaces of the side wall of the lower electrode, and the upper electrode is formed on the capacitor insulating film,
前記第１絶縁膜に前記メモリセル選択用ＭＩＳＦＥＴの半導体領域に接続されるシリコン膜からなる第１プラグが形成され、A first plug made of a silicon film connected to the semiconductor region of the memory cell selection MISFET is formed in the first insulating film;
前記第１絶縁膜に前記第１プラグが露出する開口が形成され、前記ビット線は、前記開口を介して前記第１プラグに接続され、An opening through which the first plug is exposed is formed in the first insulating film, and the bit line is connected to the first plug through the opening,
前記第１絶縁膜に、前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴの半導体領域を露出する第１接続孔が形成され、前記第１層配線は前記第１接続孔内に形成された金属膜に接続されることを特徴とする半導体集積回路装置。A first connection hole that exposes a semiconductor region of the peripheral circuit MISFET or the logic circuit MISFET is formed in the first insulating film, and the first layer wiring is a metal film formed in the first connection hole A semiconductor integrated circuit device connected to the semiconductor integrated circuit device.
前記メモリセル選択用ＭＩＳＦＥＴおよび前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴを覆い、かつその表面が平坦化された第１絶縁膜を形成する工程、
前記メモリセルアレイ領域の前記第１絶縁膜上にビット線を、前記周辺回路領域または前記ロジック回路領域の前記第１絶縁膜上に前記ビット線と同一の材料からなる第１層配線を形成する工程、
前記ビット線および前記第１層配線を覆い、かつその表面が平坦化された第２絶縁膜を前記メモリセルアレイ領域および前記周辺回路領域または前記ロジック回路領域上に形成する工程、
ストッパ膜を前記メモリセルアレイ領域の前記第２絶縁膜の上部に形成する工程、
前記ストッパ膜上に第３絶縁膜を形成する工程、
前記メモリセルアレイ領域の前記第３絶縁膜および前記ストッパ膜をエッチングして溝を形成する工程、
前記溝の内壁および底部上に情報蓄積用容量素子の下部電極を形成する工程、
前記ストッパ膜をエッチングストッパとして前記第３絶縁膜をエッチングして前記下部電極を露出させる工程、
前記下部電極を覆う容量絶縁膜および上部電極を形成する工程、
前記情報蓄積用容量素子上および前記周辺回路領域または前記ロジック回路領域上に、表面が平坦化された第４絶縁膜を形成する工程、
前記周辺回路領域または前記ロジック回路領域の前記平坦化された前記第４絶縁膜および前記第２絶縁膜に他の溝を前記第１層配線を露出するように形成し、前記他の溝の内部を含む前記第４絶縁膜上に導電層を堆積し、前記第４絶縁膜の表面上の前記導電層を除去して、前記他の溝内に前記導電層からなる導電部を、前記第１層配線に接続するように形成する工程、
を含み、
前記下部電極の下には前記ストッパ膜が存在せず、前記下部電極の側壁に接する領域に前記ストッパ膜が存在することを特徴とする半導体集積回路装置の製造方法。 Forming a memory cell selection MISFET in the memory cell array region on the main surface of the semiconductor substrate, and forming a peripheral circuit MISFET or a logic circuit MISFET in the peripheral circuit region or logic circuit region of the semiconductor substrate;
Step said memory cell selecting MISFET and the not covering the peripheral circuit MISFET or MISFET for the logic circuit, and having a surface forming a first insulating film is flattened,
Forming a bit line on the first insulating film in the memory cell array region and forming a first layer wiring made of the same material as the bit line on the first insulating film in the peripheral circuit region or the logic circuit region; ,
Forming a second insulating film covering the bit line and the first layer wiring and having a planarized surface on the memory cell array region and the peripheral circuit region or the logic circuit region;
Forming a scan stopper film on the second insulating film of the memory cell array area,
Forming a third insulating film before kissing stopper film,
Forming a trench by etching the third insulating film and before kiss stopper film of the memory cell array area,
Forming a lower electrode of an information storage capacitive element on the inner wall and bottom of the groove ;
Exposing the pre-Symbol lower electrode by etching the third insulating film using the stopper film as an etching stopper,
Forming a capacitive insulating film and an upper electrode covering the lower electrode;
Before SL information on storage capacitor and the peripheral circuit region or the logic circuit region, forming a fourth insulating film having a planarized surface,
Another groove is formed in the planarized fourth insulating film and second insulating film in the peripheral circuit region or the logic circuit region so as to expose the first layer wiring, and the inside of the other groove A conductive layer is deposited on the fourth insulating film containing the conductive layer, the conductive layer on the surface of the fourth insulating film is removed, and a conductive portion made of the conductive layer is formed in the other groove. Forming to connect to the layer wiring;
Including
A method of manufacturing a semiconductor integrated circuit device , wherein the stopper film does not exist under the lower electrode, and the stopper film exists in a region in contact with a side wall of the lower electrode .
前記メモリセル選択用ＭＩＳＦＥＴおよび前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴを覆い、かつその表面が平坦化された第１絶縁膜が形成され、
前記メモリセルアレイ領域の前記第１絶縁膜上にビット線が、前記周辺回路領域または前記ロジック回路領域の前記第１絶縁膜上に前記ビット線と同一の材料からなる第１層配線が形成され、
前記ビット線および前記第１層配線を覆い、かつその表面が平坦化された第２絶縁膜が前記メモリセルアレイ領域および前記周辺回路領域または前記ロジック回路領域上に形成され、
ストッパ膜が前記メモリセルアレイ領域の前記第２絶縁膜の上部に形成され、
前記ストッパ膜上に絶縁膜が形成され、
前記絶縁膜に情報蓄積用容量素子の下部電極、前記下部電極を覆う容量絶縁膜および上部電極が形成され、
前記絶縁膜は前記情報蓄積用容量素子上および前記周辺回路領域または前記ロジック回路領域上に表面が平坦化されて形成され、
前記下部電極の下には前記ストッパ膜が存在せず、前記下部電極の側壁に接する領域に前記ストッパ膜が存在し、前記ストッパ膜は、前記下部電極を形成する際のエッチングストッパとして機能することを特徴とする半導体集積回路装置。 A memory cell selection MISFET is formed in the memory cell array region of the main surface of the semiconductor substrate, and a peripheral circuit MISFET or a logic circuit MISFET is formed in the peripheral circuit region or the logic circuit region of the semiconductor substrate, respectively.
The first insulating film for a memory cell selection MISFET and said not covering the peripheral circuit MISFET or MISFET for the logic circuit, and its surface is planarized is formed,
A bit line is formed on the first insulating film in the memory cell array region, and a first layer wiring made of the same material as the bit line is formed on the first insulating film in the peripheral circuit region or the logic circuit region,
A second insulating film covering the bit line and the first layer wiring and having a planarized surface is formed on the memory cell array region and the peripheral circuit region or the logic circuit region;
Scan stopper film is formed on the second insulating film of the memory cell array area,
Insulation film is formed before kissing stopper film,
The lower electrode of the information storage capacitor in the insulating film, the capacitor insulating film covering the lower electrode and the upper electrode are formed,
Before Kize' Enmaku surface is formed is flattened to the information on the storage capacitor and the peripheral circuit region or the logic circuit region,
Wherein there is no kiss stopper film before below the lower electrode, there is pre-kiss stopper film in the region against the sidewall of the lower electrode, before kissing stopper film, when forming the lower electrode A semiconductor integrated circuit device that functions as an etching stopper.
前記メモリセル選択用ＭＩＳＦＥＴおよび前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴを覆い、かつその表面が平坦化された第１絶縁膜を形成する工程、
前記メモリセルアレイ領域の前記第１絶縁膜上にビット線を、前記周辺回路領域または前記ロジック回路領域の前記第１絶縁膜上に前記ビット線と同一の材料からなる第１層配線を形成する工程、
前記ビット線および前記第１層配線を覆い、かつその表面が平坦化された第２絶縁膜を前記メモリセルアレイ領域および前記周辺回路領域または前記ロジック回路領域上に形成する工程、
前記第２絶縁膜に接続孔を形成し、前記接続孔にプラグを形成する工程、
ストッパ膜を前記第２絶縁膜および前記プラグ上を含む前記メモリセルアレイ領域の上部に形成する工程、
前記ストッパ膜上に第３絶縁膜を形成する工程、
前記メモリセルアレイ領域の前記第３絶縁膜および前記ストッパ膜をエッチングして前記プラグを露出する溝を形成する工程、
前記溝の内壁および底部上に情報蓄積用容量素子の下部電極を形成する工程、
前記ストッパ膜をエッチングストッパとして前記第３絶縁膜をエッチングして前記下部電極を露出させる工程、
前記下部電極を覆う容量絶縁膜および上部電極を形成する工程、
前記情報蓄積用容量素子上および前記周辺回路領域または前記ロジック回路領域上に第４絶縁膜を形成する工程、
前記第４絶縁膜の表面を研磨法で平坦化した後、前記周辺回路領域または前記ロジック回路領域の前記平坦化された前記第４絶縁膜および前記第２絶縁膜に他の溝を前記第１層配線を露出するように形成し、前記他の溝の内部を含む前記第４絶縁膜上に導電層を堆積し、前記第４絶縁膜の表面上の前記導電層を除去して、前記他の溝内に前記導電層からなる導電部を、前記第１層配線に接続するように形成する工程、
を含み、
前記下部電極の下には前記ストッパ膜が存在せず、前記下部電極の側壁に接する領域に前記ストッパ膜が存在することを特徴とする半導体集積回路装置の製造方法。 Forming a memory cell selection MISFET in the memory cell array region on the main surface of the semiconductor substrate, and forming a peripheral circuit MISFET or a logic circuit MISFET in the peripheral circuit region or logic circuit region of the semiconductor substrate;
Step said memory cell selecting MISFET and the not covering the peripheral circuit MISFET or MISFET for the logic circuit, and having a surface forming a first insulating film is flattened,
Forming a bit line on the first insulating film in the memory cell array region and forming a first layer wiring made of the same material as the bit line on the first insulating film in the peripheral circuit region or the logic circuit region; ,
Forming a second insulating film covering the bit line and the first layer wiring and having a planarized surface on the memory cell array region and the peripheral circuit region or the logic circuit region;
Forming a connection hole in the second insulating film, and forming a plug in the connection hole;
Forming a scan stopper film on the memory cell array area including the second insulating film and the upper plug,
Forming a third insulating film before kissing stopper film,
Etching the third insulating film and the stopper film in the memory cell array region to form a groove exposing the plug;
Forming a lower electrode of an information storage capacitive element on the inner wall and bottom of the groove;
Etching the third insulating film using the stopper film as an etching stopper to expose the lower electrode;
Forming a capacitive insulating film and an upper electrode covering the lower electrode;
Forming a fourth insulating film before Symbol information on storage capacitor and the peripheral circuit region or the logic circuit region,
After flattening polishing method of the surface of the fourth insulating film, the said peripheral circuit region or the planarized fourth insulating film Contact and said another trench in the second insulating film in the logic circuit region first formed to expose the first layer wiring, the other to sedimentary a conductive layer on the fourth insulating film including the inside of the groove, dividing the front Kishirube conductive layer on the surface of the fourth insulating film and removed by forming a conductive portion made of pre Kishirube conductive layer on the other groove, so as to be connected to the first layer wiring,
Including
A method of manufacturing a semiconductor integrated circuit device , wherein the stopper film does not exist under the lower electrode, and the stopper film exists in a region in contact with a side wall of the lower electrode .
前記メモリセル選択用ＭＩＳＦＥＴおよび前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴを覆い、かつその表面が平坦化された第１絶縁膜が形成され、
前記メモリセルアレイ領域の前記第１絶縁膜上にビット線が、前記周辺回路領域または前記ロジック回路領域の前記第１絶縁膜上に前記ビット線と同一の材料からなる第１層配線が形成され、
前記ビット線および前記第１層配線を覆い、かつその表面が平坦化された第２絶縁膜が前記メモリセルアレイ領域および前記周辺回路領域または前記ロジック回路領域上に形成され、
前記第２絶縁膜に接続孔が形成され、前記接続孔にプラグが形成され、
ストッパ膜が前記第２絶縁膜および前記プラグ上を含む前記メモリセルアレイの上部に形成され、
前記ストッパ膜上に絶縁膜が形成され、
前記絶縁膜に情報蓄積用容量素子の下部電極、前記下部電極を覆う容量絶縁膜および上部電極が形成され、
前記絶縁膜は、前記情報蓄積用容量素子上および前記周辺回路領域または前記ロジック回路領域上に表面が平坦化されて形成され、
前記周辺回路領域または前記ロジック回路領域の前記絶縁膜および前記第２絶縁膜に溝が前記第１層配線を露出するように形成され、
前記溝内に導電層からなる導電部が、前記第１層配線に接続するように形成され、
前記ストッパ膜は、前記下部電極を形成する際のエッチングストッパとして機能し、
前記下部電極は内面及び外面を有する側壁を有し、
前記下部電極の下には前記ストッパ膜が除去されて前記プラグに接続し、かつ前記下部電極の側壁に接する領域に前記ストッパ膜が存在し、
前記下部電極の側壁の内面及び外面上に前記容量絶縁膜、前記容量絶縁膜上に前記上部電極が形成されていることを特徴とする半導体集積回路装置。 A memory cell selection MISFET is formed in the memory cell array region of the main surface of the semiconductor substrate, and a peripheral circuit MISFET or a logic circuit MISFET is formed in the peripheral circuit region or the logic circuit region of the semiconductor substrate, respectively.
Forming a first insulating film covering the memory cell selection MISFET and the peripheral circuit MISFET or the logic circuit MISFET and having a flattened surface;
A bit line is formed on the first insulating film in the memory cell array region, and a first layer wiring made of the same material as the bit line is formed on the first insulating film in the peripheral circuit region or the logic circuit region,
A second insulating film covering the bit line and the first layer wiring and having a planarized surface is formed on the memory cell array region and the peripheral circuit region or the logic circuit region;
A connection hole is formed in the second insulating film, and a plug is formed in the connection hole;
A stopper film is formed on the memory cell array including the second insulating film and the plug,
An insulating film is formed on the stopper film;
A lower electrode of an information storage capacitive element, a capacitive insulating film and an upper electrode covering the lower electrode are formed on the insulating film,
The insulating film is formed by planarizing the surface on the information storage capacitor element and the peripheral circuit region or the logic circuit region,
A groove is formed in the peripheral circuit region or the logic circuit region in the insulating film and the second insulating film so as to expose the first layer wiring;
A conductive portion made of a conductive layer is formed in the groove so as to be connected to the first layer wiring,
The stopper film functions as an etching stopper when forming the lower electrode,
The lower electrode has a sidewall having an inner surface and an outer surface,
Under the lower electrode, the stopper film is removed and connected to the plug, and the stopper film is present in a region in contact with the side wall of the lower electrode,
A semiconductor integrated circuit device , wherein the capacitive insulating film is formed on an inner surface and an outer surface of a side wall of the lower electrode, and the upper electrode is formed on the capacitive insulating film .
前記メモリセル選択用ＭＩＳＦＥＴおよび前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴを覆い、かつその表面が研磨法により平坦化された第１絶縁膜を形成する工程、Forming a first insulating film that covers the memory cell selecting MISFET and the peripheral circuit MISFET or the logic circuit MISFET and whose surface is planarized by a polishing method;
前記メモリセルアレイ領域の前記第１絶縁膜上にビット線を、前記周辺回路領域または前記ロジック回路領域の前記第１絶縁膜上に前記ビット線と同一の材料からなる第１層配線を形成する工程、Forming a bit line on the first insulating film in the memory cell array region and forming a first layer wiring made of the same material as the bit line on the first insulating film in the peripheral circuit region or the logic circuit region; ,
前記ビット線および前記第１層配線を覆い、かつその表面が研磨法により平坦化された第２絶縁膜を前記メモリセルアレイ領域および前記周辺回路領域または前記ロジック回路領域上に形成する工程、Forming a second insulating film on the memory cell array region and the peripheral circuit region or the logic circuit region, covering the bit line and the first layer wiring and having a surface planarized by a polishing method;
前記第２絶縁膜に第２接続孔を形成し、前記第２接続孔に第２プラグを形成する工程、Forming a second connection hole in the second insulating film and forming a second plug in the second connection hole;
ストッパ膜を前記第２絶縁膜および前記第２プラグ上を含む前記メモリセルアレイ領域の上部に形成する工程、Forming a stopper film on the memory cell array region including the second insulating film and the second plug;
前記ストッパ膜上に第３絶縁膜を形成する工程、Forming a third insulating film on the stopper film;
前記メモリセルアレイ領域の前記第３絶縁膜および前記ストッパ膜をエッチングして前記第２プラグを露出する溝を形成する工程、Etching the third insulating film and the stopper film in the memory cell array region to form a groove exposing the second plug;
前記溝の内壁および底部上に情報蓄積用容量素子の下部電極を形成する工程、Forming a lower electrode of an information storage capacitive element on the inner wall and bottom of the groove;
前記ストッパ膜をエッチングストッパとして前記第３絶縁膜をエッチングして前記下部電極を露出させる工程、Etching the third insulating film using the stopper film as an etching stopper to expose the lower electrode;
前記下部電極を覆う容量絶縁膜および上部電極を形成する工程、Forming a capacitive insulating film and an upper electrode covering the lower electrode;
前記情報蓄積用容量素子上および前記周辺回路領域または前記ロジック回路領域上に第４絶縁膜を形成する工程、Forming a fourth insulating film on the information storage capacitive element and on the peripheral circuit region or the logic circuit region;
前記第４絶縁膜の表面を研磨法で平坦化した後、前記周辺回路領域または前記ロジック回路領域の前記平坦化された前記第４絶縁膜および前記第２絶縁膜に他の溝を前記第１層配線を露出するように形成し、前記他の溝の内部を含む前記第４絶縁膜上に導電層を堆積し、前記第４絶縁膜の表面上の前記導電層を除去して、前記他の溝内に前記導電層からなる導電部を、前記第１層配線に接続するように形成する工程、After planarizing the surface of the fourth insulating film by a polishing method, another groove is formed in the flattened fourth insulating film and second insulating film in the peripheral circuit region or the logic circuit region. Forming a layer wiring to be exposed, depositing a conductive layer on the fourth insulating film including the inside of the other groove, removing the conductive layer on the surface of the fourth insulating film, and Forming a conductive portion made of the conductive layer in the groove so as to be connected to the first layer wiring;
を含み、Including
前記下部電極の下には前記ストッパ膜が存在せず、前記下部電極の側壁に接する領域に前記ストッパ膜が存在し、The stopper film does not exist under the lower electrode, and the stopper film exists in a region in contact with the side wall of the lower electrode,
前記第１絶縁膜に前記メモリセル選択用ＭＩＳＦＥＴの一方の半導体領域に接続されるシリコン膜からなる第１プラグが形成され、A first plug made of a silicon film connected to one semiconductor region of the memory cell selection MISFET is formed in the first insulating film,
前記第１絶縁膜に前記第１プラグが露出する開口が形成され、前記ビット線は、前記開口を介して前記第１プラグに接続され、An opening through which the first plug is exposed is formed in the first insulating film, and the bit line is connected to the first plug through the opening,
前記第１絶縁膜に前記メモリセル選択用ＭＩＳＦＥＴの他方の半導体領域に接続されるシリコン膜からなる第３プラグが形成され、A third plug made of a silicon film connected to the other semiconductor region of the memory cell selecting MISFET is formed in the first insulating film;
前記第３プラグは前記第２プラグに接続され、The third plug is connected to the second plug;
前記第１絶縁膜に、前記周辺回路用ＭＩＳＦＥＴまたはロジック回路用ＭＩＳＦＥＴの半導体領域を露出する第１接続孔が形成され、前記第１層配線は前記第１接続孔内に形成された金属膜に接続されることを特徴とする半導体集積回路装置の製造方法。A first connection hole exposing the semiconductor region of the peripheral circuit MISFET or the logic circuit MISFET is formed in the first insulating film, and the first layer wiring is formed in a metal film formed in the first connection hole. A method of manufacturing a semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is connected.
前記ストッパ膜は窒化シリコン膜であることを特徴とする半導体集積回路装置の製造方法。The method of manufacturing a semiconductor integrated circuit device, wherein the stopper film is a silicon nitride film.
前記メモリセル選択用ＭＩＳＦＥＴおよび前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴを覆い、かつその表面が研磨法により平坦化された第１絶縁膜が形成され、Forming a first insulating film that covers the memory cell selection MISFET and the peripheral circuit MISFET or the logic circuit MISFET and whose surface is planarized by a polishing method;
前記メモリセルアレイ領域の前記第１絶縁膜上にビット線が、前記周辺回路領域または前記ロジック回路領域の前記第１絶縁膜上に前記ビット線と同一の材料からなる第１層配線が形成され、A bit line is formed on the first insulating film in the memory cell array region, and a first layer wiring made of the same material as the bit line is formed on the first insulating film in the peripheral circuit region or the logic circuit region,
前記ビット線および前記第１層配線を覆い、かつその表面が研磨法により平坦化された第２絶縁膜が前記メモリセルアレイ領域および前記周辺回路領域または前記ロジック回路領域上に形成され、A second insulating film that covers the bit line and the first layer wiring and whose surface is planarized by a polishing method is formed on the memory cell array region and the peripheral circuit region or the logic circuit region,
前記第２絶縁膜に第２接続孔が形成され、前記第２接続孔に第２プラグが形成され、A second connection hole is formed in the second insulating film, and a second plug is formed in the second connection hole;
ストッパ膜が前記第２絶縁膜および前記第２プラグ上を含む前記メモリセルアレイの上部に形成され、A stopper film is formed on the memory cell array including the second insulating film and the second plug,
前記ストッパ膜上に絶縁膜が形成され、An insulating film is formed on the stopper film;
前記絶縁膜に情報蓄積用容量素子の下部電極、前記下部電極を覆う容量絶縁膜および上部電極が形成され、A lower electrode of an information storage capacitive element, a capacitive insulating film and an upper electrode covering the lower electrode are formed on the insulating film,
前記絶縁膜は、前記情報蓄積用容量素子上および前記周辺回路領域または前記ロジック回路領域上に表面が研磨法により平坦化されて形成され、The insulating film is formed by polishing the surface on the information storage capacitor element and the peripheral circuit area or the logic circuit area by a polishing method,
前記周辺回路領域または前記ロジック回路領域の前記絶縁膜および前記第２絶縁膜に溝が前記第１層配線を露出するように形成され、A groove is formed in the peripheral circuit region or the logic circuit region in the insulating film and the second insulating film so as to expose the first layer wiring;
前記溝内に導電層からなる導電部が、前記第１層配線に接続するように形成され、A conductive portion made of a conductive layer is formed in the groove so as to be connected to the first layer wiring,
前記ストッパ膜は、前記下部電極を形成する際のエッチングストッパとして機能し、The stopper film functions as an etching stopper when forming the lower electrode,
前記下部電極は内面及び外面を有する側壁を有し、The lower electrode has a sidewall having an inner surface and an outer surface,
前記下部電極の下には前記ストッパ膜が除去されて前記第２プラグに接続し、かつ前記下部電極の側壁に接する領域に前記ストッパ膜が存在し、Under the lower electrode, the stopper film is removed and connected to the second plug, and the stopper film is present in a region in contact with the side wall of the lower electrode,
前記下部電極の側壁の内面及び外面上に前記容量絶縁膜、前記容量絶縁膜上に前記上部電極が形成され、The capacitive insulating film is formed on the inner and outer surfaces of the side wall of the lower electrode, and the upper electrode is formed on the capacitive insulating film,
前記第１絶縁膜に前記メモリセル選択用ＭＩＳＦＥＴの一方の半導体領域に接続されるシリコン膜からなる第１プラグが形成され、A first plug made of a silicon film connected to one semiconductor region of the memory cell selection MISFET is formed in the first insulating film,
前記第１絶縁膜に前記第１プラグが露出する開口が形成され、前記ビット線は、前記開口を介して前記第１プラグに接続され、An opening through which the first plug is exposed is formed in the first insulating film, and the bit line is connected to the first plug through the opening,
前記第１絶縁膜に前記メモリセル選択用ＭＩＳＦＥＴの他方の半導体領域に接続されるシリコン膜からなる第３プラグが形成され、A third plug made of a silicon film connected to the other semiconductor region of the memory cell selecting MISFET is formed in the first insulating film;
前記第３プラグは前記第２プラグに接続され、The third plug is connected to the second plug;
前記第１絶縁膜に、前記周辺回路用ＭＩＳＦＥＴまたは前記ロジック回路用ＭＩＳＦＥＴの半導体領域を露出する第１接続孔が形成され、前記第１層配線は前記第１接続孔内に形成された金属膜に接続されることを特徴とする半導体集積回路装置。A first connection hole that exposes a semiconductor region of the peripheral circuit MISFET or the logic circuit MISFET is formed in the first insulating film, and the first layer wiring is a metal film formed in the first connection hole A semiconductor integrated circuit device connected to the semiconductor integrated circuit device.
前記ストッパ膜は窒化シリコン膜であることを特徴とする半導体集積回路装置。The semiconductor integrated circuit device, wherein the stopper film is a silicon nitride film.
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| JP2004335811A JP3892867B2 (en) | 2004-11-19 | 2004-11-19 | Semiconductor integrated circuit device and manufacturing method thereof |
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| JP5613033B2 (en) | 2010-05-19 | 2014-10-22 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| US20120223413A1 (en) | 2011-03-04 | 2012-09-06 | Nick Lindert | Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layer |
| JP2015233069A (en) | 2014-06-09 | 2015-12-24 | ルネサスエレクトロニクス株式会社 | Semiconductor device and semiconductor device manufacturing method |
| JP6263093B2 (en) | 2014-06-25 | 2018-01-17 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| SG11202013103YA (en) * | 2018-08-07 | 2021-02-25 | Kioxia Corp | Semiconductor memory device |
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