JP2005101609A - Method of manufacturing on-chip bypass capacitor and chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a on-chip bypass capacitor and its manufacturing method. <P>SOLUTION: The on-chip bypass capacitor includes at least two capacitor arrays, each capacitor array includes a primary layer which couples at least two capacitor arrays in series, each capacitor array includes a plurality of capacitors, and each of the plurality of capacitors includes a secondary layer which couples a plurality of capacitors in parallel. The on-chip bypass capacitor may also be a part of the chip which further includes a memory cell array containing at least one cell capacitor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing an on-chip bypass capacitor and a chip.

  FIG. 1 illustrates a simplified configuration of a power supply network 10. The power supply network 10 may include parasitic elements including resistive on-chip parasitic elements and inductive off-chip parasitic elements. Further, the current flowing through these elements can induce a noise voltage represented by the following equation.

Ri + Ldi / dt
In the power supply network 10 of FIG. 1, a 10 watt chip can obtain 4 amps (DC current) at 2.5 volts, but may have a peak current of 10-20 amps.

  The difference between the peak current and the average current to filter noise can be provided by a local on-chip bypass capacitor or a decoupling capacitor. The difference between the peak current and the average current is illustrated in FIG.

In conventional processes, on-chip bypass capacitors can be formed in a manufacturing process similar to that used to form cell capacitors. The voltage across the cell capacitor of the memory cell is
(VINT-VSS) / 2
As shown.

  However, the voltage difference across the on-chip bypass capacitor is indicated by VINT / VSS, which can cause the oxide of the on-chip capacitor to degrade faster than the oxide of the cell capacitor.

  The present invention has been made in view of the above problems, for example, to reduce the voltage applied to both ends of each on-chip bypass capacitor array in order to reduce deterioration of the dielectric layer of the on-chip bypass capacitor array, or The purpose is to make the voltage substantially the same as the voltage applied to both ends of the memory cell array.

  A first aspect of the present invention relates to a method of manufacturing an on-chip bypass capacitor including a plurality of capacitor arrays each including a plurality of capacitors on a chip having at least one cell capacitor, the method including the at least one capacitor Forming a first layer that is common to each of the cell capacitor and the plurality of capacitor arrays, and connects the plurality of capacitors of each capacitor array in parallel; and the at least one cell capacitor and the plurality of capacitor arrays And forming a second layer that connects the plurality of capacitor arrays in series.

  A second aspect of the present invention relates to a chip, and the chip includes a memory cell array including at least one cell capacitor and an on-chip bypass capacitor including at least two capacitor arrays, each capacitor array including the at least one capacitor array. A first layer connecting two capacitor arrays in series is included, each capacitor array including a plurality of capacitors, and each of the plurality of capacitors includes a second layer connecting the plurality of capacitors in parallel. And

A third aspect of the present invention relates to a method of manufacturing an on-chip bypass capacitor including a plurality of capacitor arrays each including a plurality of capacitors on a chip having at least one cell capacitor, the method including the at least one capacitor Forming a cell capacitor and a layer common to each of the plurality of capacitor arrays,
The layer is characterized in that each of the plurality of capacitors of each capacitor array is connected in parallel, and the plurality of capacitor arrays are connected in series.

  A fourth aspect of the present invention relates to a chip, and the chip includes an on-chip bypass capacitor including a memory cell array including at least one cell capacitor and at least two capacitor arrays, and each capacitor array includes the at least one capacitor array. The capacitor array includes layers connecting two capacitor arrays in series, each capacitor array including a plurality of capacitors, and the layers further connect the plurality of capacitors in parallel.

  A fifth aspect of the present invention relates to a chip, which includes a memory cell array including at least one cell capacitor, a first electrode, a plurality of second electrodes, the first electrode, and the plurality of second electrodes. A first capacitor including a first portion of a second layer connecting the oxide layer and the plurality of second electrodes, a third electrode, a plurality of fourth electrodes, the third electrode, and the plurality of fourth electrodes A second capacitor including a second portion of the second layer that connects the oxide film and the plurality of fourth electrodes, and a first portion of the second layer and a second portion of the second layer And a first layer.

  In accordance with the present invention, for example, the voltage applied across each on-chip bypass capacitor array is reduced or the voltage applied across the memory cell array to reduce degradation of the dielectric layer of the on-chip bypass capacitor array. And can be substantially the same.

  The embodiments of the present invention are provided merely for illustrative purposes of the present invention and are not intended to limit the present invention. The present invention will be more fully understood from the following detailed description and the accompanying drawings.

  It should be noted that these drawings are intended to illustrate general features of the methods and apparatus of the embodiments of the present invention for purposes of describing the embodiments herein. However, these drawings are not actual sizes, and may not accurately reflect the characteristics of a given embodiment, and are interpreted as limiting the characteristics of the embodiment or the range of values within the scope of the present invention. must not.

  In particular, the relative thickness and position of the layers or regions may be reduced or enlarged for clarity. In addition, the layer formed on the reference layer or the substrate may be formed directly on the reference layer or the substrate, or may be formed on another layer or pattern on the reference layer.

  The following embodiment relates to an on-chip bypass capacitor including at least two on-chip bypass capacitor arrays connected in series.

  The following embodiments also relate to a chip including a memory cell array and an on-chip bypass capacitor including at least two on-chip bypass capacitor arrays connected in series.

  The following embodiments also relate to an on-chip bypass capacitor array including at least one capacitor connected in parallel.

  In the following embodiments, the on-chip bypass capacitor array and the memory cell array can be formed simultaneously using the same process steps.

According to the following embodiments, the voltage applied across each on-chip bypass capacitor array connected in series is reduced or made substantially the same as the voltage applied across the memory cell array. In addition, deterioration of the dielectric layer (eg, oxide layer) of the on-chip bypass capacitor array is reduced.
The following embodiments relate to an on-chip bypass capacitor including at least two on-chip bypass capacitor arrays connected in series by a first layer such as a common wiring.

  The following embodiments also relate to an on-chip bypass capacitor array that includes at least one capacitor connected in parallel by a second layer, such as a bit line.

  The following embodiments also relate to a chip in which at least two on-chip bypass capacitor arrays are connected in series, and the capacitors of each on-chip bypass capacitor array are connected in parallel using a single layer. A single layer can be a layer of common wiring and / or bit lines.

  The following embodiments also relate to an on-chip bypass capacitor including an on-chip bypass capacitor array formed after, above or below the memory cell array.

  The following embodiments also relate to a chip that includes an on-chip bypass capacitor and a memory cell array, and the memory cell array can be composed of MOS capacitors and / or multilayer capacitors.

  When the on-chip bypass capacitor array is stacked above or below the memory cell array, the on-chip bypass capacitor arrays are connected in series, and a single layer is used to connect the capacitors of each on-chip bypass capacitor array in parallel. There can be particular advantages when including MOS capacitors.

  The following embodiments may be used for any type of memory, for example DRAM memory.

  The following embodiment relates to a method for manufacturing the embodiment.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As illustrated in FIG. 3A, a chip according to an embodiment of the present invention may include an internal circuit (or a memory cell array capacitor) and an on-chip capacitor in parallel with the internal circuit, the on-chip capacitors being arranged in series. At least two capacitor arrays (C1, C2). The total capacitance C _total of the on-chip capacitor illustrated in FIG.
C _total = (C1 × C2) / (C1 + C2)
The voltage across each capacitor array (C1 and C2) is
△ V = 1/2 × VINT
It is.

  Although FIG. 3A illustrates two capacitor arrays (C1 and C2) connected in series, those skilled in the art will recognize that any number of capacitor arrays greater than two may be used.

  As illustrated in FIG. 3B, each capacitor array C1, C2 may include one or more capacitors connected in parallel. 3B illustrates four capacitors in parallel, those skilled in the art will appreciate that one or more capacitors can be arranged in parallel with the internal circuitry.

  As illustrated in FIGS. 3A and 3B, on-chip bypass capacitors according to embodiments of the present invention are formed using the same process steps used for internal circuitry (or memory cell array capacitors), and Capacitance can be increased by parallel connection of capacitors of the on-chip bypass capacitor array, and electrolysis between the oxide layers can be reduced by the serial arrangement of the on-chip bypass capacitor array, which contributes to improvement of reliability. .

  4A to 4F, a process for manufacturing an on-chip bypass capacitor on a chip having at least one cell capacitor is illustrated as an embodiment of the present invention. FIG. 4A illustrates the formation of an active region using an active photomask according to one embodiment of the present invention. The active photomask includes portions for both the cell array and the on-chip bypass capacitor array so that both are formed simultaneously. As shown in the figure, FIG. 4A illustrates not only a vertical structure diagram of the memory cell array and the on-chip bypass capacitor array but also a plan view. As shown in FIG. 4A, the active regions 170 are formed between the isolation regions 100 of the memory cell array, and the dummy active regions 270 are formed between the dummy isolation layers 200 of the on-chip bypass capacitor array. The plan view and the vertical structure view are views seen from Y1 and Y2. The plan view of FIG. 4A illustrates the active area 170.

  FIG. 4B illustrates the formation of word lines using a gate polyphotomask as an embodiment of the present invention. FIG. 4B illustrates a plan view and a vertical structure diagram illustrating the gate poly layer. As shown in the vertical structure diagram, word lines 110 are patterned to form transistors in the memory cell array, and dummy patterns 210 (which can be omitted) are patterned into an on-chip bypass capacitor array. The plan view and the vertical structure view are views seen from Y1 and Y2. The plan view of FIG. 4B illustrates the word line 110 associated with the active area 170.

  FIG. 4C illustrates the formation of a self-aligned contact (SAC) pad using a SAC photomask as an embodiment of the present invention. FIG. 4C illustrates a plan view and a vertical structure diagram of the memory cell array and the on-chip bypass capacitor array. As shown in the vertical structure diagram, a self-aligned contact pad 150 is formed in the memory cell array, and a self-aligned contact pad 250 is formed in the on-chip bypass capacitor array. As can be seen in the vertical structure portion of FIG. 4C, the self-aligned contact pads 150 of the memory cell array are patterned, but the self-aligned contact pads 250 of the on-chip bypass capacitor array are not patterned. The plan view and the vertical structure view are views seen from Y1 and Y2. The plan view of FIG. 4C illustrates a self-aligned contact pad 150 associated with the word line 110 and active region 170 of the memory cell array, and illustrates a self-aligned contact pad 250 of the on-chip bypass capacitor array.

  FIG. 4D illustrates the formation of a bit line contact using a bit line contact photomask as one embodiment of the present invention. FIG. 4D illustrates a plan view and a vertical structure diagram of the memory cell array and the on-chip bypass capacitor array. As shown in the vertical structure portion, a bit contact line 160 (only in Y2 of the embodiment illustrated in FIG. 4D and not in Y1) is formed in the memory cell array and a bit line contact 260 (implementation of FIG. 4D). Is only formed in the on-chip bypass capacitor array. 4D illustrates a self-aligned contact pad 150, a word line 110, and a bit contact line 160 related to the active region 170 of the memory cell array.

  FIG. 4E illustrates the formation of a bit line using a bit line photomask as an embodiment of the present invention. FIG. 4E illustrates a plan view and a vertical structure diagram of the memory cell array and the on-chip bypass capacitor array. As shown in the vertical structure portion, a bit line 120 (only in Y2 of the embodiment illustrated in FIG. 4E, not in Y1) is formed in the memory cell array, and can be connected in series 220 (can be connected in series) (Only in Y2 ′ of the illustrated embodiment of FIG. 4E) is formed in an on-chip bypass capacitor array.

  In FIG. 4F, cell formation is illustrated as an embodiment of the present invention. FIG. 4F illustrates a plan view and a vertical structure diagram of the memory cell array and the on-chip bypass capacitor array. A storage cell capacitor 180 (only in Y1 of the embodiment illustrated in FIG. 4F and not in Y2) is formed in the memory cell array as shown in the vertical structure portion, and a bypass capacitor 280 (illustrated in FIG. 4F). (Only in Y1 ′ of the embodiment) is formed in the on-chip bypass capacitor array. The electrodes 130, 140, 230, and 240 of the memory cell and the capacitor of the on-chip bypass capacitor array are formed simultaneously, and a dielectric layer is formed therebetween.

  FIG. 5 illustrates an on-chip bypass capacitor formed by the exemplary method shown in FIGS. 4A-4F.

  In FIG. 5, as one embodiment of the present invention, a first on-chip bypass capacitor array 300 (or C1 shown in FIG. 3A) and a second on-chip bypass capacitor array 400 (or C2 shown in FIG. 3B). The common wiring 220 is illustrated. As shown in FIG. 5, the first on-chip bypass capacitor array 300 (or C1) is connected in series with the second on-chip bypass capacitor array 400 (or C2).

  As shown in FIG. 5, the first on-chip bypass capacitor array 300 (or C1 shown in FIG. 3A) includes a dummy isolation layer 200, a dummy word line 210-a, a common wiring 220, and a first electrode 230-. a, a second electrode 240-a, a first self-aligned contact pad 250-a, a via contact 260-a, and a cell capacitor 270-a (one of which may be Vdd or VINT). Such a voltage can be applied as shown in FIGS. 3A and 3B). In one embodiment, the first electrode 230-a and the second electrode 240-a may be formed as doped polysilicon.

  As shown in FIG. 5, the second on-chip bypass capacitor array 400 (or C2 shown in FIG. 3B) includes a dummy isolation layer 200, a dummy word line 210-b, a common wiring 220, a third electrode 230- b, a fourth electrode 240-b, a second self-aligned contact pad 250-b, a via contact 260-b, and a cell capacitor 270-b (one of which is a voltage such as Vss as shown in FIG. 3A). And can be applied as shown in FIG. 3B). In one embodiment, the third electrode 230-b and the fourth electrode 240-b may be formed as doped polysilicon.

  As shown in FIG. 5, the SAC pad 150 is patterned in the memory cell array, but in the on-chip bypass capacitor arrays 300 and 400, the SAC pads 250-a and 250-b are a plurality of via contacts 260-a and 260. It was not patterned in the Y1 direction to provide electrical connection between -b and the plurality of third electrodes 240-a, 240-b. The SAC pad 250-a can be connected to the SAC pad 250-b through the common wiring 220 and the via contact 260. As described above, the common wiring 220 is also the bit line 120 in the memory cell array.

  As shown in FIG. 5, each of the on-chip bypass capacitor arrays 300, 400 may include one or more capacitors 270-a, 270-b in parallel. As shown in FIG. 5, all the second electrodes 240-a of the first on-chip bypass capacitor array 300 are connected to the SAC pad 250-a, and thus each capacitor 270 of the first on-chip bypass capacitor array 300. -A are connected to each other in parallel. Similarly, all the fourth electrodes 240-b of the second on-chip bypass capacitor array 400 are connected to the SAC pad 250-b, so that each capacitor 270-b of the second on-chip bypass capacitor array 400 is mutually connected. Connected in parallel.

  FIG. 6 illustrates an equivalent circuit of the vertical structure of the on-chip bypass capacitor of FIG. The reference numbers in FIG. 6 indicate the same reference numbers in FIG. For example, the electric line 220 is the common wiring 220 in FIG. The electrical wirings 260-a and 260-b are the via contacts 260-a and 260-b in FIG.

  As shown in FIG. 6, the equivalent circuit includes a first on-chip bypass capacitor array 300 (or C1) and a second on-chip bypass capacitor array 400 (or C2) connected in series, so that the total capacitance is C1. * C2 / (C1 + C2). This series connection can be formed by the common wiring 220. The capacitance C1 of the first on-chip bypass capacitor array 300 can be configured by connecting a plurality of capacitors 270-a in parallel. Similarly, the capacitance C2 of the second on-chip bypass capacitor array 400 can be configured by connecting a plurality of capacitors 270-b in parallel.

  FIG. 7 illustrates an equivalent circuit of another embodiment of the on-chip bypass capacitor of the present invention. The on-chip bypass capacitor array 900 of the equivalent circuit of FIG. 7 includes a first on-chip bypass capacitor array 600 (or C1), a second on-chip bypass capacitor array 700 (or C2) and a third on-chip bypass capacitor connected in series. Array 800 (or C3) is included. A series connection between the capacitor arrays 600, 700, and 800 can be formed by common wirings 220-a and 220-b. The common wiring 220-a can be the same layer formed simultaneously with the bit lines in the memory cell array, and the common wiring 220-b can be used when forming wirings such as the power supply voltage Vdd and the ground voltage Vss. It is also a wiring formed simultaneously. The first on-chip bypass capacitance C1 is configured by a parallel connection of a plurality of capacitors 270-a, and the second on-chip bypass capacitance C2 is configured by a parallel connection of a plurality of capacitors 270-b. C3 can be configured by a parallel connection of a plurality of capacitors 270-c.

  The electrical wirings 260-a, 260-b, 260-c, and 260-d are via contacts. The SAC pad 250-a is connected to the SAC pad 250-b through the via contact 260-a, the common wiring 220-a, and the via contact 260-b. The SAC pad 250-c is connected to the SAC pad 250-d through the via contact 260-c, the common wiring 220-b, and the via contact 260-d. All the first electrodes 230-a of the first on-chip bypass capacitor array 600 are commonly connected to the voltage Vdd or the voltage VINT, and all the second electrodes 240-a of the first on-chip bypass capacitor array 600 are connected to the SAC. It is connected to the pad 250-a. Accordingly, the capacitors 270-a of the first on-chip bypass capacitor array 600 are connected in parallel to each other. Similarly, all the third electrodes 230-b of the second on-chip bypass capacitor array 700 are connected to the SAC pad 250-c, and all the fourth electrodes 240-b of the second on-chip bypass capacitor array 700 are It is connected to the SAC pad 250-b. Accordingly, the capacitors 270-b of the second on-chip bypass capacitor array 700 are connected in parallel with each other. Similarly, all the fifth electrodes 230-c of the third on-chip bypass capacitor array 800 are connected to the SAC pad 250-d, and all the sixth electrodes 240-c of the third on-chip bypass capacitor array 800 are Commonly connected to the voltage Vss. Accordingly, the capacitors 270-c of the third on-chip bypass capacitor array 800 are connected in parallel to each other.

  The common wirings 220-a and 220-b are in a floating state where a voltage cannot be applied. As a result, the first, second, and third on-chip bypass capacitor arrays 600, 700, and 800 are configured to be connected in series between the voltage Vdd and the voltage Vss. Accordingly, the total capacitance of the on-chip bypass capacitor array 900 is C1 × C2 × C2 / (C1 + C2 + C3).

  When 30 capacitors are divided into two groups to form two groups of on-chip bypass capacitor arrays, if the capacitance of each of the 30 capacitors is C, the capacitance of each group is C × 15. Becomes C × 15/2. On the other hand, when 30 capacitors are divided into three groups to form three groups of on-chip bypass capacitor arrays, the capacitance of each group is C × 10, and the total capacitance is C × 10/3.

  As a result, if the memory cell capacitors are divided into three groups instead of two groups in the same area to form an on-chip bypass capacitor array, the capacitance is reduced.

  While embodiments of the present invention have been described with two and three on-chip bypass capacitor arrays, those skilled in the art will appreciate that any number of on-chip bypass capacitor arrays greater than two or three can be used. Understand. While embodiments of the present invention have been described with each on-chip bypass capacitor array including four capacitors, those skilled in the art will appreciate that any number of capacitors greater than or equal to one can be used. Also, those skilled in the art will appreciate that the number of capacitors in each on-chip bypass capacitor array can vary.

  Although the embodiments of the present invention have been described with respect to on-chip bypass capacitor arrays connected in series with a common wire, those skilled in the art will recognize that any different layers can be used to connect the on-chip bypass capacitor arrays. I understand well.

  Similarly, although embodiments of the present invention have been described for capacitors in each on-chip bypass capacitor array connected in parallel by bit lines, any different layers can be used to connect the capacitors in each on-chip bypass capacitor array in parallel. Those skilled in the art will appreciate that can be used.

  In the embodiment of the present invention, the on-chip bypass capacitor array connected in series by the common wiring and the capacitor of each on-chip bypass capacitor array connected in parallel by the bit line have been described. However, the on-chip bypass capacitor array is connected in series. One skilled in the art will appreciate that a single layer can be used to connect the capacitors of each on-chip bypass capacitor array in parallel.

  Although embodiments of the present invention have been described with respect to forming an on-chip bypass capacitor array after a memory cell array, those skilled in the art will recognize that an on-chip bypass capacitor array can be stacked above or below the memory cell array. I understand well.

  Although embodiments of the present invention have generally described a memory cell array, those skilled in the art will appreciate that a memory cell array can be composed of MOS capacitors and / or multilayer capacitors. When the on-chip bypass capacitor array is stacked above or below the memory cell array, the on-chip bypass capacitor arrays are connected in series, and a single layer is used to connect the capacitors of each on-chip bypass capacitor array in parallel. Those skilled in the art will appreciate that can include a particular advantage when including a MOS capacitor.

  Those skilled in the art will appreciate that embodiments of the present invention may be used with any type of memory, such as DRAM memory.

  Those skilled in the art will appreciate that in embodiments of the present invention, an on-chip bypass capacitor array can be formed simultaneously using process steps similar to a memory cell array.

  In an embodiment of the present invention, the voltage applied across each on-chip bypass capacitor array in series is reduced or memory is reduced to reduce degradation of the dielectric layer (oxide layer) of the on-chip bypass capacitor array. Those skilled in the art will appreciate that the voltage applied across the cell array can be substantially the same.

  4A-4F and FIGS. 5-6 illustrate a specific process that generates a specific final structure with a specific equivalent circuit, the published process generates other final structures with other equivalent structures. The published final structure can be generated by other processes, the published equivalent structure can also be generated by other processes, and can correspond to other final structures. Those skilled in the art will understand what can be done.

  It will be apparent to those skilled in the art that other changes and modifications can be practiced in the above-described embodiments without departing from the scope of the invention, and all matters contained in the above description are exemplary. It is designed to be analyzed as non-limiting.

It is an illustration figure of the conventional simple power supply network. FIG. 6 is a diagram illustrating a difference between a peak current and an average current that can be supplied by a conventional local on-chip bypass capacitor or a decoupling capacitor. 1 is an exemplary view of a chip according to an embodiment of the present invention. FIG. FIG. 3 is an exemplary view of a capacitor array according to an embodiment of the present invention. FIG. 3 is an exemplary view of forming an active region using an active photomask according to an embodiment of the present invention. FIG. 5 is an exemplary view of forming a word line using a gate poly photomask according to an embodiment of the present invention. FIG. 3 is an exemplary view of forming a self-aligned contact (SAC) pad using a SAC photomask according to an embodiment of the present invention. FIG. 4 is an exemplary view of forming a bit line contact using a bit line contact photomask according to an embodiment of the present invention. FIG. 3 is an exemplary view of forming a bit line using a bit line photomask according to an embodiment of the present invention. FIG. 4 is an exemplary view of formation of a cell according to an embodiment of the present invention. 5 is an exemplary diagram of two on-chip bypass capacitor arrays formed by the exemplary method shown in FIGS. 4A-4F. FIG. FIG. 6 is an equivalent circuit diagram of a vertical structure of the on-chip bypass capacitor of FIG. 5. FIG. 6 is an equivalent circuit diagram of an on-chip bypass capacitor according to another embodiment of the present invention.

Claims (37)

In a method of manufacturing an on-chip bypass capacitor including a plurality of capacitor arrays each including a plurality of capacitors on a chip having at least one cell capacitor,
Forming a first layer common to each of the at least one cell capacitor and the plurality of capacitor arrays, and connecting each of the plurality of capacitors of each capacitor array in parallel;
Forming a second layer common to each of the at least one cell capacitor and the plurality of capacitor arrays and connecting the plurality of capacitor arrays in series;
The manufacturing method of the on-chip bypass capacitor characterized by including these.   The method of claim 1, wherein the first layer is a non-patternable region of the self-aligned contact pad of the at least one cell capacitor.   2. The on-chip bypass according to claim 1, wherein the second layer is a bit line layer of the at least one cell capacitor that serves as a common wiring among the plurality of capacitor arrays. A method for manufacturing a capacitor.   The method for manufacturing an on-chip bypass capacitor according to claim 1, wherein the first layer and the second layer are the same layer.   The method of manufacturing an on-chip bypass capacitor according to claim 4, wherein the layer is a polysilicon layer. The at least one capacitor is a MOS capacitor;
The method of manufacturing an on-chip bypass capacitor according to claim 4, wherein the on-chip bypass capacitor is formed on the MOS capacitor.   The method of manufacturing an on-chip bypass capacitor according to claim 1, wherein the at least one cell capacitor is a multilayer capacitor.   The method of manufacturing an on-chip bypass capacitor according to claim 1, wherein the series connection between the at least two capacitor arrays is between the first layers of the at least two capacitor arrays. A memory cell array including at least one cell capacitor;
An on-chip bypass capacitor including at least two capacitor arrays;
Each capacitor array includes a first layer connecting the at least two capacitor arrays in series;
Each capacitor array includes a plurality of capacitors,
Each of the plurality of capacitors includes a second layer that connects the plurality of capacitors in parallel.   The chip of claim 9, wherein the first layer is a non-patternable region of a self-aligned contact pad of the at least one cell capacitor.   10. The chip according to claim 9, wherein the second layer is a bit line layer of the at least one cell capacitor that serves as a common wiring between the at least two capacitor arrays.   The chip according to claim 9, wherein the first layer and the second layer are the same layer.   The chip according to claim 12, wherein the layer is a polysilicon layer. The at least one capacitor is a MOS capacitor;
The chip of claim 12, wherein the on-chip bypass capacitor is formed on the MOS capacitor.   The chip according to claim 9, wherein the at least one cell capacitor is a multilayer capacitor.   The chip of claim 9, wherein the serial connection between the at least two capacitor arrays is between first layers of the at least two capacitor arrays. In a method of manufacturing an on-chip bypass capacitor including a plurality of capacitor arrays each including a plurality of capacitors on a chip having at least one cell capacitor,
Forming a layer common to each of the at least one cell capacitor and the plurality of capacitor arrays;
The method of manufacturing an on-chip bypass capacitor, wherein the layer connects the plurality of capacitors of each capacitor array in parallel and connects the plurality of capacitor arrays in series.   The layer is an unpatterned region of the self-aligned contact pad of at least one cell capacitor and / or the bit line of the at least one cell capacitor serving as a common wiring between each of the plurality of capacitor arrays. The method of manufacturing an on-chip bypass capacitor according to claim 17.   The method of manufacturing an on-chip bypass capacitor according to claim 17, wherein the layer is a polysilicon layer. The at least one capacitor is a MOS capacitor;
The method of manufacturing an on-chip bypass capacitor according to claim 20, wherein the on-chip bypass capacitor is formed on the MOS capacitor.   The method of claim 17, wherein the at least one cell capacitor is a multilayer capacitor. A memory cell array including at least one cell capacitor;
At least two capacitor arrays;
Including an on-chip bypass capacitor
Each capacitor array includes a layer connecting the at least two capacitor arrays in series, each capacitor array includes a plurality of capacitors, and the layer further connects the plurality of capacitors in parallel.   The layer is an unpatterned region of the self-aligned contact pad of the at least one cell capacitor and / or a bit line of the at least one cell capacitor serving as a common wiring between each of the plurality of capacitor arrays. The chip according to claim 22.   The chip of claim 22, wherein the layer is a polysilicon layer. The at least one capacitor is a MOS capacitor;
The chip of claim 22, wherein the on-chip bypass capacitor is formed on the MOS capacitor.   The chip of claim 22, wherein the at least one cell capacitor is a multilayer capacitor. A memory cell array including at least one cell capacitor;
A first capacitor including a first electrode, a plurality of second electrodes, a first portion of a second layer connecting the oxide layer and the plurality of second electrodes between the first electrode and the plurality of second electrodes; ,
A second capacitor including a third electrode, a plurality of fourth electrodes, and a second portion of the second layer connecting the oxide film and the plurality of fourth electrodes between the third electrode and the plurality of fourth electrodes. When,
A first layer connecting the first portion of the second layer and the second portion of the second layer;
A chip comprising:   28. The chip of claim 27, wherein the first electrode of the first capacitor and the third electrode of the second capacitor are connected to a first power source and a second power source, respectively.   28. The chip of claim 27, wherein the first electrode is a plate polysilicon layer of the at least one cell capacitor.   30. The chip of claim 29, wherein the second electrode is a storage polysilicon layer of the at least one cell capacitor.   29. The chip of claim 28, wherein the first power source is one of an external VCC generator, an external VDD generator, and an internal DC generator.   28. The chip of claim 27, wherein the second layer is a non-patternable portion of the self-aligned contact pad layer of the at least one cell capacitor.   28. The chip of claim 27, wherein the first layer is a bit line of the at least one cell capacitor that serves as a common wiring between second electrodes of the first and second capacitors.   28. The chip according to claim 27, wherein the first layer and the second layer are the same layer.   The chip of claim 34, wherein the layer is a polysilicon layer. The at least one cell capacitor is a MOS capacitor;
The chip of claim 34, wherein the on-chip bypass capacitor is formed on the MOS capacitor.   28. The chip of claim 27, wherein the at least one cell capacitor is a multilayer capacitor.

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