JP2005098809A - Inspection system, method, signal processor and its method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily and speedily inspect a plurality of signal sources inside a semiconductor circuit. <P>SOLUTION: Phase-locked loops PLL201 to PLL203 respectively produce signals 111 to 113. An OR circuit 221 operates logical sum of signals 111 to 113 and produces a signal 191. The signal analysis part 151 analyzes the signal 191 by, for example, using discrete Fourier transformation etc., and supplies the analysis results to a display 152. The display 152 indicates the input analysis results. By this, a plurality of PLLs inside the semiconductor circuit can be inspected easily and speedily. This invention, for example, can be applied to a semiconductor circuit checking device. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an inspection system and method, and a signal processing apparatus and method, and more particularly to an inspection system and method, and a signal processing apparatus, which can easily and quickly inspect a plurality of signal sources inside a semiconductor circuit. And methods.

  The semiconductor circuit has a plurality of signal sources inside and performs various signal processing based on signals generated by the signal sources. If the signal source is broken, correct signal processing results cannot be obtained. Therefore, it is necessary to check whether or not the signal source has failed.

  FIG. 1 shows a configuration example of a conventional semiconductor circuit inspection system 1.

  The semiconductor circuit inspection system 1 measures and inspects a semiconductor circuit 11 with a measuring device 12.

  The semiconductor circuit 11 includes three signal sources 31, a signal source 32, and a signal source 33, and a corresponding number of three terminals 41, a terminal 42, and a terminal 43. The signal sources 31 to 33 generate signals 1 to 3, respectively, and are used in an internal circuit (not shown). In order to be able to inspect the signals 1 to 3 from the outside, terminals 41 to 43 are provided, and the signals 1 to 3 are supplied to the terminals 41 to 43 (that is, test terminals used for signal inspection). Is done. The terminals 41 to 43 output the signals 1 to 3 supplied from the signal sources 31 to 33 to the outside. The measuring device 12 receives the signals 1 to 3 output from the terminals 41 to 43 and measures each of them simultaneously.

  That is, in the semiconductor circuit inspection system 1 of FIG. 1, the three signal sources 31 to 33 can be inspected simultaneously by measuring the signals 1 to 3 simultaneously. Therefore, in the semiconductor circuit inspection system 1 of FIG. 1, it is possible to inspect in a short time whether or not a plurality of signal sources have failed in the semiconductor circuit 11.

  FIG. 2 shows another configuration example of the conventional semiconductor circuit inspection system 1. The components corresponding to the configuration of the semiconductor circuit inspection system 1 in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted to avoid repetition.

  In this example, a signal switching unit 61 and one terminal 81 are provided. The signal switching unit 61 selects any one of the signals 1 to 3 supplied from the signal sources 31 to 33 based on a selection signal input from the outside, and supplies the selected signal 71 to the terminal 81. To do. The terminal 81 outputs the signal 71 supplied from the signal switching unit 61 to the measuring device 12. The measuring device 12 measures the signal 71 input from the terminal 81.

  That is, in the semiconductor circuit inspection system 1 of FIG. 2, a plurality of signals (FIG. 2) generated by a plurality of signal sources (three signal sources 31 to 33 in the example of FIG. 2) inside the semiconductor circuit 11 are used. In the case of this example, any one of the three signals 1 to 3) is sequentially selected and used as a test signal (in the case of the example of FIG. Therefore, in the semiconductor circuit inspection system 1 of FIG. 2, the three signal sources 31 to 33 inside the semiconductor circuit 11 can be inspected in a time division manner by measuring the signal 71 supplied from the terminal 81.

  As described above, in the semiconductor circuit inspection system 1 in FIG. 2, it takes more time to inspect a plurality of signals in the semiconductor circuit 11 than in the semiconductor circuit inspection system 1 in FIG. The number of test terminals used in the inspection of a plurality of signals inside the semiconductor circuit 11 can be made smaller than the number of signal sources inside the semiconductor circuit 11. For example, in the example of FIG. 2, the number of signal sources is three (for example, signal sources 31 to 33), but the number of terminals can be one (for example, terminal 81).

JP-A-6-252774

  However, in the conventional semiconductor circuit inspection system 1 in FIG. 2, the number of test terminals of the semiconductor circuit 11 can be reduced, but there is a problem that inspection takes time.

  The present invention has been made in view of such a situation, and an object thereof is to enable a simple and quick inspection of a plurality of signal sources inside a semiconductor circuit.

  The inspection system of the present invention is an inspection system comprising an inspected apparatus and an inspection apparatus for inspecting the inspected apparatus. The inspected apparatus includes two or more first signals generating means and generating means. An arithmetic means for calculating two or more generated first signals to generate a smaller number of second signals; an output means for outputting the second signals generated by the arithmetic means to the inspection apparatus; The inspection apparatus includes an analysis unit that analyzes the second signal output by the output unit, and a display unit that displays an analysis result by the analysis unit.

  The generation unit can generate a second signal by calculating a logical sum of two or more first signals or adding two or more first signals.

  The analysis means can analyze the second signal using discrete Fourier transform.

  The analysis means can analyze the frequency component of the first signal.

  The generating means may include a PLL.

  An inspection method of the present invention is an inspection method for an inspection system comprising an inspected device and an inspection device for inspecting the inspected device, wherein the inspected device generates two or more first signals; and An arithmetic step for calculating two or more first signals generated by the processing of the generation step to generate a smaller number of second signals, and an inspection of the second signal generated by the processing of the arithmetic step The inspection apparatus includes an analysis step for analyzing the second signal output by the process of the output step, and a display step for displaying the analysis result by the process of the analysis step. Features.

  The signal processing apparatus according to the present invention generates a smaller number of second signals for inspection by generating two or more first signals and generating means for generating two or more first signals. It is characterized by comprising a computing means and a smaller number of output means than the first signal for outputting the second signal for inspection generated by the computing means to the outside.

  The signal processing apparatus may further include an analysis unit that analyzes the second signal.

  According to the signal processing method of the present invention, two or more first signals are generated, and the two or more first signals are operated to generate a smaller number of second signals for inspection. The second signal for inspection is output to the inspection device from a smaller number of output terminals than the first signal.

  In the inspection system and method of the present invention, in the inspection system comprising the device to be inspected and the inspection device for inspecting the device to be inspected, the device to be inspected generates and generates two or more first signals. Two or more first signals are calculated to generate a smaller number of second signals and output to the generated inspection device, the inspection device analyzes the output second signal, and Display analysis results.

  In the signal processing apparatus and method of the present invention, two or more first signals are generated, and the two or more first signals are calculated to generate a smaller number of second signals for inspection. The generated second signal for inspection is output to the outside.

  According to the present invention, it is possible to inspect signals inside the device under inspection. In particular, it is possible to reduce the number of inspection signals output for inspecting a plurality of signals of the device under inspection without compressing or expanding the signals. In addition, since a plurality of signals are inspected at the same time, a quick inspection is possible. As a result, it is possible to easily and quickly inspect which signal source out of a plurality of signal sources is malfunctioning inside the apparatus to be inspected.

  Embodiments of the present invention will be described below. Correspondences between constituent elements described in the claims and specific examples in the embodiments of the present invention are exemplified as follows. This description is to confirm that specific examples supporting the invention described in the claims are described in the embodiments of the invention. Therefore, even if there are specific examples that are described in the embodiment of the invention but are not described here as corresponding to the configuration requirements, the specific examples are not included in the configuration. It does not mean that it does not correspond to a requirement. On the contrary, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.

  Further, this description does not mean that all the inventions corresponding to the specific examples described in the embodiments of the invention are described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of an invention not described in the claims of this application, that is, in the future, a divisional application will be made. It does not deny the existence of an invention that is added by correction.

[Claim 1]
An inspection system (for example, FIG. 4) including an inspection target device (for example, the semiconductor circuit 101 of FIGS. 4 and 12) and an inspection device (for example, the signal inspection device 102 of FIGS. 4 and 12) for inspecting the inspection target device. 4 and the semiconductor circuit inspection system 81) of FIG.
The inspected device is:
Generation means for generating two or more first signals (for example, the signals 111 to 113 in FIGS. 4 and 12) (for example, steps S1 in FIG. 5 and step S21 in FIG. 13 are executed). 12 PLLs 201 to 203),
Two or more of the first signals generated by the generating means are calculated, and a smaller number of second signals (for example, the signal 191 in FIG. 4 and the signals 221-1 and 221-in FIG. 12) are calculated. 2) generating means (for example, the OR circuit 221 in FIG. 4 and the adding circuit 261 in FIG. 12 that execute the processing in step S2 in FIG. 5 and step S22 in FIG. 13);
Output means for outputting the second signal generated by the arithmetic means to the inspection apparatus (for example, the terminal 141 in FIG. 4 for executing the processing of step S3 in FIG. 5 and step S23 in FIG. 13 and FIG. 12). Terminal 241-1 and terminal 241-2),
The inspection device includes:
Analysis means for analyzing the second signal output by the output means (for example, the signal analysis unit 151 in FIG. 4 and FIG. 12 that executes the processing in step S4 in FIG. 5 and step S24 in FIG. 13),
Display means for displaying the analysis results (for example, the output results of FIGS. 7, 9, 11, and 15) by the analysis means (for example, the processing for executing steps S5 and S25 in FIGS. 5 and 13) 4 and the display unit 152) of FIG.
[Claim 2]
The generating means generates the second signal by calculating a logical sum of two or more of the first signals, or adding two or more of the first signals. The inspection system according to claim 1.
[Claim 3]
The inspection system according to claim 1, wherein the analysis unit analyzes the second signal using a discrete Fourier transform.
[Claim 4]
The signal processing system according to claim 1, wherein the analysis unit analyzes a frequency component of the first signal.
[Claim 5]
The signal processing system according to claim 1, wherein the generation unit includes a PLL.
[Claim 6]
An inspection system (for example, FIG. 4) including an inspection target device (for example, the semiconductor circuit 101 of FIGS. 4 and 12) and an inspection device (for example, the signal inspection device 102 of FIGS. 4 and 12) for inspecting the inspection target device. 4 and the inspection method of the semiconductor circuit inspection system 81) of FIG.
The inspected device is:
A generation step (for example, step S1 in FIG. 5 and step S21 in FIG. 13) for generating two or more first signals (for example, signals 111 to 113 in FIGS. 4 and 12);
Two or more first signals generated by the processing of the generating step are calculated, and a smaller number of second signals (for example, the signal 191 in FIG. 4 and the signal 221-1 in FIG. 221-2) to generate (for example, step S2 in FIG. 5 and step S22 in FIG. 13),
An output step (for example, step S3 in FIG. 5 and step S23 in FIG. 13) that outputs the second signal generated by the processing of the calculation step to the inspection device;
The inspection device includes:
An analysis step (for example, step S4 in FIG. 5 and step S24 in FIG. 13) for analyzing the second signal output by the processing in the output step;
A display step (for example, steps S5 and S25 in FIGS. 5 and 13) for displaying an analysis result (for example, the output results in FIGS. 7, 9, 11, and 15) by the processing of the analysis step. Inspection method characterized by that.
[Claim 7]
Generation means for generating two or more first signals (for example, the signals 111 to 113 in FIGS. 4 and 12) (for example, steps S1 in FIG. 5 and step S21 in FIG. 13 are executed). 12 PLLs 201 to 203),
Two or more of the first signals are calculated to generate a smaller number of second signals for inspection (for example, the signal 191 in FIG. 4 and the signals 221-1 and 221-2 in FIG. 12). Arithmetic means (for example, the OR circuit 221 in FIG. 4 and the adder circuit 261 in FIG. 12 that execute the processing in step S2 in FIG. 5 and step S22 in FIG. 13);
The second signal for inspection generated by the arithmetic means is output to the outside, and the output means is smaller in number than the first signal (for example, the processing of step S3 in FIG. 5 and step S23 in FIG. 13 is performed). 4. A signal processing apparatus comprising: the terminal 141 of FIG. 4 to be executed; and the terminals 241-1 and 241-2) of FIG.
[Claim 8]
Analysis means for analyzing the second signal (for example, the signal analysis unit 151 in FIG. 4 and FIG. 12 that executes the processing in step S4 in FIG. 5 and step S24 in FIG. 13).
The signal processing apparatus according to claim 7, further comprising:
[Claim 9]
In the signal processing method of the signal processing device,
Generate two or more first signals (eg, signals 111 through 113 in FIGS. 4 and 12);
Two or more of the first signals are calculated to generate a smaller number of second signals for inspection (for example, the signal 191 in FIG. 4 and the signals 221-1 and 221-2 in FIG. 12). And
The generated second signal for inspection is output to the inspection device from a smaller number of output terminals than the first signal.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 3 shows the overall configuration of a semiconductor circuit inspection system 81 to which the present invention is applied.

  The semiconductor circuit inspection system 81 inspects a semiconductor circuit 101 as an inspected apparatus by a signal inspection apparatus 102 as an inspection apparatus.

  For example, an IC (Integrated Circuit), an LSI (Large Scale Integration), a VLSI, and other semiconductor circuits 101 have signal sources 171 to 173 as the signal generation unit 131. Signals 111 to 113 as clocks of different frequencies generated by the signal sources 171 to 173 are supplied to a circuit (not shown) of the semiconductor circuit 101 and used for signal processing. In order to be able to inspect the signal sources 171 to 173 from the outside, a signal calculation unit 132 and one terminal 141 are provided.

  The signal calculation unit 132 includes a signal calculation device 191. For example, the signal sources 171 to 173 generate clocks having a frequency of 12.5 Hz, 10 Hz, or 8.33 Hz, respectively, and supply the clocks as signals 111 to 113 to the signal arithmetic unit 191. The signal calculation device 191 generates one signal 121 by calculating the signals 111 to 113 supplied from the signal sources 171 to 173 by a predetermined method (for example, by performing an OR operation or an addition operation) ( One signal including the frequency components of the original signals 111 to 113 is calculated and generated, and supplied to one terminal 141. A terminal 141 for outputting an inspection signal to the outside outputs the signal 121 supplied from the signal arithmetic unit 191 to the signal inspection apparatus 102 connected to the terminal 141 via a cord (not shown).

  The signal inspection apparatus 102 includes a signal analysis unit 151 and a display unit 152. The signal analysis unit 151 analyzes the signal 121 input from the semiconductor circuit 101 to be inspected by a predetermined conversion method, for example, discrete Fourier transform (DFT), and the analysis result is displayed on the display unit 152. Supply.

  The display unit 152 includes a display (not shown) configured by a CRT (Cathode-Ray Tube), an LCD (Liquid Crystal Display), and the like, and displays the analysis result supplied from the signal analysis unit 151. The inspector looks at this display and determines whether or not the semiconductor circuit 101 is acceptable.

  FIG. 4 shows a specific example of the semiconductor circuit 101. In this example, the signal sources 171 to 173 are configured by PLL (Phase Locked Loop) 201 to PLL 203, and the signal arithmetic unit 191 is configured by an OR circuit 221.

  Each of the PLL 201 to PLL 203 generates a clock having a specific frequency and supplies it to the OR circuit 221 as signals 111 to 113. The OR circuit 221 calculates the logical sum of the signals 111 to 113 supplied from the PLL 201 to PLL 203, generates one signal 191 as the logical result, and supplies the signal 191 to the terminal 141.

  Next, the semiconductor circuit inspection process of the semiconductor circuit inspection system 81 of FIG. 4 will be described with reference to the flowchart of FIG.

  In step S1, the PLL 201 to PLL 203 generate digital signals 111 to 113, respectively. In step S <b> 2, the OR circuit 221 calculates a logical sum of the three signals 111 to 113 supplied from the PLL 201 to PLL 203 and generates one signal 191.

  With reference to FIG. 6, the OR operation in the OR circuit 221 will be described.

  The first column to the third column in FIG. 6 indicate the logical values of the signals 111 to 113 supplied from the PLL 201 to the PLL 203 to the OR circuit 221 at the respective sampling points (sampling points indicated by numbers 0 to 1023). In the fourth column, the logical value of the signal 191 obtained by the operation in the OR circuit 221 is shown.

  For example, as shown in the first row, when the logical values of the signals 111 to 113 supplied from the PLL 201 to the PLL 203 to the OR circuit 221 are “1”, “1”, and “1”, respectively, The logical value of the signal 191 generated by the OR operation of the OR circuit 221 is “1”. For example, as shown in the seventh line, the logical values of the signals 111 to 113 supplied from the PLL 201 to the PLL 203 to the OR circuit 221 are “0”, “0”, and “0”, respectively. In this case, the logical value of the signal 191 generated by the OR operation of the OR circuit 221 is “0”.

  Further, for example, as shown in the sixth line, when at least one of the logic values 111 to 113 supplied from the PLL 201 to the PLL 203 to the OR circuit 221 is “1”, the logic of the OR circuit 221 The logical value of the signal 191 generated by the sum operation is “1”.

  In this way, a single test signal that holds the frequency components of the signals 111 to 113 without compressing the three signals 111 to 113 supplied from the PLL 201 to the PLL 203 to the OR circuit 221 (i.e., A signal 191) can be generated. Therefore, the terminal that outputs the inspection signal can be a single terminal (in the example of FIG. 4, the terminal 141). That is, even if the number of signal sources inside the semiconductor circuit 101 is 10, for example, the number of test terminals can be reduced to one.

  In step S <b> 3, the terminal 141 outputs the signal 191 supplied from the OR circuit 221 to the signal analysis unit 151.

  In step S4, the signal analysis unit 151 analyzes the signal 191 input from the terminal 141 by a predetermined conversion method, for example, discrete Fourier transform.

  Here, the discrete Fourier transform performed in the signal analysis unit 151 will be described. Discrete Fourier transform is one of orthogonal transforms, and is a transform method for transforming an input time-series waveform into several fundamental frequencies. By using this discrete Fourier transform, it is possible to analyze what frequency components are included in a signal represented on a certain finite time axis. In other words, by using the discrete Fourier transform, it is possible to analyze how much the signal strength of the frequency component contained in the signal represented on a certain finite time axis is.

  In the discrete Fourier transform processing performed in the signal analysis unit 151, first, the signal 191 including the frequency components of the signals 111 to 113 of the PLL 201 to PLL 203 input from the terminal 141 is obtained at predetermined time intervals (with a sampling period Ts). , Sampled N times.

Next, sampling data when sampling is performed N times at the sampling period Ts (in the case of FIG. 6, the logical value of the signal 191 in the fourth column), that is, a discrete data sequence x (n ) (n = 0,1,2, ..., N-1), N complex Fourier series X (i) (i = 0,1,2, ..., N-1) It is calculated by (1).

When the complex Fourier series X (i) is obtained by equation (1), the original discrete data series x (n) is obtained by equation (2). The original discrete data sequence x (n) obtained by this equation (2) is N represented by the frequency n / (N Ts) (n = 0, 1, 2,..., N-1). It is a discrete Fourier transform output of the fundamental frequency.

Further, in the discrete Fourier transform, using the complex Fourier series X (i) obtained by the equation (1), the absolute value of the discrete Fourier transform output | X (i) | (i = 0,1,2, ..., N-1) is obtained. In the discrete Fourier transform, the frequency contained in a signal represented on a certain finite time axis is obtained by squaring the absolute value | X (i) | obtained by the equations (3) and (4) The signal intensities (so-called spectral intensities) of N fundamental frequencies represented by 0 to frequency n / ((N−1) Ts) are obtained.

  In the fifth column of FIG. 6, sampling numbers 0 to N, which are the numbers of the sampling data when N times are sampled at the sampling period Ts, are sequentially shown. In the case of the example in FIG. 6, since sampling has been performed 1024 times, sampling numbers 0 to 1023 are sequentially shown. In the sixth column to the ninth column in FIG. 6, “discrete Fourier transform output”, “absolute value”, “signal intensity” in the calculation process when the discrete Fourier transform is performed in the signal analysis unit 151, And “Frequency” are shown respectively.

  The “discrete Fourier transform output” in the sixth column means the discrete Fourier transform output of N fundamental frequencies represented by the frequency n / (N Ts), and x ( The numerical value of n). For example, in the second row of the sixth column, the “discrete Fourier transform output” is “2.00848159008397-6.1325196866612E-002i”, and is composed of a real part and an imaginary part. The real part is a sine function and the imaginary part is a cosine function.

  The “absolute value” in the seventh column means the amplitude when the real part of the “discrete Fourier transform output” in the sixth column is expressed by a sine function. The absolute value obtained by equation (3) | X (i) |. For example, in the second row of the seventh column, the “absolute value” is “2.009418”.

  “Signal strength” in the eighth column means the signal strengths of N fundamental frequencies represented by frequencies 0 to n / ((N−1) Ts). It is a numerical value obtained by squaring "value". This value is the spectral intensity. For example, in the second row of the eighth column, the “signal strength” is “4.037759”, which is a value obtained by squaring the absolute value “2.009418” of the second row of the seventh column.

  “Frequency” in the ninth column means the intensity of N fundamental frequency components represented by frequency 0 to frequency n / ((N−1) Ts). For example, in the second row of the ninth column, “Frequency” is “0.097656”.

  In the case of the example of FIG. 6, as described above, the number N of sampling data per time in the discrete Fourier transform is, for example, 1024 (that is, 0 to 1023), and the sampling period Ts is 1 Therefore, the intensities of the 1024 fundamental frequency components represented by frequency 0 to frequency n / ((N-1) Ts) are 0 to 99.90234, respectively, as shown in FIG. Become.

  In step S <b> 5, the display unit 152 displays the analysis result supplied from the signal analysis unit 151.

  FIG. 7 shows a first display example of the display unit 152 in step S5.

  In the display example of FIG. 7, significant signal intensity peaks are displayed at frequencies of 8.33 MHz, 10 MHz, and 12.5 MHz. Accordingly, the frequencies of the signals 111 to 113 can be specified as 12.5 MHz, 10 MHz, and 8.33 MHz, respectively.

  As shown in FIG. 7, the frequency components displayed on the display unit 152 include frequency components other than the frequencies 12.5 MHz, 10 MHz, and 8.33 MHz of the signals 111 to 113 generated by the PLL 201 to PLL 203. It is. This is because the linearity of the signals 111 to 113 supplied from the PLL 201 to the PLL 203 to the OR circuit 221 is not held by the OR circuit 221 and the signals 111 to 113 are rectangular waves.

  In the case of the second display example of FIG. 9, for example, because the PLL 202 of FIG. 4 has failed, the signal 112 having a frequency of 10 MHz cannot be generated, and as shown in FIG. It is assumed that the logical value of the signal 112 supplied to the OR circuit 221 is always fixed to “0”. In this case, since the signal 112 generated by the PLL 202 becomes “0” even when the logical value must be “1”, the signal 191 supplied from the OR circuit 221 to the terminal 141 is When the value must be “1”, it becomes “0”. As a result, as shown in FIG. 9, even if discrete Fourier transform is performed in the signal analysis unit 151, a significant signal intensity peak is not displayed at a frequency of 10 MHz.

  Therefore, in the case of the example of FIG. 9, it can be seen from the signal intensity displayed on the display unit 152 that the PLL 202 serving as the signal source inside the semiconductor circuit 101 has failed.

  On the other hand, in the case of the third display example of FIG. 11, for example, the PLL 202 of FIG. 4 is out of order, so the signal 112 having a frequency of 10 MHz cannot be generated, and as shown in FIG. Further, it is assumed that the logical value of the signal 112 is always fixed to “1”. In this case, the logical value of the signal 112 generated by the PLL 202 is “1” even when the signal 112 has to be “0”. Therefore, the logical value of the signal 191 is always fixed to “1”. Become. As a result, as shown in FIG. 11, even if the discrete Fourier transform is performed in the signal analysis unit 151, it is remarkable at any frequency (for example, 8.33 MHz, 10 MHz, 12.5 MHz in the case of FIG. 6). The signal intensity peak is not displayed.

  Therefore, in the case of the example in FIG. 11, it is easily determined that one of the signal sources (for example, the PLL 201 to the PLL 203) has failed at least inside the semiconductor circuit 101 based on the signal strength displayed on the display unit 152. can do.

  As described above, according to the semiconductor circuit inspection system 81 in FIG. 4, the number of test terminals used when inspecting a plurality of signals of the semiconductor circuit 101 is set to one without compressing or expanding the signals. And a plurality of signals can be examined simultaneously. Therefore, it can be easily inspected in a short time which signal source is malfunctioning in the semiconductor circuit 101, and the inspection time for inspecting the signal source in the semiconductor circuit 101 can be shortened. .

  In the first to third display examples in FIGS. 7, 9, and 11, only the signal intensity in the analysis result in FIG. 6 is displayed, but all the analysis results in FIG. 6 are displayed. It may be. As a result, even in the example of FIG. 11, it is possible to easily inspect which signal source is a failed signal source in the semiconductor circuit 101.

  In the semiconductor circuit inspection system 81 of FIG. 4, the number of test terminals used in the inspection of a plurality of signals inside the semiconductor circuit 101 is one regardless of the number of signal sources inside the semiconductor circuit 101. Therefore, the circuit configuration of the semiconductor circuit inspection system 81 can be further simplified.

  Further, the signals 111 to 113 output from the PLL 201 to the PLL 203 are appropriately selected, and the detection operation is not performed in a time division manner, and the processing is performed at the same time, so that quick processing is possible.

  In the case of logical sum operation, the superposition principle of Fourier transform does not hold, so the result obtained by Fourier transformation does not strictly correspond to the frequency component of the original signal, but practically, Can be treated as corresponding.

  FIG. 12 shows another configuration of the semiconductor circuit inspection 101 to which the present invention is applied. In this example, the signal arithmetic unit 191 is configured by an adder circuit 261.

  The adder circuit 261 is a full adder, and adds the signals 111 to 113 (1-bit digital signals respectively) supplied from the PLL 201 to the PLL 203 to generate a 2-bit signal 221 to generate the lower 1-bit signal. The signal 221-1 and the upper one-bit signal 221-2 are supplied to the terminal 241-1 and the terminal 241-2, respectively. The terminals 241-1 and 241-2 output the signals 221-1 and 221-2 supplied from the adder circuit 261 to the signal analysis unit 151, respectively.

  Next, the semiconductor circuit inspection process of the semiconductor circuit inspection system 81 of FIG. 12 will be described with reference to the flowchart of FIG. The processing in steps S21 to S25 in FIG. 13 is basically the same as the processing in steps S1 to S5 in FIG. 5, and the calculation processing method in step S22 is different from that in step S2.

  That is, in step S21, the PLL 201 to the PLL 203 generate the signals 111 to 113, respectively, and supply them to the adding circuit 261. In step S <b> 22, the addition circuit 261 fully adds the signals 111 to 113 supplied from the PLL 201 to PLL 203.

  As illustrated in FIG. 14, the logical values of the signals 111 to 113 supplied from the PLL 201 to the PLL 203 to the adding circuit 261 are 1-bit values represented by “1” or “0”. As a result, the value of the addition operation of the addition circuit 261 is 2 bits. For example, as shown in the first row, when the logical values of the signals 111 to 113 are “1”, “1”, and “1”, respectively, the addition result is “11” (decimal number). “3”). For example, as shown in the fifth row, when the logical values of the signals 111 to 113 are “0”, “1”, and “1”, respectively, the addition result is “10” (10 The decimal number is “2”).

  Further, for example, as shown in the sixth row, when the logical values of the signals 111 to 113 are “0”, “0”, and “1”, respectively, the addition result is “01” (10 The decimal number is "1"). For example, as shown in the seventh row, when the logical values of the signals 111 to 113 are “0”, “0”, and “0”, respectively, the addition result is “00” (10 The decimal number is “0”. In step S23, the low-order 1-bit signal 221-1 of the test signal 221 represented by these 2 bits is supplied to the terminal 241-1, and the high-order 1-bit signal 221-2 is supplied to the terminal 241-2. Is done.

  Accordingly, the number of test terminals of the semiconductor circuit 101 (terminal 241-1 and terminal 241-2 in the example of FIG. 12) is changed from the signal source inside the semiconductor circuit 101 (PLL 201 to FIG. 12 in the example of FIG. 12). The number of PLLs 203) can be the number of bits when expressed in 2 bits. In the case of the example of FIG. 12, the number of the PLL 201 to the PLL 203 as the signal source is three (“11” in 2-bit representation), so two (1 in the case of the example of FIG. 12, the terminal 241). -1 and terminal 241-2).

  That is, when the number n of PLLs is 3 or more, the number of terminals can be reduced.

  Other processes are the same as those in FIG.

  FIG. 15 shows a display example of the display unit 152 in step S25.

  In the display example of FIG. 15, for example, significant signal intensity peaks are displayed at frequencies of 8.33 MHz, 10 MHz, and 12.5 MHz. Therefore, the frequencies of the signals 111 to 113 output from the PLL 201 to the PLL 203 can be specified as 12.5 MHz, 10 MHz, and 8.33 MHz, respectively.

  As shown in FIG. 15, the frequency component displayed on the display unit 152 includes a signal 1 generated by the PLL 201 to PLL 203 as compared with the display unit 152 when the semiconductor circuit system 81 of FIG. 4 is applied. Those having frequencies other than 1 to 32.5, 12.5 MHz, 10 MHz, and 8.33 MHz are not included so much. This is because the linearity of the signals 1 to 3 supplied from the PLL 201 to the PLL 203 to the OR circuit 221 is held by the adding circuit 261.

  As described above, according to the semiconductor circuit inspection system 81 of FIG. 12, the number of test terminals used when inspecting a plurality of signals of the semiconductor circuit 101 is reduced without compressing or expanding the signals. And multiple signals can be examined simultaneously. Therefore, it can be easily inspected in a short time which signal source is malfunctioning in the semiconductor circuit 101, and the inspection time for inspecting the signal source in the semiconductor circuit 101 can be shortened. .

  Further, in the semiconductor circuit inspection system 81 of FIG. 12, the frequency components displayed on the display unit 152 are unlikely to include frequencies other than those inherent to the signal source (that is, the PLL 201 to the PLL 203), so the semiconductor circuit of FIG. Compared with the inspection system 81, it is possible to inspect which signal source has failed in the semiconductor circuit 101 with higher accuracy.

  In the embodiment of the present invention, the PLL 201 to the PLL 203 are used as signal sources for generating digital signals, but a signal source for generating analog signals may be used. In the embodiment of the present invention, the signal calculation unit 132 is provided inside the semiconductor circuit 101 and the signal analysis device 151 is provided outside the semiconductor circuit 101. However, the signal calculation unit 132 and the signal analysis device 151 are provided. Both may be provided inside the semiconductor circuit 101.

  In addition, by applying the present invention, it is possible to immediately know how many of the plurality of signal sources in the semiconductor circuit have failed, so there is no need to further check whether or not there is a failure during the burn-in test, The present invention is effective as a monitor signal.

  Furthermore, the present invention is not limited to a semiconductor circuit, and can be applied to various types of inspected devices that cannot be directly accessed from the outside.

  The semiconductor circuit inspection system 81 can be configured by, for example, a personal computer as shown in FIG.

  In FIG. 16, the CPU 301 executes various processes according to a program stored in the ROM 302 or a program loaded from the storage unit 308 to the RAM 303. The RAM 303 also appropriately stores data necessary for the CPU 301 to execute various processes.

  The CPU 301, ROM 302, and RAM 303 are connected to each other via a bus 304. An input / output interface 305 is also connected to the bus 304.

  The input / output interface 305 includes an input unit 306 including a keyboard and a mouse, a display including a CRT and an LCD, an output unit 307 including a speaker, a storage unit 308 including a hard disk, a modem, a terminal adapter, and the like. A configured communication unit 309 is connected. The communication unit 309 performs communication processing via a network including the Internet (not shown) in addition to communication with the semiconductor circuit 101.

  A drive 310 is connected to the input / output interface 305 as necessary, and a magnetic disk 321, an optical disk 322, a magneto-optical disk 323, or a semiconductor memory 324 is appropriately mounted, and a computer program read from these is loaded. It is installed in the storage unit 328 as necessary.

  As shown in FIG. 16, a program storage medium that stores a program that is installed in a computer and can be executed by the computer includes a magnetic disk 321 (including a floppy disk), an optical disk 322 (CD-ROM (Compact Disk -Read Only Memory) (including DVD (Digital Versatile Disk)), magneto-optical disk 323 (including MD (Mini-Disk)), or semiconductor media 324 package media, or programs are temporary or permanent ROM 302 stored in the hard disk, a hard disk constituting the storage unit 308, and the like. The program is stored in the program storage medium using a wired or wireless communication medium such as a local area network, the Internet, or digital satellite broadcasting via an interface such as a router or a modem as necessary.

  In the present specification, the step of describing the program stored in the program storage medium is not limited to the processing performed in time series according to the described order, but is not necessarily performed in time series. Or the process performed separately is also included.

It is a block diagram which shows the structural example of the conventional semiconductor circuit test | inspection system. It is a block diagram which shows the other structural example of the conventional semiconductor circuit test | inspection system. It is a block diagram which shows the structural example of the semiconductor circuit test | inspection system to which this invention is applied. It is a block diagram which shows the structural example of the semiconductor circuit test | inspection system to which this invention is applied. 5 is a flowchart for explaining a semiconductor circuit inspection process in the semiconductor circuit inspection system of FIG. 4. It is a figure which shows the example of the analysis result in the signal analysis part of FIG. It is a figure which shows the example of a display of the analysis result displayed on the display part of FIG. It is a figure which shows the example of the logical value which the signal input / output to OR circuit has. It is a figure which shows the example of a display of the analysis result displayed on the display part of FIG. It is a figure which shows the other example of the logical value which the signal input / output to OR circuit has. It is a figure which shows the example of a display of the analysis result displayed on the display part of FIG. It is a block diagram which shows the structural example of the semiconductor circuit test | inspection system to which this invention is applied. 13 is a flowchart for explaining a semiconductor circuit inspection process in the semiconductor circuit inspection system of FIG. It is a figure which shows the example of the analysis result in the signal analysis part of FIG. It is a figure which shows the example of a display of the analysis result displayed on the display part of FIG. And FIG. 16 is a block diagram illustrating a configuration example of a personal computer.

Explanation of symbols

81 semiconductor circuit inspection system, 101 semiconductor circuit, 102 signal inspection device, 131 signal generation unit, 132 signal operation unit, 141 terminal, 151 signal analysis unit, 152 display unit, 171 to 173 signal source, 191 signal operation device, 201 to 203 PLL, 221 OR circuit, 241-1 terminal, 241-2 terminal, 261 adder circuit

Claims (9)

In an inspection system comprising an inspected apparatus and an inspection apparatus for inspecting the inspected apparatus,
The inspected device is:
Generating means for generating two or more first signals;
Computing means for computing two or more of the first signals generated by the generating means to generate a smaller number of second signals;
Output means for outputting the second signal generated by the computing means to the inspection device,
The inspection device includes:
Analyzing means for analyzing the second signal output by the output means;
An inspection system comprising: display means for displaying an analysis result by the analysis means. The generating means generates the second signal by calculating a logical sum of two or more of the first signals, or adding two or more of the first signals. The inspection system according to claim 1. The inspection system according to claim 1, wherein the analysis unit analyzes the second signal using discrete Fourier transform. The signal processing system according to claim 1, wherein the analysis unit analyzes a frequency component of the first signal. The signal processing system according to claim 1, wherein the generation unit includes a PLL. In an inspection method of an inspection system comprising an inspected device and an inspection device for inspecting the inspected device
The inspected device is:
Generating steps for generating two or more first signals;
A calculation step of calculating two or more first signals generated by the processing of the generation step to generate a smaller number of second signals;
An output step of outputting the second signal generated by the processing of the calculation step to the inspection device;
The inspection device includes:
An analysis step of analyzing the second signal output by the processing of the output step;
A display step for displaying an analysis result obtained by the analysis step. Generating means for generating two or more first signals;
Computing means for computing two or more of the first signals to generate a smaller number of second signals for inspection;
A signal processing apparatus comprising: the output means that outputs the second signal for inspection generated by the arithmetic means to the outside, and has a smaller number of output means than the first signal. The signal processing apparatus according to claim 7, further comprising an analysis unit configured to analyze the second signal. In the signal processing method of the signal processing device,
Generating two or more first signals;
Calculating two or more said first signals to produce a smaller number of second signals for inspection;
The generated second signal for inspection is output to the inspection device from a smaller number of output terminals than the first signal.

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