JP2005094562A - Code data decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To flexibly deal with a change in a way of assigning codes while suppressing circuit scale small in a variable length code data decoder. <P>SOLUTION: LUTs 302, 304, 306 for storing decoding table information are composed of RAMs. The LUT 302 stores information for decoding code data shorter than m1. The LUT 304 stores information for decoding code data wherein the same bit continuously appears more than m2 in the top. The LUT 306 stores information for decoding the remaining codes which do not match the conditions of the LUTs 302, 304. A shift circuit 326 is provided to shift code data D3 just for m3 as many as the number of the same bit data continuously appearing in the top commonly for all codes to be decoded by the LUT 306. A shift quantity corresponding to the change in the way of assigning codes is adjusted on the basis of setting of a register part 316. A decision part 340 and a selective output part 360 selectively output appropriate one corresponding to a code length from results of decoding referring to the LUTs. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an apparatus for decoding code data. More specifically, the present invention relates to a technique for decoding with reference to table information stored in a rewritable storage medium such as a Huffman code.

  Data compression / decompression and data encoding / decoding techniques are widely used to increase data transmission speed and data storage efficiency. There are various techniques for such data compression / decompression and data encoding / decoding techniques, and a variable-length encoding system such as a Huffman code is generally used. For example, the JPEG (Joint Photographic Experts Group) system, which is well known as an image encoding system, is a system that combines Huffman encoding, DCT (discrete cosine transform), and quantization.

  In the variable-length encoding method, when encoding, code data is created by assigning a variable-length bit string as a code to the original information and packing the variable-length bit string without gaps. For example, if a bit string of a code is assigned such as 10 for information a, 110 for information b, 1110 for information c, the code data for the original information abac is 10110101110. In order to restore (decode) the original information from the code data obtained in this way, it is necessary to determine the break of each code from the code data and obtain the corresponding original information from each code.

  As a conventional example for decoding such a variable length code, there is known a method of decoding a variable length code in one clock cycle regardless of the length of the code length. Specifically, a so-called table look-up method is known in which a decoding table of variable-length code data is configured with a memory element, and decoding data corresponding to input data is read with reference to the decoding table. For example, there are decoding systems disclosed in Patent Document 1, Patent Document 2, and the like.

JP-A-5-63586 JP-A-8-167855

  Moreover, as a mounting method of a decoding device used in a decoding system, there are those disclosed in Patent Documents 3 to 5 in addition to Patent Document 1 and Patent Document 2.

Japanese Patent Laid-Open No. 4-133522 JP-A-4-90267 JP-A-8-316847

  For example, FIG. 3 of Patent Document 2 discloses an example in which the decoding device is mounted with a decoding table on one surface of ROM or RAM. Hereinafter, this example is referred to as Conventional Example 1.

  Further, FIGS. 4 and 5 of Patent Document 2 disclose an example in which a decoding device is implemented by a combinational logic circuit. Hereinafter, this example is referred to as Conventional Example 2.

  Further, FIG. 2 of Patent Document 3 and FIG. 1 of Patent Document 4 disclose examples in which the decoding device is implemented by a plurality of small-scale ROMs. Hereinafter, this example is referred to as Conventional Example 3.

  Furthermore, FIG. 1 of Patent Document 5 discloses an example in which three decoding tables are used when code assignment is fixed. Hereinafter, this example is referred to as Conventional Example 4.

  Moreover, in FIG. 11 of patent document 5, the example in the case of mounting with nine decoding tables is disclosed when code allocation is arbitrary. Hereinafter, this example is referred to as Conventional Example 5.

  However, the techniques described in the conventional examples 1 to 5 are not necessarily in a well-balanced state in terms of dealing with changes in the code allocation method, and in terms of memory capacity and memory utilization efficiency (resulting circuit scale). It is not.

  For example, when the decoding device is configured with a decoding table of one ROM or RAM as in Conventional Example 1, it is necessary to input addresses for the maximum number of bits of the code bit string, and a huge ROM or RAM is required. For example, in order to decode a variable length code with code allocation often used in JPEG (see FIGS. 5 and 6 described later), ROM or RAM address input requires 16 bits, and the capacity of ROM or RAM is 65536 words.

  That is, if the RAM is used, it is possible to cope with a change in the code allocation method, but the memory capacity increases. On the other hand, if the ROM is used, it is not possible to cope with a change in the code allocation method, and the memory capacity increases. This is because, if the code assignment method is arbitrarily switched, the change cannot be made unless the ROM supports it. In order to cope with various allocation methods, a corresponding number (variation) of ROMs is required, so that a larger memory capacity is required.

  Further, in the first conventional example, when decoding a short code such as 00, a constant decoding result must be obtained regardless of what the subsequent bit string is, so the addresses “00 00... 00” to “00” 11 ... 11 ", it is necessary to store completely the same information, and most of the memory area is spent storing similar information. bad.

  In other words, for variable length codes that are less than the longest code length, the same data must be stored redundantly for all invalid code patterns except for the portion corresponding to the upper variable length code, and the corresponding memory. Space is wasted. This is not limited to the case where the ROM is used, and the same applies to the case where the RAM is used to cope with the change in the code allocation method.

  In addition, when the decoding device is implemented by a combinational logic circuit having an input / output relationship equivalent to that of ROM or RAM as in Conventional Example 2, the circuit scale can be reduced, but the code allocation method has been changed. Sometimes it becomes difficult to respond. For example, in the JPEG standard document, an example of how to assign codes (see FIG. 5 described later) is shown. However, it is not always necessary to follow this, and codes can be assigned freely when creating code data. You may decide to.

  When a decoding device for a combinational logic circuit is mounted on an ASIC (Application Specific IC) or an FPGA (Filed Programmable Gate Alley: Field Programmable Gate Array), the ASIC can be used to support code data with different code assignments. Reworking or rewriting of FPGA circuit data is required, which is substantially impossible.

  Further, in Conventional Example 3, the decoding device is implemented by one ROM that inputs the upper side of the code data and a plurality of ROMs that input the lower side of the code data, and basically uses a ROM. Therefore, like the conventional example 2, there is a drawback that when the code assignment is changed, it cannot be flexibly handled. In addition, replacing the ROM with RAM in this configuration can be considered to flexibly cope with changes in code assignment, but in practice, how many RAMs on the lower side are required depends on how the codes are assigned. If the number of RAMs is determined and mounted, a case that cannot be handled occurs.

  In Conventional Example 4 and Conventional Example 5, each variable length code is associated with each decoding code bit group obtained by removing the common bit part from all code bits for each code group (each code bit length). Since a plurality of decoding tables that hold fixed-length data corresponding to are provided, the number of decoding tables increases.

  Further, in the conventional example 4, the input bits are divided and inputted to the three decoding tables. However, since this division method is fixed by circuit implementation, it may not be possible to cope with changes in the code allocation method. .

  Further, in the conventional example 5, in the decoding table for a code having a long bit length, the fixed number of bits at the head of the code is ignored, so there are cases where it cannot be handled if the code allocation method is changed.

  Further, in the conventional example 4 and the conventional example 5, the selection circuit for selecting one of the outputs of the plurality of decoding tables makes the determination based on the code length, so that the circuit configuration becomes complicated. If the code length is not output from the table, it cannot be determined that the operation speed of the circuit is reduced.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a decoding apparatus that can flexibly cope with a change in the code allocation method while keeping the circuit small.

  A decoding device for decoding code data according to the present invention first stores rewritable information for decoding code data having a plurality of code lengths shorter than a predetermined number of bits, among sequentially input code data. Decoding information storage unit for short bit code data having a storage device, and decoding among code data that is sequentially input, in which the same bit data is continued for a predetermined number of bits in common in the code data A decoding information storage unit for continuous bit code data having a rewritable storage device for storing the information, and information regarding the predetermined number of bits for the code data to be processed by the decoding information storage unit for continuous bit code data A continuous bit number storage unit having a rewritable storage device to be stored, and each storage unit according to a code allocation method of sequentially input code data It was assumed and a storage information update unit that makes rewriting the information to be stored.

  Furthermore, the decoding device according to the present invention includes a determination unit that determines which of the decoding results output from the decoding information storage unit for short bit code data and the decoding information storage unit for continuous bit code data is to be selected; A selection output unit that selects and outputs one of the decoding results output from the decoding information storage unit for short bit code data and the decoding information storage unit for continuous bit code data based on the determination result of the unit did.

  The invention described in the dependent claims defines a further advantageous specific example of the decoding device according to the present invention.

  For example, the decoding information storage unit for continuous bit code data may be configured to include a plurality of types of decoding information storage units for continuous bit code data corresponding to different predetermined numbers of bits. In this case, the effective portion of the code data to be processed by each decoding information storage unit for continuous bit code data is unchanged even if the code allocation method is changed for one, and the other depends on the code allocation method. It is also possible to adopt a configuration that is variable, or a configuration that is variable depending on how the codes are allocated.

  Further, the decoding information storage unit for continuous bit code data may include a single decoding information storage unit for continuous bit code data. In this case, the effective portion of the code data to be processed by the decoding information storage unit for continuous bit code data can be configured to be unchanged even if the code allocation method is changed. It is also possible to adopt a configuration that is variable according to the above.

  When the decoding information storage unit for the continuous bit code data is configured to be variable according to the code allocation method, the effective part extraction processing unit receives the code data sequentially input to the apparatus for a predetermined number of bits (in particular, Effective part by shifting the input code data by the number of consecutive identical bits appearing at the head of the code) common to all code data to be processed by the decoding information storage unit for continuous bit code data It is desirable to have a shift processing unit for extracting the code data.

  According to the decoding device of the present invention, the table information for decoding processing is implemented by a rewritable storage device such as a RAM. Therefore, when the code assignment is changed, the circuit configuration is changed. Even without this, it is possible to cope by rewriting the table information.

  In addition, as each storage unit for storing table information for decoding processing, a part for storing information for decoding code data having a plurality of code lengths shorter than a predetermined number of bits according to a code allocation method Other than this, the same bit data in the code data that is the same number of consecutive bits is handled separately as a processing target, so that the former storage unit stores the code in the decoding process. The upper bit side of the data is in charge, and the latter storage unit is in charge of the lower bit and intermediate bit of the code data. The determination circuit and the selection output unit select and output an appropriate one according to the code length from the decoding results referring to the storage units.

  As a result, it is not necessary to store the decoding information corresponding to each variable length code in each decoding table, and the capacity of the entire decoding table can be reduced. In addition, it is possible to prevent the memory space from being wasted, and the memory utilization efficiency can be improved, and the circuit scale can be reduced by configuring the memory with a plurality of small look-up tables. .

  As described above, according to the decoding apparatus of the present invention, it is possible to flexibly cope with a change in the method of assigning the code bit string while keeping the decoding table circuit small.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<System configuration>
FIG. 1 is a block diagram showing an outline of a decoding system to which a decoding apparatus according to the present invention is applied. The decoding system 1 includes a code input unit 10, a code cutout unit 20, a decoding processing unit 30, a code position management unit 40, and a decoding result output unit 50.

  The code input unit 10 includes a storage unit (not shown), and holds a plurality of bits in the process of the input code data D1 (the data is D2). At this time, the code input unit 10 sequentially fetches the next code data D1 based on timing information J3 input from a code position management unit 40 described later.

  The code cutout unit 20 cuts out a portion of the code data D2 held by the code input unit 10 that has not been decoded (the data is D3) and inputs the portion to the decoding processing unit 30.

  The decoding processing unit 30 performs a decoding process based on the code data D3 cut out by the code cutting unit 20, inputs the decoding result information J1 to the decoding result output unit 50, and code length information of the decoded code. J2 is input to the code position management unit 40.

The code position management unit 40 cumulatively adds the code length information J2 input from the decoding processing unit 30, determines the timing for fetching the next code data D1 into the code input unit 10, and inputs the timing information J3 as a code. The cut position of the next code data is determined and the cut position information J4 is fed back to the code cut section 20 while being input to the section 10.
On the other hand, the decoding result output unit 50 performs predetermined processing on the decoding result information J1 input from the code position management unit 40 as necessary to obtain decoding result information J5 (J1 may be left as it is if unnecessary). , Output to the subsequent circuit.

  The decoding system 1 can decode one code in one clock cycle by operating the entire system in synchronization with the clock signal. In this way, the code extraction unit 20 and the decoding processing unit 30 are provided, and one code is decoded in one clock cycle by accumulating the decoded code length information.

<First embodiment: first LUT (one) + second / third LUT (multiple; one is the same meaning as fixed shift amount → second LUT)>
FIG. 2 is a circuit block diagram showing a first embodiment of a decoding processing unit 30 which is an example of a decoding device according to the present invention. The first embodiment is a configuration example suitable for a case where the maximum length of the code data D3 is predetermined (that is, the maximum length is fixed).

  As shown in the figure, the decoding processing unit 30 of the first embodiment includes a memory unit 300 having a rewritable storage unit such as a RAM, and an effective portion of the code data D3 corresponding to the code allocation change. A shift amount adjustment processing unit 320 which is an example of an effective part extraction processing unit for appropriately adjusting the width, a determination unit 340 for determining which of a plurality of decoding results output from the memory unit 300 should be selected, A selection output unit 360 that selects and outputs a decoding result of one system output from the memory unit 300 based on a determination result of the determination unit 340, and rewrites information stored in the memory unit 300 according to a code allocation method And a stored information updating unit 380.

  The memory unit 300 takes in the code data D3 extracted by the code extraction unit 20 as code data D31 in order to decode code data shorter than a predetermined number of bits (m1), and decode result information J11 and code length information Decode first look-up table (hereinafter referred to as LUT) 302 that outputs J21, and code data in which a predetermined number or more of the same bits continuously appear at the beginning (upper bit side) of code data D3. A second LUT 304 that outputs J12 and code length information J22, and a third code that decodes the remaining codes that do not match the conditions of the first LUT 302 and the second LUT 304, and outputs decoding result information J13 and code length information J23 LUT 306 and a shift amount adjustment processing unit 320 corresponding to the third LUT 306 are provided.

  The first LUT 302 is an example of a decoding information storage unit for short bit code data. The second LUT 304 is an example of a first decoding information storage unit for continuous bit code data. The third LUT 306 is an example of a second decoding information storage unit for continuous bit code data.

  In the first LUT 302, information for decoding code data having a plurality of code lengths shorter than the predetermined number of bits m1 among code data sequentially input to the decoding system 1 is stored. Therefore, for example, if m1 = 8, the first LUT 302 stores decoding information for decoding all code data having a code length of 8 bits or less.

  The shift amount adjustment processing unit 320 shifts the input code data D3 by the number of consecutive identical bit data appearing at the head of the code common to all codes in the code decoded by the third LUT 306. have. Corresponding to this, the memory unit 300 includes a shift number register unit 316 for setting the shift number of the shift circuit 326.

  The shift number register unit 316 determines the shift amount for the input code data D3 based on the encoded sequence information of the code data D3, and inputs the shift amount information S13a representing the shift amount to the shift circuit 326. Similar shift amount information S13b is input to the determination unit 340.

  The shift circuit 326 is an example of a shift processing unit, and adjusts the shift amount of the code data D3 input from the code cutout unit 20 based on the shift amount information S13a input from the shift number register unit 316. By moving the code data D3 by a predetermined number of bits according to the shift amount, the head side substantially invalid data is swept away, and only the remaining valid part is extracted and is stored in the third LUT 306 as code data D33. input.

  Here, both the second LUT 304 and the third LUT 306 are intended to decode a code in which the data “1” is continuously higher than the code data and continues for a predetermined number of times. Performs the same kind of processing. However, in the first embodiment, this corresponds to the case where the maximum length of the code data D3 is fixed, and one of the two LUTs continues to the head (upper bit side) of the code data D3. It is possible to fix the “predetermined number” of the same bits that appear.

  Accordingly, the second LUT 304 corresponding to this is a code in which m2 or more (m2 is larger than m3 for the third LUT 306) appearing continuously at the head (upper bit side) of the code data D3. Information for decoding is stored, and the shift amount can be substantially fixed. Therefore, the upper bit side is permanently deleted without providing the shift amount adjustment processing unit 320 corresponding to the third LUT 306. This can be handled by taking in the data as code data D32.

  The LUTs 302, 304, and 306 store the input code data D31, D32, and D33, that is, the decoding information (decoding result information and code length information) corresponding to the code data D3 that is responsible for the decoding process, respectively. . In this way, the effective part corresponding to the code length that each LUT is responsible for decoding is extracted from the code data D3 input to each, and the corresponding decoding result is obtained by referring to each LUT using this effective part as an address. Information and code length information can be read.

  In the configuration of the first embodiment, only the third LUT 306 is configured so that the shift amount can be adjusted by the shift amount adjustment processing unit 320. This is because the first LUT 302 always has the upper m1 bit set. This is because the shift amount of the second LUT 304 may be fixed to m2 in a fixed manner. Correspondingly, in the memory unit 300, the effective upper bit number register unit 312 for setting m1 information corresponding to the first LUT 302 and the shift number register for setting m2 information corresponding to the second LUT 304 are stored. Part 314.

  The valid high-order bit number register unit 312 inputs valid high-order bit information S11b representing m1 corresponding to the first LUT 302 to the determination unit 340. Further, the shift number register unit 314 inputs shift amount information S12b representing m2 corresponding to the second LUT 302 to the determination unit 340.

  The determination unit 340 determines the number of consecutive identical bits that appear at the beginning of the input code data, that is, the run length when the same bits appear continuously at the beginning, so that any of the three LUTs 302, 304, and 306 can be determined. Determine whether output should be selected. Specifically, the number of consecutive identical bits appearing at the head of the code data D3 cut out by the code cutout unit 20 is determined, and the valid upper bit information S11b input from the valid upper bit number register unit 312; Referring to the shift amount information S12b input from the shift number register unit 314 and the shift amount information S13b input from the shift number register unit 316, which output of the three LUTs 302, 304, and 306 should be selected Determination is performed, and determination information S21 indicating the determination result is input to the selection output unit 360.

  As described above, in the configuration of the first embodiment, the shift amount adjustment processing unit 320 can adjust the shift amount only for the third LUT 306. It is necessary to refer to at least the shift amount information S13b among S11b, S12b, and S13b in order to cope with the change in allocation method. However, for the remaining S11b and S12b, the information is set in the determination unit 340 in advance. It can also be handled by (fixed handling).

  The selection output unit 360, based on the determination information S21 input from the determination unit 340, any one of the decoding result information J11, J12, J13 output from the three LUTs 302, 304, 306 and the corresponding code length information Any one of J21, J22, and J23 is selected and output.

  The stored information update unit 380, for example, based on the information indicating the code allocation method included in the code data D1 input to the decoding system 1, each LUT 302, 304, 306 of the memory unit 300, and the valid upper bits Information stored in the number register unit 312, the shift number register unit 314, and the shift number register unit 316 is rewritten. The code data D1 does not directly include information indicating how to allocate the code, and the code data D1 describes a corresponding code, and information indicating the code allocation from other means with reference to the corresponding code The configuration may be such that Moreover, the structure which acquires the information which shows how to allocate a code | symbol separately from code data D1 may be sufficient.

  With such a configuration, the decoding processing unit 30 of the first embodiment presets the contents of the three LUTs and the number of input shifts of the third LUT 306 in accordance with how the variable length codes are allocated. The decoding result J11, J12, output from each LUT by inputting the upper bits of the code data D3 to the first LUT 302, the lower bits to the second LUT 304, and the intermediate bits to the third LUT 306, respectively. By selecting and outputting any one of J13, decoding is possible even when the variable length code allocation method is changed. Hereinafter, this point will be described in detail.

  3 and 4 are tables showing basic examples of code allocation methods. In the decoding processing unit 30 of the first embodiment, it is assumed that the maximum length of the code data D3 is predetermined (that is, the maximum length is fixed), and even if the code allocation method changes, It is assumed that the maximum length of the code data is limited to M bits. In addition, among codes, a first type code with a short number of bits (here, code length m1; m1 <M) and codes up to a maximum length M (code length is m1 + 1 to M) are included. It can be divided roughly. Further, a code having a code length of m1 + 1 to M is further a second type code in which at least m2 bits at the head (upper bit side) of the code are all “1” (that is, m2 or more consecutively), It can be divided into other types of codes.

  The RAM 1 for the first LUT 302 is used to decode a first type code having a code length of m1 bits or less. The RAM 2 for the second LUT 304 has a code length of m1 + 1 to M bits and is used for decoding the second type code. The RAM 3 for the third LUT 306 has a code length of m1 + 1 to M bits and is used for decoding the third type code. Since the RAM 2 for the second LUT 304 is used to decode the second type code, the bit width to be supported may be M-m2.

  On the other hand, since the RAM 3 for the third LUT 306 is used for decoding the third type code, the corresponding bit width is M (M bit code at the beginning of the code and m2 bits). There is no “1”), and the minimum is 1. Therefore, if it is intended to deal with all the code allocation methods, the bit width to be supported by the RAM 3 for the third LUT 306 is M bits.

  However, depending on the encoding method, for example, an M-bit code is assigned to a large number of pieces of information with low appearance frequency, and the number of consecutive “1” s on the leading side increases as the code length increases. Furthermore, among the codes of m1 + 1 bit to M bits, at least m3 bits at the head (upper bit side) of the code are all set to “1” (that is, m3 or more and less than m2 are consecutive). Can do. In the case of such an encoding method, the bit width to be supported by the RAM 3 for the third LUT 306 is smaller than M bits and may be M-m3 to M bits, and in some cases, it may be about M-m2. Get better.

  Therefore, in the present embodiment, M-m2 is set as the bit width to which the RAM 3 for the third LUT 306 should correspond, and the bit length is m1 + 1 to M and the second type is set in the RAM 3 for the third LUT 306. Among the codes to be excluded, information for decoding a code in which the first m3 bits of the code are continuous is set. Correspondingly, the shift number register unit 316 adjusts the shift amount for m3 bits, and only the lower side (for 1 to M−m3 bits) except the upper m3 bits is included in the third LUT 306. To be entered. The third LUT 306 can reliably decode a code in which m3 + 1 bits on the head side are continuous among codes of m1 + 1 to M bits, but cannot decode a code in which the first m3 bits in the code are not continuous.

  Therefore, when assigning codes, it is essential not to assign codes that do not have consecutive m3 bits at the beginning for m1 + 1 to M-bit codes. In this way, even when the code allocation method changes, all codes can be decoded without fail as long as the above-described conditions are satisfied.

  For example, as shown in FIG. 3 and FIG. 4, the first type codes whose code length (bit length of the code data) is up to m1 bits are all input to the first LUT 302 and decoded by the first LUT 302. It becomes the object of processing. Of the codes having a code length of m1 + 1 to M bits, the second type code in which m2 or more of data “1” continues on the upper side is only the lower bits from which the upper m2 bits are deleted ( (Substantially equivalent to a shift of m2 bits) is input to the second LUT 304 and becomes a target of decoding processing by the second LUT 304.

  Also, the third type code excluding the second type code among the code lengths m1 + 1 to M is the upper m3a bits (in the case of code allocation in FIG. 3) or the upper m3b bits (in FIG. 4). In the case of allocation), only the lower-order bits deleted by the shift circuit 326 are input to the third LUT 304, and are subject to decoding processing by the third LUT 306.

  By adopting such a circuit configuration, various code lengths and variable length codes with code assignment can be decoded by changing the contents of the LUT and the setting of the shift number register unit 316 even if the code assignment method changes. be able to. For example, as long as the relationship of m1, m2, m3a, M or m1, m2, m3b, M can be maintained, it is possible to cope with the same shift amount setting by the shift number register unit 316.

  When m3 is changed from m3a to m3b, the shift circuit 326 only has to be rewritten from m3a to m3b the information to be stored in each LUT 302, 304, 306 and the register value for the shift number register unit 316. Since the shift amount can be adjusted based on the shift amount information S13a from the shift number register unit 316, it is possible to cope with a change in code assignment with the same circuit configuration (that is, without changing the circuit).

  Next, a specific description will be given of a case where a JPEG Huffman code is decoded as encoded data.

  5 and 6 are examples of Huffman code allocation tables based on the JPEG standard. Here, the allocation table of the first example shown in FIG. 5 is an allocation table of Huffman codes for AC components described as an example in the JPEG standard. In JPEG, the type of information to which a code should be assigned is “162”, and the maximum bit length M (maximum length of code data) of code data is limited to “16”. Therefore, as shown in FIG. 5, a short code is assigned to information with a high appearance frequency, and a 16-bit code tends to be assigned to a large number of information with a low appearance frequency.

  Further, in a code having a long code length, a large number of “1” s appear continuously in the head portion from the upper side of the code, and the number of consecutive “1” s tends to increase as the code length increases. Although it is allowed to change the code allocation method depending on the nature of the image, this tendency does not change even if the allocation method is changed due to the above-mentioned limitations.

  Therefore, in the decoding processing unit 30 of the first embodiment shown in FIG. 2, the code bit string of the input code data D3 is 16 bits, which is the maximum value of the code length. This input code bit string is obtained by cutting out 16 bits at a time by the code cutting unit 20 of the decoding system 1 shown in FIG. 1 and inputting the data as code data D3 to the decoding processing unit 30. Correspondingly, as shown in FIG. 2, three lookup tables LUTs 302, 304, and 306 are provided, and each is implemented by an 8-bit input RAM.

  For example, since the first LUT 302 takes in the upper m1 (= 8) bits of the 16-bit code data D3, the RAM 1 for the first LUT 302 decodes a code having a code length of 8 bits or less. Set the information. Specifically, the decoding information of the code in the range 1 shown in FIG.

  Further, since the second LUT 304 takes in the lower (= 8) bits excluding the upper m2 (= 8) bits in the code data D3 having the maximum length M (= 16) bits, it is stored in the RAM 2 for the second LUT 304. Sets information for decoding a code in which the first 8 bits (upper bit side) of the code are all “1”. Specifically, the decoding information of the code in the range 2 shown in FIG.

  In addition, since the third LUT 306 takes in a code (called intermediate bit data) D33 that cannot be decoded by the first LUT 302 and the second LUT 304, the RAM 3 for the third LUT 306 stores the first LUT 302 and the second LUT 306. Information for decoding a code that cannot be decoded by the LUT 304 is set. Specifically, the decoding information of the code in the range 3 shown in FIG.

  Here, since all the m3a (= 5) bits at the beginning of the code of the code in range 3 are “1”, “5” is set in the shift number register, and the intermediate bit data input to the RAM 3 is the code bit string. The first 5 bits are deleted and the 6th bit and subsequent 8 bits are used. Correspondingly, the shift number register unit 316 adjusts the shift amount for 5 bits, and only the lower side except the upper 5 bits is input to the third LUT 306.

  Here, “8 bits after the 6th bit” is set to 8 bits as an intermediate bit that is a code that cannot be decoded by the first LUT 302 and the second LUT 304 in accordance with the code allocation method permitted in the JPEG format. This is because, if the degree is assigned, even if the code assignment method changes, it is considered that almost all assignment methods can be handled.

  The determination unit 340 selects the output of the RAM 2, that is, the second LUT 304 if at least the first 8 (= m2) bits of the code bit string are all “1” for the code data D30 extracted by the code extraction unit 20. The determination information S21 for switching the selection output unit 360 is output.

  Further, the determination unit 340, based on the shift amount information S13b, continues with “1” as many as the number (= m3) set in the shift number register unit 316 at least at the beginning of the code bit string when the above condition is not satisfied. If it appears, determination information S21 for switching the selection output unit 360 so as to select the output of the RAM 3, that is, the third LUT 306 is output. Finally, when the above two conditions are not satisfied, the determination unit 340 outputs determination information S21 for switching the selection output unit 360 so as to select the output of the RAM 1, that is, the first LUT 302.

  The selection output unit 360 outputs one of the three outputs of the first, second, and third LUTs 302, 304, and 306, that is, RAM1, RAM2, and RAM3, according to the determination information S21 input from the determination unit 340. Select and output.

  The selection output unit 360 outputs the decoding result information J1 out of the decoding result output to the subsequent circuit via the decoding result output unit 50 shown in FIG. 1, and inputs the code length information J2 to the code position management unit 40. To do.

  Next, a case where the code allocation method is changed from the allocation table of the first example shown in FIG. 5 to the allocation table of the second example shown in FIG. 6 will be described. Similar to the allocation table of the first example shown in FIG. 5, the allocation table of the second example shown in FIG. 6 follows that the maximum length M of the code data is “16”, and is short for information with high appearance frequency. A code is assigned and a 16-bit code is assigned to a large number of pieces of information with low appearance frequency. In a code with a long code length, a number of “1” s appear continuously from the upper part of the code. The number of consecutive “1” s tends to increase as the length increases.

  Here, as can be seen by comparing the allocation table of the first example shown in FIG. 5 and the allocation table of the second example shown in FIG. 6, the code is first of the first type whose number of bits is shorter than m1 (= 8). A code (both are indicated by range 1) and a code (code length is 9 to 16 bits) up to the maximum length M (= 16), and at least m2 (= higher bit side) of the code 8) All bits (that is, 8 or more consecutively) are divided into a second type code (both indicated by a range 1) which is “1”.

  Further, in the allocation table of the first example shown in FIG. 5, the remaining codes of 9 bits to 16 bits are all at least m3a (= 5) bits at the beginning (upper bit side) of the codes (that is, 8 or more 8 bits). On the other hand, in the allocation table of the second example shown in FIG. 6, at least m3b (= 3) bits at the beginning (upper bit side) of the code are all present. (That is, 3 or more and less than 8 consecutively) becomes “1” (indicated by range 3).

  Therefore, when the code allocation method is changed from the allocation table of the first example shown in FIG. 5 to the allocation table of the second example shown in FIG. 6, information to be stored in each LUT 302, 304, 306 and shift The register value for the number register unit 316 (indicating the shift amount corresponding to m3 derived from the code assignment table) is rewritten from m3a to m3b, and the shift circuit 326 shifts based on the shift amount information S13a from the shift number register unit 316. Adjust the amount. This makes it possible to change the code assignment from the assignment table of the first example shown in FIG. 5 to the assignment table of the second example shown in FIG. 6 with the same circuit configuration shown in FIG. 2 without recreating the circuit. Can respond.

  In addition, by mounting the lookup table with a rewritable storage means such as a RAM, it is possible to cope with rewriting the table without changing the circuit configuration when the code assignment is changed, and the decoding table. Can be composed of a plurality of small look-up tables, and the circuit scale can be kept small.

<Second Embodiment: First LUT (1) + Third LUT (Plural; Both are Variable in Shift Amount)>
FIG. 7 is a circuit block diagram showing a second embodiment of the decoding processing unit 30. The second embodiment is a configuration example suitable for the case where the maximum length M of the code data D3 is not fixed. As described in the first embodiment, each of the second LUT and the third LUT uses a code in which the data “1” is continuously higher than the code data as a target for decoding processing. Therefore, the same kind of processing is performed essentially, but when the maximum length M of the code data D3 is fixed, the shift amount can be fixed for one of the two LUTs. On the other hand, if the maximum length M of the code data D3 is not fixed, the shift amount cannot be fixed in both cases. Therefore, in the second embodiment, the second LUT is substantially removed, 3 LUTs and two shift circuits corresponding to the three LUTs. This will be specifically described below.

  As shown in the drawing, in the decoding processing unit 30 of the second embodiment, the memory unit 300 uses a code shorter than a predetermined number of bits (= m1) for the code data D3 extracted by the code extraction unit 20. For the first LUT 302 that captures as code data D31 for decoding and outputs decoding result information J11 and code length information J21, and for codes whose code length exceeds m1, the same bit is m3A at the head (upper bit side) of code data D3. For the third LUT 306A that decodes the codes that appear continuously and outputs the decoding result information J13A and the code length information J23A, and the code whose code length exceeds m1, the same bit at the head (upper bit side) of the code data D3 Decodes a code that continuously appears for m3B or more, and outputs decoding result information J13B and code length information J23B. And a UT306B.

  The shift amount adjustment processing unit 320 shifts the input code data by the number of consecutive identical bits (m3A) appearing at the head of the code common to all codes in the code decoded by the third LUT 306A. The second shift for shifting the input code data by the number of consecutive identical bits (m3B) appearing at the head of the code common to all codes in the code decoded by the shift circuit 326A and the third LUT 306B Circuit 326B. Corresponding to this, the memory unit 300 sets the shift number register unit 316A for setting the shift number (= m3A) of the shift circuit 326A and the shift number (= m3B, m3A <m3B) of the shift circuit 326B. A shift number register unit 316A.

  The shift number register unit 316A determines a shift amount with respect to the input code data D3 for the third LUT 306A based on the encoded sequence information of the code data D3, and uses the shift amount information S13aA representing this shift amount as a shift circuit. The same shift amount information S13bA is input to the determination unit 340 as well as to 326A. The shift number register unit 316B determines a shift amount with respect to the input code data D3 for the third LUT 306B based on the encoded sequence information of the code data D3, and uses the shift amount information S13aB representing this shift amount as a shift circuit. The same shift amount information S13bB is input to the determination unit 340 as well as to 326B.

  The circuit configuration such as the input bit width to each of the LUTs 302, 306A, and 306B is determined in consideration of the nature of code assignment, the situation of circuit mounting, and the like, as in the first embodiment.

  According to the configuration of the second embodiment, the second LUT 304 in the first embodiment is replaced with the third LUT 306B, and a shift circuit 326B corresponding to the second LUT 306B is provided. The position of the bit string input to 306B can be changed by the register setting by the shift number register units 316A and 316B and the corresponding shift circuits 326A and 326B. That is, the position of the bit string input to each LUT can be changed by register setting and the shift circuit. As a result, in addition to the case where the code allocation is changed, it is possible to cope with another type of variable length coding scheme in which the maximum code length is changed (for example, shorter than 16 bits). Hereinafter, this point will be described.

  FIG. 8 and FIG. 9 are tables showing basic examples of code allocation methods for explaining the effects of the second embodiment. The allocation table of the first example shown in FIG. 8 is the same as the allocation table of the first example shown in FIG. On the other hand, in the allocation table of the second example shown in FIG. 9, the maximum code length is changed from MA = 16 bits to MB = 15 bits. That is, when the code allocation method changes, the relationship of m1 can be maintained, but M cannot be maintained.

  Therefore, in this case, by switching m3A and m3B in conjunction with M, the register settings by the shift number register units 316A and 316B are changed by the corresponding shift circuits 326A and 326B, and the third LUT 306A, The position of the bit string input to 306B is switched.

  Thus, even if the maximum length is changed from MA to MB, the information to be stored in each LUT 302, 304, 306 and the register values m3A, m3B for the shift number register units 316A, 316B are changed to MA. As long as rewriting is performed in conjunction with MB, the shift circuits 326A and 326B can adjust the shift amount based on the shift amount information S13aA and S13aB from the shift number register units 316A and 316B.

  Thereby, it is possible to cope with a change to another type of variable-length encoding method in which the maximum code length is short without changing the circuit. On the other hand, even if the code length becomes longer, for example, “17” or “18”, the code length can be adjusted to some extent by adjusting the shift amount.

<Third embodiment: first LUT (one) + third LUT (one)>
FIG. 10 is a circuit block diagram showing a third embodiment of the decoding processing unit 30. The third embodiment is a modification of the configuration of the second embodiment that is suitable when the maximum length M of the code data D3 is not fixed, and is characterized in that it includes only one third LUT. As shown in the figure, the second LUT 304 is removed from the decoding processing unit 30 of the first embodiment.

  According to the configuration of the third embodiment, the maximum code length cannot be predicted in advance, although the flexibility for changing the code allocation method is reduced as compared with the configurations of the first and second embodiments. Even if it is a case, it can cope to some extent. For example, it is possible to cope with a change in which the value of M before the change is large, that is, the maximum code length is long.

<Fourth embodiment: first LUT (one) + second LUT (one)>
FIG. 11 is a circuit block diagram showing a fourth embodiment of the decoding processing unit 30. As shown in the figure, the fourth embodiment is characterized in that the third LUT 306 and the shift amount adjustment processing unit 320 are removed from the decoding processing unit 30 of the first embodiment. In the fourth embodiment, first, the first LUT 302 decodes a code having a certain bit length m1 or less, and the second LUT 304 decodes a code having the same bit length m2 at the beginning.

  The determination unit 340 determines which output of the two LUTs 302 and 304 should be selected based on the code data D3 extracted by the code extraction unit 20, and selectively outputs determination information S21 indicating the determination result. To the part 360. Specifically, the determination unit 340 selects the output of the RAM 2, that is, the second LUT 304 if the first m2 bits of the code bit string are all “1” for the code data D30 extracted by the code extraction unit 20. The determination information S21 for switching the selection output unit 360 is output. Further, the determination unit 340 outputs determination information S21 for switching the selection output unit 360 so as to select the output of the RAM 1, that is, the first LUT 302, when the above condition is not satisfied.

  The selection output unit 360 selects and outputs one of the two outputs of the RAMs 1 and 2 as the first and second LUTs 302 and 304 according to the determination information S21 input from the determination unit 340. According to such a configuration of the fourth embodiment, the circuit can be further simplified than the configuration of the first embodiment described above.

  Here, in order to correspond to the code allocation method shown in FIG. 5, if m2 = 8, m1 needs to be equal to or larger than the bit of range 2 (= 11). That is, since the third LUT 306 is removed, the code range handled by the first LUT 302 is expanded to range 3. That is, unlike the first to third embodiments, the bit width of the address input of the RAM 1 is not 8 bits. As a circuit configuration, a RAM corresponding to such a bit width is mounted in advance in view of this point.

  It should be noted that the code range handled by the second LUT 304 may be widened to the range 3 as opposed to widening the code range handled by the first LUT 302. However, in this case, the bit width of the address input of the RAM 2 is not 8 bits unlike the first to third embodiments, and in addition to the leading side of the code data D3 to be excluded by the second LUT 304 (first 3 is equivalent to the shift amount by the shift circuit 326 for the LUT 306).

  The configuration of the fourth embodiment is similar to the configuration shown in FIG. 5 (hereinafter referred to as prior art 1) of JP-A-8-167855. However, in the configuration of this prior art 1, the first two bits are input to the combinational logic circuit, the cases of “00”, “01”, “10” are decoded, the third and subsequent bits are input to the memory, The case of “11” is decoded. Assuming a certain code allocation method, a configuration that can be used only in that case is shown.

  In contrast, the configuration of the fourth embodiment can be adapted to m1 and m2 even when the code assignment changes. In other words, the configuration specialized for the case of m1 = m2 = 2 may be considered to be the configuration shown in the prior art 1. In this respect, there is a difference in configuration and operational effect between the configuration of the fourth embodiment that can be adapted according to m1 and m2, and the configuration of the prior art 1.

  The configuration of the fourth embodiment is similar to the configuration shown in FIG. 1 (hereinafter referred to as Conventional Technology 2) of JP-A-8-316847. In other words, the configuration of the conventional technique 2 is configured by three LUTs, and if one LUT is reduced, the configuration is similar to the configuration of the fourth embodiment. However, in the prior art 2, since one of the outputs from the plurality of tables is selected using the selection data output from the table, the circuit configuration is complicated, and the code length is determined from the table. There is a problem that it cannot be determined that it is not output and causes a reduction in operating speed.

  On the other hand, in the fourth embodiment, the selection data output from the table is not used, but the determination information S21 from the determination unit 340, that is, the code data D3 extracted by the code extraction unit 20 is obtained. Since one of the two outputs of RAM1 and RAM2 which are the first and second LUTs 302 and 304 is selected and output in accordance with the determination information S21, the determination is made because the configuration is simple and the code length is not output. The difference is that the problem of not being possible does not occur. Therefore, although the fourth embodiment and the prior art 2 are similar, there is a difference in configuration, operation, and effect.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the first to third embodiments, the case where the bit widths of the address inputs of RAM1, RAM2, and RAM3 are all 8 bits is taken as an example. However, in consideration of the nature of code assignment and the circumstances of circuit implementation, etc. It is also possible to implement by changing the bit width. The fourth embodiment is an example.

  Also, the bit width of the code bit string input to the decoding table is fixed by the circuit configuration of the code cutout unit 20, but it is possible to support various types of variable length codes as long as the number of bits is less than this number. It is.

  For example, in the example shown in FIG. 2, since the case of JPEG is taken as an example, the bit width of the input code bit string is set to “16”, and decoding is possible even when the JPEG code assignment is changed. In addition, other types of variable-length codes whose code maximum bit length is “16” or less can be dealt with without changing the circuit configuration by simply rewriting the set values of the RAM and the register.

  In the above-described embodiment, the decoding process for a variable length code such as a Huffman code adopted by the JPEG method has been described. However, the decoding process for an equal length code can also be applied. For example, in a variable-length code such as a Huffman code, code data having a short data length is assigned to input data having a high appearance frequency, and code data having a long data length is assigned to input data having a low appearance frequency. As a result, the average data length to be used is shortened to reduce the data amount of the entire code data. However, when the code data is decoded, a process for discriminating between the code lengths is required.

  On the other hand, in the isometric code, the code data is allocated with a constant code length regardless of the appearance frequency, and therefore, it may contain many parts that are substantially meaningless. Is unnecessary.

  As shown in the above embodiment, in the decoding process of this embodiment, the decoding information corresponding to the substantially effective portion of the input code data according to the predetermined condition as described above is stored in the LUT. In this regard, even for the isometric code, decoding information corresponding to the effective part excluding the substantially meaningless part is prepared in the LUT. Processing can be performed.

It is the block diagram which showed the outline | summary of the decoding system to which the decoding apparatus concerning this invention is applied. It is a circuit block diagram which shows 1st Embodiment of the decoding process part which is an example of the decoding apparatus which concerns on this invention. It is the graph of the 1st example which showed the basic example of how to allocate a code | symbol. It is the chart of the 2nd example which showed the basic example of how to allocate a code. It is an allocation table of the Huffman code of the first example based on the JPEG standard. It is the allocation table of the Huffman code of the 2nd example based on JPEG standard. It is a circuit block diagram which shows 2nd Embodiment of a decoding process part. It is the table | surface which showed the 1st example of the allocation of the code | symbol explaining the effect of 2nd Embodiment. It is the table | surface which showed the 2nd example of the allocation of the code | symbol explaining the effect of 2nd Embodiment. It is a circuit block diagram which shows 3rd Embodiment of a decoding process part. It is a circuit block diagram which shows 4th Embodiment of a decoding process part.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Decoding system, 10 ... Code input part, 20 ... Code extraction part, 30 ... Decoding processing part, 300 ... Memory part, 302 ... 1st LUT, 304 ... 2nd LUT, 306, 306a, 306b ... 1st 3 LUTs, 312... Valid upper bit number register unit, 314... Shift number register unit, 316, 316 a, 316 b... Shift number register unit, 320 ... shift amount adjustment processing unit, 326, 326 a, 326 b. Determination unit, 360 ... selection output unit, 380 ... stored information update unit, 40 ... code position management unit, 50 ... decoding result output unit

Claims (9)

A decoding device for decoding code data,
Decoding for short-bit code data having a rewritable storage device for storing information for decoding code data having a plurality of code lengths shorter than a predetermined number of bits among code data sequentially input to the decoding device An information storage unit;
There is a rewritable storage device that stores information for decoding the code data that is sequentially input to the decoding apparatus and having the same bit data as a processing target in common in the code data. A decoding information storage unit for continuous bit code data,
A continuous bit number storage unit having a rewritable storage device that stores information about the predetermined number of bits of code data to be processed by the decoding information storage unit for continuous bit code data;
A storage information update unit that rewrites information stored in each storage unit according to a code allocation method of code data sequentially input to the decoding device;
A determination unit for determining which of the decoding results output from the decoding information storage unit for short bit code data and the decoding information storage unit for continuous bit code data is to be selected;
A selection output unit that selects and outputs one of the decoding results output from the decoding information storage unit for short bit code data and the decoding information storage unit for continuous bit code data based on the determination result of the determination unit And a decoding device comprising: The continuous bit code data decoding information storage unit stores information for decoding the processing target code data in association with an effective portion excluding the predetermined number of consecutive bits from the processing target code data. The decoding device according to claim 1. The effective code data is extracted from the code data to be processed by excluding the continuous portion of the predetermined number of bits, and the effective portion of the code data is input to the decoding information storage unit for the continuous bit code data. The decoding apparatus according to claim 1, further comprising a partial extraction processing unit. The decoding device according to claim 3, wherein the effective part extraction processing unit includes a shift processing unit for moving code data sequentially input to the decoding device by the predetermined number of bits. The shift processing unit shifts code data that is input by the number of consecutive identical bits that appear on the head side of the code in common with all code data to be processed by the decoding information storage unit for continuous bit code data. The decoding device according to claim 4, wherein: The decoding information storage unit for continuous bit code data is a first decoding information storage unit for first continuous bit code data that stores information for decoding data that is continuous for the first predetermined number of bits or more, The decoding information storage unit for the short bit code data and the decoding information storage unit for the first continuous bit code data that are continuous for the second predetermined bit number that is less than or equal to the first predetermined number of bits. A decoding information storage unit for second continuous bit code data that stores information for decoding code data not to be processed,
The continuous bit number storage unit is changed according to the code allocation method for the second predetermined bit number of code data to be processed by the second continuous bit code data decoding information storage unit. A register unit for storing information,
The effective part extraction processing unit extracts code data of the effective part based on information about the second predetermined number of bits stored in the register unit, and extracts the code data of the effective part to the second To the decoding information storage unit for continuous bit code data of
The first continuous bit code data decoding information storage unit is information according to the code allocation method for the first predetermined number of bits for the code data to be processed, and the allocation method is Capture code data of the effective part based on predetermined information that is unchanged even if changed,
The determination unit, based on code data sequentially input to the decoding device and information on the second predetermined number of bits stored in the register unit, the decoding information storage unit for short bit code data and Any one of the decoding results output from the decoding information storage units for the first and second continuous bit code data should be selected. 6. The decoding device according to item. The decoding information storage unit for continuous bit code data is a first decoding information storage unit for first continuous bit code data that stores information for decoding data that is continuous for the first predetermined number of bits or more, The decoding information storage unit for the short bit code data and the decoding information storage unit for the first continuous bit code data that are continuous for the second predetermined bit number that is less than or equal to the first predetermined number of bits. A decoding information storage unit for second continuous bit code data that stores information for decoding code data not to be processed,
The continuous bit number storage unit is changed according to the code allocation method for the first predetermined number of bits for the code data to be processed by the first continuous bit code data decoding information storage unit. A first register unit for storing the information and a decoding information storage unit for the second continuous bit code data for the second predetermined number of bits for the code data to be processed. A second register unit for storing information to be changed in response,
The effective part extraction processing unit extracts the code data of the first effective part based on the information about the first predetermined number of bits stored in the first register unit, The code data of the effective portion is input to the first decoding information storage unit for the continuous bit code data, and the second data is stored based on the second predetermined number of bits stored in the second register unit. Code data of the effective portion of the second, and input the code data of the second effective portion to the second continuous bit code data decoding information storage unit,
The determination unit is configured to generate the short bit code data based on code data sequentially input to the decoding device and information on the predetermined number of bits stored in the first and second register units. 6. The decoding information storage unit and the first and second continuous bit code data decoding information storage units output from the decoding result storage unit to be selected are determined. The decoding device according to any one of the above. The continuous bit number storage unit stores information that is changed according to the code allocation method for the predetermined number of bits for the code data to be processed by the decoding information storage unit for the continuous bit code data. Part
The effective part extraction processing unit extracts code data of the effective part based on information about the predetermined number of bits stored in the register unit, and uses the code data of the effective part for the continuous bit code data Input to the decryption information storage unit,
The determination unit includes the decoding information storage unit for the short bit code data and the continuous bits based on the code data sequentially input to the decoding device and information on the predetermined number of bits stored in the register unit. The decoding apparatus according to any one of claims 3 to 5, wherein which of the decoding results output from the decoding information storage unit for code data is to be selected is determined. The continuous bit code data decoding information storage unit relates to the predetermined number of bits for the code data to be processed, based on predetermined information that remains unchanged even if the code allocation method is changed. The determination unit captures the short bit code data based on code data sequentially input to the decoding device and predetermined information that is invariable even if the code allocation method is changed. The decoding information storage unit for data and the decoding information storage unit for the continuous bit code data are determined which one of the decoding results to be selected is selected. The decoding device described.

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