JP2005094094A - Image processor and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that the amount of information is not possibly reduced effectively when a special processing, e.g. repeat or skip, occurs because pull down detection results do not match image data being read out. <P>SOLUTION: In correspondence with respective frame memories 11-1 to 11-n, a pull down detection system including pull down detection circuits 13-1 to 13-n and pull down detection judging flags 14-1 to 14-n, and a nonstandard decision system including nonstandard decision circuits 17-1 to 17-n and nonstandard decision flags 18-1 to 18-n are provided. When image data is read out from the frame memory, image data repeated under control of a cpu 19 is processed while being regarded as image data repeated by 3-2 pull down processing whereas skipped image data is processed while being regarded as image data different from that of one frame before thus eliminating contradiction between image data being read out and pull down detection results. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus and an image processing method.

  A 24 Hz progressive video recorded at 24 frames per second (such as a movie film) is displayed at 30 frames per second (60 fields) of the NTSC (National Television System Committee) system used in television broadcasting, for example, at 60 Hz interlace. In this case, as shown in FIG. 7, a 3-2 pull-down process for converting the rate by decomposing the frame image into fields and displaying the same field repeatedly is performed. Conversely, when recording the image data subjected to the 3-2 pull-down process on the recording medium, if the repeated image data is discarded, the amount of information recorded on the recording medium can be reduced. For this purpose, it is necessary to detect that the image data is repeated by 3-2 pull-down processing.

  Conventionally, when recording image data that has been subjected to 3-2 pulldown processing on a recording medium, when detecting that the image data has been repeated by 3-2 pulldown processing, the image data of the previous frame is retained. The difference between the image data of the current frame and the image data of the previous frame is taken, and it is determined whether or not the difference is smaller than a certain threshold value. Whether or not is detected (see, for example, Patent Document 1).

  Specifically, as shown in FIG. 8, a memory device 101 having a plurality of frame memories is prepared, and image data of one frame before is stored in each frame memory of the memory device 101, and the stored one frame before The subtraction circuit 102 takes the difference between the image data of the current frame and the image data of the current frame, and gives the subtraction result to the pull-down detection circuit 103. The pull-down detection circuit 103 compares the subtraction result of the subtraction circuit 102 with a certain threshold, detects that the image data has been repeated by 3-2 pull-down processing when the difference is smaller than the threshold, and determines the detection result. It gives to CPU104.

  When the CPU 104 receives a detection result indicating that the image data has been repeated by the 3-2 pull-down process from the pull-down detection circuit 103, the image of the current frame determined to be the repeated image data for the memory device 101. A command for prohibiting reading of data to the encoder 105 is given, and a command for prohibiting encoding processing is given to the encoder 105. As a result, the image data of the current frame determined to be image data repeated by the 3-2 pull-down process is not read from the memory device 101 to the encoder 105, and is not subjected to, for example, an MPEG encoding process. It is not recorded on the medium. As a result, the amount of information recorded on the recording medium can be reduced.

International Publication No. 00/13418 Pamphlet

  However, in the above prior art, when the timing for writing image data to the frame memory from the outside is asynchronous with the timing for reading the image data from the frame memory internally, or the image data input from the outside is a non-standard signal. In some cases, the following problems may occur. Here, the non-standard signal refers to a video signal in which the vertical synchronization signal interval, the horizontal synchronization signal interval, or the like is longer or shorter than the standard interval due to fast forward or rewind. When the timing for writing image data to the frame memory from the outside and the timing for reading image data from the frame memory internally are asynchronous, or when a non-standard signal is input from the outside, the timing for writing image data to the memory device 101 and the timing for reading it There is no correlation.

  Thus, if there is no correlation between the write timing and the read timing, when reading image data from the frame memory in which image data is being written from the outside, for example, if the read speed is faster than the write speed, Since image data is overtaken and read processing is performed, image corruption occurs. In order to prevent this image from collapsing, special processing such as skip and repeat by frame synchronization processing is generally performed. However, when such special processing occurs, the pull-down detection circuit 103 sequentially performs pull-down detection on the input image data, whereas the image data reading side performs, for example, repeat processing to perform the same image. Since data is read out, the detection result of the pull-down detection circuit 103 does not match the read image data. As a result, there is a possibility that the amount of information cannot be reduced effectively, for example, when the encoder 105 encodes to MPEG.

  The present invention has been made in view of the above problems, and the object of the present invention is to provide a case where the timing of writing image data from the outside and the timing of reading out image data are asynchronous, or a non-standard signal from the outside. An object of the present invention is to provide an image processing apparatus and an image processing method capable of effectively reducing the amount of information while preventing image collapse even when the image is input.

  In order to achieve the above object, in the present invention, an image processing apparatus having a frame memory for storing input image data and reading image data from the frame memory at a timing asynchronous with the input image data, Whether the image data of the previous frame stored in the frame memory is subtracted from the image data of the current frame, and whether the image data of the current frame is the image data repeated by the pull-down process based on the subtraction result Is detected and the detection result is retained. Then, when the image data is read from the frame memory, it is determined whether the image data read from the frame memory is the image data repeated by the pull-down process based on the detection result held.

  By using the held pull-down detection result when reading the image data from the frame memory, it is possible to reliably associate the read-out image data with the pull-down detection result. Also, it is determined whether the image data to be read is image data that has been subjected to special processing such as repeat for repeatedly reading the same image data or skipping over a certain amount of image data. In the case of repeated image data, pull-down processing is performed. In the case of skipped image data, it is determined that the image data is different from the image data of the previous frame, and inconsistency occurs between the read image data and the pull-down detection result. Can be eliminated.

  In the present invention, the image processing apparatus further includes a frame memory for storing input image data, and reads the image data from the frame memory at a timing asynchronous with the input image data. The period of the included vertical synchronizing signal is measured, whether or not the measurement result is a predetermined period is identified, and the identification result is held. Whether or not the image data read from the frame memory is the image data repeated by the pull-down process based on the detection result and the identification result held when the image data is read from the frame memory Determine whether.

  Here, the identification result of whether or not the measurement result has a predetermined cycle indicates that the input image data is a standard signal when the measurement result has a predetermined cycle, and the measurement result has a predetermined cycle. If not, it indicates that the input image data is a non-standard signal. When the identification result indicates the input of a non-standard signal, when the image data of the previous frame is read, it is determined that the image data has been repeated by pull-down processing regardless of the detection result. Further, when the identification result indicates the input of the standard signal and the identification result of the previous frame indicates the input of the non-standard signal, the image data of the previous frame is not normal image data, and the detection result is reliable. Since it cannot be performed, it is processed as image data that is not repeated by pull-down processing. By these processes, it can be determined without contradiction whether the read image data is the same as or different from the image data processed one frame before.

  According to the present invention, when the timing for writing image data from the outside and the timing for reading image data internally are asynchronous, if the read image is image data that has undergone special processing such as repeat or skip, the pull-down detection result Regardless of the value, by setting the pull-down detection result to a value corresponding to the special processing, it is possible to eliminate the contradiction between the read image data and the pull-down detection result, so that the amount of information can be effectively reduced.

  When the identification result indicates the input of a non-standard signal, the image data of the previous frame memory is read and processed as image data repeated by pull-down processing, while the identification result is the standard signal. When the identification result of one frame before indicates an input of a non-standard signal, it is processed as image data that is not repeated by pull-down processing, and the read image data is processed one frame before. Therefore, it is possible to determine whether they are the same or different from each other without contradiction, and the amount of information can be effectively reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration example of an image processing apparatus according to an embodiment of the present invention.

  As shown in FIG. 1, the image processing apparatus according to the present embodiment includes a plurality of frame memories 11-1 to 11-n that store input image data. Here, when the image data is externally written to and read from the frame memories 11-1 to 11-n, the frame memories 11-1 to 11- of the image data are synchronized with the input image data. While writing to n is performed, reading of the image data from the frame memories 11-1 to 11-n is performed at a timing asynchronous with the input image data.

  Each of the frame memories 11-1 to 11-n includes subtraction circuits 12-1 to 12-n as subtraction means, pull-down detection circuits 13-1 to 13-n as detection means, and pull-down detection determination as holding means. Flags 14-1 to 14-n, vertical synchronizing signal separation circuits 15-1 to 15-n, vertical synchronizing signal interval counters 16-1 to 16-n serving as counting means, and nonstandard determination circuit 17-1 serving as identification means To 17-n and non-standard determination flags 18-1 to 18-n, which are other holding means, are provided correspondingly. Note that subtraction circuits 12-1 to 12-n, pull-down detection circuits 13-1 to 13-n, vertical synchronization signal separation circuits 15-1 to 15-n, vertical synchronization signal interval counters 16-1 to 16-n, and non- The standard determination circuits 17-1 to 17-n may not be provided individually corresponding to the frame memories 11-1 to 11-n, but may be shared with the frame memories 11-1 to 11-n. . Further, a CPU 19 and an encoder 20 which are determination means are provided in common for the frame memories 11-1 to 11-n.

  The subtraction circuits 12-1 to 12-n subtract both the images by subtracting the image data of the current frame input from the outside and the image data of the previous frame stored in the frame memories 11-1 to 11-n. Take data differences. The subtraction results (differences) of the subtraction circuits 12-1 to 12-n are given to the pull-down detection circuits 13-1 to 13-n. The pull-down detection circuits 13-1 to 13-n are synchronized with the vertical synchronization signal Vsync obtained by being separated from the input image data by the vertical synchronization signal separation circuits 15-1 to 15-n, and the subtraction circuit 12-1. The result of subtraction of ˜12-n, that is, the image data of the current frame is repeated by the 3-2 pull-down process by comparing the difference between the image data of the current frame and the image data of the previous frame with a certain threshold value Detect whether it is data.

  More specifically, the pull-down detection circuits 13-1 to 13-n determine the difference between the image data of the current frame and the image data of the previous frame from the threshold for each of the plurality of frame memories 11-1 to 11-n. Detection result 1 indicating that the image data of the current frame is the image data repeated in the 3-2 pull-down process is output when the difference is equal to or smaller than 3-2, and the image data of the current frame is 3-2 A detection result 0 indicating that the image data is not repeated in the pull-down process is output. The detection results 1/0 of the pull-down detection circuits 13-1 to 13-n are held in the corresponding pull-down detection determination flags 14-1 to 14-n for each of the plurality of frame memories 11-1 to 11-n.

  In this example, the pull-down detection determination flags 14-1 to 14-n are provided as components different from the pull-down detection circuits 13-1 to 13-n, but the pull-down detection determination flags 14-1 to 14-n are provided. n can also be provided in the pull-down detection circuits 13-1 to 13-n. The pull-down detection circuits 13-1 to 13-n and the pull-down detection determination flags 14-1 to 14-n are provided for the plurality of frame memories 11-1 to 11-n. It is also possible to provide them in common for ˜11-n. If the image data is provided in common, it is detected for each frame memory 11-1 to 11-n whether or not the image data is repeated in the 3-2 pull-down process, and the detection result is stored in a plurality of frame memories 11-1. ˜11-n may be held in association with each other.

  The vertical synchronization signal separation circuits 15-1 to 15-n separate the vertical synchronization signal Vsync included in the image data from the input image data. The separated vertical synchronization signal Vsync is supplied to the pull-down detection circuits 13-1 to 13-n and the CPU 19, and the vertical synchronization signal interval counters 16-1 to 16-n and the nonstandard determination circuits 17-1 to 17-. given to n. The vertical synchronization signal interval counters 16-1 to 16-n are counters that count up, for example, in synchronization with a constant clock between two consecutive vertical synchronization signals Vsync. Accordingly, the count values of the vertical synchronization signal interval counters 16-1 to 16-n correspond to the period of two consecutive vertical synchronization signals Vsync. That is, it becomes a cycle of two vertical synchronization signals Vsync in which count value × clock cycle continues.

  The non-standard determination circuits 17-1 to 17-n have a determination window corresponding to the standard signal, and determine whether or not the count values of the vertical synchronization signal interval counters 16-1 to 16-n are outside the determination window. Thus, it is identified whether or not the period of the vertical synchronization signal Vsync included in the input image data is a predetermined period, that is, whether or not the input image data conforms to the standard signal. More specifically, the non-standard determination circuits 17-1 to 17-n have the input image data become standard signals if the count values of the vertical synchronization signal interval counters 16-1 to 16-n are within the determination window. An identification result 0 that is compliant is output, and if the count value is outside the determination window, an identification result 1 that the input image data does not conform to the standard signal (non-standard) is output.

  As an example, when a video signal conforming to the NTSC system is used as a standard signal, the vertical window is 30 Hz in the NTSC system, so the determination window is set to a value corresponding to (1/30) ± α (α is a margin). Whether the input image data conforms to the NTSC system is determined by determining whether the count values of the vertical synchronization signal interval counters 16-1 to 16-n are within the determination window. Can be identified. The identification results 1/0 of the nonstandard determination circuits 17-1 to 17-n are held in the corresponding nonstandard determination flags 18-1 to 18-n for each of the plurality of frame memories 11-1 to 11-n. .

  In this example, the vertical synchronization signal separation circuits 15-1 to 15-n and the vertical synchronization signal interval counters 16-1 to 16-n are provided for each of the plurality of frame memories 11-1 to 11-n. It is also possible to provide a plurality of frame memories 11-1 to 11-n in common. Further, the nonstandard determination circuits 17-1 to 17-n and the nonstandard determination flags 18-1 to 18-n may be provided in common for the plurality of frame memories 11-1 to 11-n. Is possible. When provided in common, the image data is subjected to non-standard identification for each of the frame memories 11-1 to 11-n storing the input image data, and the identification result is used as a plurality of frame memories 11-1 to 11-11. It may be held in association with each of -n.

  The CPU 19 obtains image data stored in the frame memory 11-i from any one of the plurality of frame memories 11-1 to 11-n (i is an arbitrary value of 1 to n). When reading, the detection result 1/0 of the pull-down detection circuit 13-i held in the pull-down detection determination flag 14-i corresponding to the frame memory 11-i and the non-holding held in the non-standard determination flag 18-i. The identification result 1/0 of the standard determination circuit 17-i is referred to. Based on the detection result 1/0 and the identification result 1/0, it is determined whether or not the image data read from the frame memory 11-i is the image data repeated by the 3-2 pull-down process. Based on the result, access to the frame memory 11-i is controlled.

  When the CPU 19 determines that the image data read from the frame memory 11-i is the image data repeated by the 3-2 pull-down process, the CPU 19 prohibits the frame memory 11-i from reading the image data to the encoder 20. And a command for prohibiting the encoding process to the encoder 20. Thereby, the image data of the frame memory 11-i determined to be repeated image data is not read from the frame memory 11-i to the encoder 20, and the encoder 20 performs an encoding process, for example, to MPEG. Absent. Therefore, since the image data repeated by the 3-2 pull-down process is not recorded on the recording medium, the amount of information recorded on the recording medium can be reduced.

  If the CPU 19 determines that the image data read from the frame memory 11-i is not the image data repeated by the 3-2 pull-down process, the CPU 19 instructs the frame memory 11-i to read the image data to the encoder 20. And an encoding execution command to the encoder 20. Thereby, the image data of the frame memory 11-i determined not to be repeated image data is read from the frame memory 11-i, and after being subjected to, for example, encoding processing to MPEG in the encoder 20, the recording medium To be recorded.

  Subsequently, an example of a specific image processing method in the image processing apparatus according to the present embodiment having the above-described configuration will be described. In the following description, the case where the number n of frame memories is n = 4, that is, there are four frame memories, will be described as an example.

  First, when the image data input from the outside is a standard signal, and the timing interval for writing image data from the outside to the frame memory is the same as the timing interval for reading image data from the frame memory internally, the operation description of FIG. This will be described with reference to the drawings.

  In FIG. 2, wt (write top) writes one field, wb (write bottom) writes one field, rt (read top) reads the other field, and rb (read bottom) reads the other. This means reading out of the field (same for other figures). Further, the upper part of the figure shows the timing relation of writing image data from the outside, and the lower part of the figure shows the timing relation of reading image data inside (the same applies to other figures).

  In the 3-2 pull-down method, the first frame (frame) is converted into 3 fields, the next frame is converted into 2 fields, and thereafter, 3 fields, 2 fields,. Therefore, when the image data subjected to the 3-2 pull-down process is written in the four frame memories 1 to 4, as shown in FIG. , Wb, wt), frame memory 2 and 3 for the next two fields (shaded wb, wt), frame memory 3 and 4 for the next three fields (outlined wb, wt, wb), frame Each image data for the next two fields (the shaded area wt and wb) is written in the memory 1.

  These 5 frames (10 fields) form one sequence of the 3-2 pull-down method. Here, in the portion of the third field, the image data of the third field becomes image data repeated by the 3-2 pull-down process, and therefore the pull-down detection result of the image data of the third field is 1. The fact that the timing interval for writing image data is the same as the timing interval for reading out means that the writing period A for image data for one field is equal to the reading period B for image data for one field. As shown in FIG. 2, the read image data and the pull-down detection result have a consistent relationship.

  Next, when image data input from the outside is a standard signal and the timing for writing image data from the outside to the frame memory and the timing for reading image data from the frame memory internally are asynchronous, FIG. 3 and FIG. The operation will be described with reference to FIG.

  When the timing at which image data is written to the frame memory from the outside and the timing at which image data is read from the frame memory are asynchronous, the CPU 19 stores a frame memory in which image data for the previous frame used for pull-down detection is stored. To read image data from the same frame memory. As a result, even if the timing for reading the image data internally is faster than the timing for writing the image data from the outside or vice versa, the image data is surely read from the frame memory in which the image data for one frame is written. Can be read. Such a process is called a frame sync process.

  However, during this frame sync process, if special processing such as repeat to read the same image data repeatedly for the image data to be read or skip to skip a certain amount of image data is performed, the input image data is sequentially pulled down. While the detection is performed, the same image data is read out by performing, for example, repeat processing on the image data reading side, so that there is a contradiction between the pull-down detection result and the read image data. . In order to eliminate the contradiction, the CPU 19 determines whether the image data to be read is repeated image data or skipped image data. In the case of repeated image data, the pull-down detection determination flag is forcibly set to 1 regardless of the value of the pull-down detection determination flag, and processing is performed assuming that the image data is repeated. Conversely, for a skipped image, the pull-down detection determination flag pull is forcibly set to 0 regardless of the value of the pull-down detection determination flag, and processing is performed assuming that the image data is different from the image data of the previous frame.

  Specifically, as shown in FIG. 3, when the image data read period B for one field is shorter than the image data write period A for one field (A> B), 2 of the frame memory 2 is used. During the reading period of the second field, the timing for reading the image data internally overtakes the timing for writing the image data from the outside, so that the same two fields of image data are read again by the repeat process. Therefore, regarding the image data for two fields by this repeat processing, the pull-down detection determination flag is forcibly set to 1 regardless of the value of the pull-down detection determination flag, and is regarded as image data repeated by the 3-2 pull-down processing. Process.

  On the contrary, as shown in FIG. 4, when the image data read period B for one field is longer than the image data write period A for one field (A <B), there is no problem in the first sequence. Although data is read out, the timing of writing image data from the outside during the reading period of the frame memory 1 of the next sequence overtakes the timing of reading out the image data internally, so the frame memory is skipped over the frame memory 2 by skip processing. 3 image data is read out. Therefore, for the image data for two fields in the frame memory 3 by this skip processing, the pull-down detection determination flag is forcibly set to 0 regardless of the value of the pull-down detection determination flag and an image different from the image data of the previous frame. Treat as data.

  In this way, when image data input from the outside is a standard signal and the timing for writing image data to the frame memory and the timing for reading image data from the frame memory are asynchronous, special processing such as repeat and skip In order to eliminate the contradiction between the image data read by and the pull-down detection result, it is determined whether the read image data is repeated image data or skipped image data. In the case of skipped image data, processing is performed by regarding it as image data different from the image data of the previous frame. The image data is the same as or different from the image data processed one frame ago Therefore, it is possible to effectively reduce the amount of information.

  Next, the case where image data input from the outside is a non-standard signal will be described with reference to the flowchart of FIG. 5 and the operation explanatory diagram of FIG. The operation explanatory diagram of FIG. 6 shows an example when a vertical synchronization signal shorter than the standard is input.

  Even when a non-standard signal is input from the outside, the image data input from the outside is basically a standard signal, and the timing for writing the image data to the frame memory from the outside and the image data from the frame memory internally As in the case where the read timing is asynchronous, the image data read internally is read from the same frame memory as the frame memory read by pull-down detection. At that time, the CPU 19 refers to the non-standard determination flag corresponding to the frame memory to be read and the non-standard determination flag one frame before. The memory access algorithm at this time is shown in the flowchart of FIG.

  In the flowchart of FIG. 5, first, a non-standard determination flag corresponding to a frame memory from which image data is read is referred to, and it is determined whether or not the non-standard determination flag is 1 (step S11). If the non-standard determination flag is 1, the image data of the previous frame memory is read so that the corrupted image data is not read, and the pull-down detection determination flag is set regardless of the value of the pull-down detection determination flag. The image is forcibly set to 1 and processed as an image repeated by the 3-2 pull-down process (step S12).

  If the non-standard determination flag corresponding to the frame memory from which the image data is read is 0, the non-standard determination flag of the previous frame is referred to and it is determined whether the non-standard determination flag is 1 (step S13). . If the non-standard judgment flag of 1 frame before is 1, even if the pull-down detection judgment flag of the frame memory from which the image data is read is 1, the image data of the previous frame is not normal image data and the judgment is reliable. Since this is not possible, the pull-down detection determination flag is forcibly set to 0 and the image data is not repeated by the 3-2 pull-down process (step S14). If the non-standard determination flag of one frame before is also 0, normal processing for reading image data with reference to the pull-down detection determination flag as it is is executed (step S15).

  As described above, the non-standard determination flag corresponding to the frame memory from which the image data is read is referred to. When the non-standard determination flag is 1, the image data of the previous frame memory is read and 3-2 pull-down processing is performed. When the non-standard determination flag is 0 and the non-standard determination flag of 1 frame before is 1, the image data is processed as non-repeated image data by 3-2 pull-down processing. Thus, since it can be determined without contradiction whether the read image data is the same as or different from the image data processed one frame before, the amount of information can be effectively reduced.

  In the above embodiment, the pull-down detection system including the subtraction circuits 12-1 to 12-n, the pull-down detection circuits 13-1 to 13-n, and the pull-down detection determination flags 14-1 to 14-n, and the vertical synchronization signal Non-standard including separation circuits 15-1 to 15-n, vertical synchronization signal interval counters 16-1 to 16-n, non-standard determination circuits 17-1 to 17-n, and non-standard determination flags 18-1 to 18-n However, when the image data input from the outside is a standard signal, only the pull-down detection determination flag is used without referring to the non-standard determination flag. If the system is based on the assumption that non-standard signals are not input from the outside, only the pull-down detection system is provided and the intended purpose is achieved. It can be.

It is a block diagram which shows the structural example of the image processing apparatus which concerns on one Embodiment of this invention. FIG. 10 is an operation explanatory diagram when image data input from the outside is a standard signal, and a timing interval at which image data is written to the frame memory and a timing interval at which image data is read from the frame memory are the same. FIG. 10 is an operation explanatory diagram at the time of repeat processing when image data input from the outside is a standard signal and the timing of writing image data to the frame memory and the timing of reading image data from the frame memory are asynchronous. FIG. 10 is an operation explanatory diagram of skip processing in a case where image data input from the outside is a standard signal and the timing for writing image data to the frame memory and the timing for reading image data from the frame memory are asynchronous. It is a flowchart which shows the algorithm of a memory access when the image data input from the outside is a nonstandard signal. It is operation | movement explanatory drawing when the image data input from the outside is a nonstandard signal. It is a conceptual diagram of 3-2 pulldown processing. It is a block diagram which shows the structural example of the image processing apparatus which concerns on a prior art example.

Explanation of symbols

  11-1 to 11-n: frame memory, 12-1 to 12-n: subtraction circuit, 13-1 to 13-n: pull-down detection circuit, 14-1 to 14-n: pull-down detection determination flag, 15-1 -15-n ... vertical synchronization signal separation circuit, 16-1 to 16-n ... vertical synchronization signal interval counter, 17-1 to 17-n ... non-standard determination circuit, 18-1 to 18-n ... non-standard determination flag , 19 ... CPU, 20 ... encoder

Claims (12)

An image processing apparatus having a frame memory for storing input image data and reading image data from the frame memory at a timing asynchronous with the input image data,
Subtracting means for subtracting the image data of the previous frame and the image data of the current frame stored in the frame memory;
Detection means for detecting whether the image data of the current frame is image data repeated by pull-down processing based on a subtraction result of the subtraction means;
Holding means for holding a detection result of the detecting means;
When reading image data from the frame memory, it is determined whether the image data read from the frame memory is image data repeated by the pull-down process based on the detection result held in the holding unit. An image processing apparatus comprising: a determination unit that performs the determination. The determination unit determines that the image data read from the frame memory is image data repeated by pull-down processing regardless of the detection result when the image data is read repeatedly. The image processing apparatus described. The determination means determines that the image data read from the frame memory is different from the image data of the previous frame regardless of the detection result when the image data skips a certain amount of image data. The image processing apparatus according to claim 1. An image processing apparatus having a frame memory for storing input image data and reading image data from the frame memory at a timing asynchronous with the input image data,
Subtracting means for subtracting the image data of the previous frame and the image data of the current frame stored in the frame memory;
Detection means for detecting whether the image data of the current frame is image data repeated by pull-down processing based on a subtraction result of the subtraction means;
Measuring means for measuring a period of a vertical synchronizing signal included in the input image data;
Identification means for identifying whether the measurement result of the measurement means is a predetermined cycle;
Holding means for holding the detection result of the detection means and the identification result of the identification means;
Whether the image data read from the frame memory is the image data repeated by the pull-down process based on the detection result and the identification result held in the holding means when reading the image data from the frame memory An image processing apparatus comprising: determination means for determining whether or not. When the identification means held in the holding means indicates that the predetermined period is not the predetermined period, the determination means pulls down regardless of the detection result of the detection means when reading image data one frame before. The image processing apparatus according to claim 4, wherein the image processing apparatus determines that the image data has been repeated by the processing. The determination means indicates that the identification result held in the holding means is the predetermined cycle, and the identification result held in the holding means corresponding to the image data of one frame before is 5. The image processing apparatus according to claim 4, wherein when the predetermined period is not indicated, it is determined that the image data is not repeated by pull-down processing regardless of a detection result of the detection unit. An image processing method for writing input image data to a frame memory and reading the image data from the frame memory at a timing asynchronous with the input image data,
A first step of subtracting the image data of the previous frame stored in the plurality of frame memories and the image data of the current frame;
A second step of detecting whether the image data of the current frame is image data repeated by pull-down processing based on the subtraction result in the first step;
A third step for holding the detection result in the second step;
When reading image data from the frame memory, based on the detection result held in the third step, it is identified whether the image data read from the frame memory is image data repeated by the pull-down process And a fourth step. An image processing method comprising: 5. In the fourth step, when the image data read from the frame memory is image data read repeatedly, it is determined as image data repeated by pull-down processing regardless of the detection result. 8. The image processing method according to 7. In the fourth step, if the image data read from the frame memory is image data that skips a certain amount of image data, it is determined that the image data is different from the image data of the previous frame regardless of the detection result. The image processing method according to claim 7, wherein: An image processing method for writing input image data to a frame memory and reading the image data from the frame memory at a timing asynchronous with the input image data,
A first step of subtracting the image data of the previous frame stored in the frame memory from the image data of the current frame;
A second step of detecting whether the image data of the current frame is image data repeated by pull-down processing based on the subtraction result in the first step;
A third step for holding the detection result in the second step;
A fourth step of measuring a period of a vertical synchronization signal included in the input image data;
A fifth step for identifying whether or not the measurement result in the fourth step has a predetermined period;
A sixth step for holding the identification result in the fifth step;
When reading image data from the frame memory, the image data read from the frame memory is repeated by the pull-down process based on the detection result held in the third step and the identification result held in the sixth step. And a seventh step of determining whether or not the image data is an image data. In the seventh step, when the identification result held in the sixth step indicates that it is not the predetermined cycle, when the image data of the previous frame is read, the detection result in the second step is related. The image processing method according to claim 10, wherein the image data is determined to be repeated by pull-down processing. In the seventh step, the identification result held in the sixth step indicates the predetermined cycle, and the identification result held in the sixth step corresponding to the image data one frame before is 11. The image processing method according to claim 10, wherein when it indicates that the period is not a predetermined period, it is determined that the image data is not repeated by the pull-down process regardless of the detection result in the second step.

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