JP2005093828A - Semiconductor device and manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily and securely obtain a semiconductor device capable of obtaining desired performance as to an inductive passive element and to obtain a high-precision inductive passive element which has a small variation in characteristic. <P>SOLUTION: When the inductive passive element is formed of a wire on an element separating and insulating film 2 formed on a silicon substrate 1, a substrate which has a 2 to 4 kΩcm specific resistance value, preferably, a 3 kΩcm specific resistance value is used as the silicon substrate. Further, a substrate is used which has a specific resistance value obtained from ρ<SB>Si</SB>=20/(2πε<SB>Si</SB>ε<SB>0</SB>), where ε<SB>0</SB>is a dielectric constant under a vacuum, ε<SB>Si</SB>is a specific dielectric constant of silicon, and (f) is a signal frequency. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a high-frequency semiconductor integrated circuit formed on a silicon substrate, and particularly to a semiconductor device having an inductive passive element such as an inductor as an integrated circuit in addition to an active element such as a transistor and a manufacturing method thereof.

  When forming a high-frequency semiconductor integrated circuit on a silicon substrate, in order to improve the operating characteristics of the high-frequency circuit and reduce the number of component mounting steps, in addition to active elements such as transistors, passives such as inductive inductors An element may be formed on an integrated circuit. At this time, there is a problem that the Q value (Quality Factor) is lowered due to the attenuation of the signal from the wiring constituting the passive element to the silicon substrate side.

  Conventionally, as a method for improving the characteristics of passive elements such as an inductor formed on a silicon substrate as an integrated circuit, 1) a method using a special manufacturing process dedicated to forming the inductor, and 2) wiring constituting the inductor 3) A method for improving the inductor characteristics by keeping the wiring resistance low, and 3) a method for improving the inductor characteristics by suppressing the loss from the inductor to the silicon substrate by increasing the substrate resistance of the silicon substrate. It has been.

  Among these, the manufacturing method using the inductor-dedicated process 1) requires a special process to be added to the normal semiconductor process, which inevitably increases the manufacturing cost. Therefore, in order to improve the performance of the inductor while suppressing an increase in cost, it is effective to reduce the resistance of the wiring in 2) or increase the resistance of the silicon substrate in 3). The present invention relates to increasing the resistance of the silicon substrate 3), and the prior art relating to the present invention will be described below.

[First prior art]
The first prior art will be described with reference to Patent Document 1. In the first prior art, a method for providing a semiconductor device having a high substrate resistance corresponding to a high Q value and high speed of the semiconductor device is described. In a semiconductor device in which an element active layer is formed on a silicon substrate in order to constitute a target semiconductor device, the dopant concentration other than the element active layer portion of the silicon substrate is 1 × 10 ¹³ cm ⁻³ or less. The oxygen donor concentration is 1 × 10 ¹³ cm ⁻³ or less. In this case, the dopant concentration of 1 × 10 ¹³ cm ⁻³ or less corresponds to a specific resistance value of about 400 Ωcm or more in the case of n-type silicon (see, for example, Non-Patent Document 1). As described above, the silicon substrate is maintained at a high resistance by suppressing the dopant concentration and the oxygen donor concentration to a low level, which corresponds to a high Q value. In particular, in order to realize a low oxygen donor concentration, the oxygen concentration in the substrate is set to 4 × 10 ¹³ cm ⁻³ or more and 15 × 10 ¹³ cm ⁻³ or less, and the heat treatment time in the range of 500 ° C. to 900 ° C. is predetermined calculation. By suppressing the time to a time equal to or less than the value obtained by the equation, it is possible to suppress the generation of oxygen donors and to suppress the decrease in the substrate resistivity due to the generation of oxygen donors.

[Second prior art]
The second prior art will be described with reference to Patent Document 2. In the second prior art, a method for providing a semiconductor device and a method for manufacturing the same in which a defect due to the occurrence of slip is prevented using a high resistance substrate having excellent RF characteristics is described. In order to configure the target semiconductor device, the interstitial oxygen concentration in the silicon substrate used for manufacturing is 8 × 10 ¹³ cm ⁻³ or less, and the density of micro defects (Bulk Micro Defect, BMD) due to oxygen precipitation is 1 ×. By using a substrate having a substrate resistivity of 10 ¹³ cm ⁻³ or more and a substrate specific resistance of 500 Ωcm or more, and suppressing the thermal process in the device process within 25 hours in terms of 1000 ° C., the reduction in resistance of the substrate is suppressed, The effect of suppressing the occurrence of slip on the silicon substrate during the production is obtained.

[Third prior art]
The third prior art will be described with reference to Patent Document 3. In the third prior art, a method for providing an inexpensive and accurate high-frequency module using a silicon substrate is described. In order to realize the target semiconductor device (module), the resistance of the silicon substrate is increased by diffusing gold, platinum or copper into the silicon substrate on which the passive element is formed, and a passive element such as a spiral inductor is formed on the substrate. And forming an active element on another silicon substrate to fabricate a semiconductor chip, and flip-chip mounting the silicon substrate on which the passive element is formed and the semiconductor chip on which the active element is formed, so that the metal atoms are formed. An effect is obtained that diffusion to the semiconductor chip on which the active element is formed can be prevented.

The applicant has not yet found prior art documents related to the present invention by the time of filing other than the prior art documents specified by the prior art document information described in this specification.
JP 2000-269225 A JP 2002-9081 A JP 2002-319658 A SMSze, Physics of Semiconductor Devices, 2nd ed., P.32, John Wiley & Sons, Inc., New York, 1981. J. Kodate et al., "Gain Improvement of a 2.4-GHz / 5-GHz CMOS Low Noise Amplifier by using High-Resistivity Silicon-on-Insulator Wafers," IEICE Trans. Electoron., Vol.E86-C, pp. 1041-1049, 2003. CPYue and S. Wong, "0n-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's," IEEE J. Solid-State Circuits, Vol.33, pp.743-752, 1998. AMNiknejad and RG Meyer, "Analysis, Design, and Optimization of Spiral Inductors and Transformers for Si RF IC's," IEEE J. Solid-State Circuits, Vol.33, pp.1470-1481, 1998. R. Brederlow et al., "A Mixed-Signal Design Roadmap," IEEE Design & Test of Computers, Vol.18, pp.34-46, Nov-Dec 2001. S. Gevorgian, "Surface Impedance of Silicon Substrates and Films," Int. J. RF and Microwave Computer-Aided-Engineering, Vol.8, pp.433-440, 1998. Muneyuki Date, "Asakura Modern Physics Course 12 Physical Physics", 7. Dielectric Phenomena, pp.134-148, Asakura Shoten, 1991. Supervised by Junichi Nishizawa, edited by Hiroshi Tango, "Semiconductor Engineering Series 9 Semiconductor Process Technology", 9. Crystal / Wafer Technology, pp.262-283, Baifukan, 1998. Yoshihiro Konishi, Fundamentals of Microwave Circuits and Their Applications, 2.3 Microstrip Line, pp.53-66, General Electronic Publishing Company, 1992.

  However, although such a conventional technique uses a silicon substrate with a high resistance to improve the characteristics of the inductive passive element, the range for defining the characteristics of the silicon substrate is wide and specific numerical grounds Therefore, there has been a problem that a semiconductor device capable of obtaining a desired performance for an inductive passive element cannot be easily and accurately realized. In addition, although these prior arts have been studied to increase the Q value, they do not consider the suppression of the Q value variation, and it is not possible to obtain a highly accurate inductive passive element with a small variation in characteristics. was there.

  For example, although the first prior art aims to cope with higher Q values and higher speeds of semiconductor devices, there is no specific disclosure as to how much high Q values are effective. That is, this high Q value is considered to indicate that of a passive element such as an inductor, but an embodiment including dimensions and a configuration method regarding the passive element and characteristic data related thereto are not specifically disclosed. Regarding the description of the dopant concentration, the upper limit value is shown as a numerical value, but the relationship between the obtained effect and the dopant concentration only has to satisfy the value of the dopant concentration, and there is no effect below that value. However, the lower the value, the more clearly the effect of increasing the Q value is not clearly stated.

  Although it is stated in the second prior art that the high resistance substrate is excellent in RF characteristics, there is no specific disclosure as to how it is excellent. Further, it is said that the specific resistance value of the silicon substrate should be 500 Ωcm or more, but no specific basis for this numerical value is presented, and it is only necessary that the specific resistance value of the silicon substrate satisfy the value, The specific effect level is not clearly stated as to whether the higher the specific resistance value, the more remarkable the effect.

  In the third prior art, the specific resistance value of silicon is required to be 10 kΩcm or more. As specific data for explaining this, the transmission loss of the 50Ω strip line is reduced by increasing the resistance of the substrate. The data shows that the decrease is saturated at 100 kΩcm. However, the correspondence between the value shown in the data of 100 kΩcm and the point that the above 10 kΩcm is required is unclear, and the illustration of the 50Ω strip line is appropriate as an explanation of the passive element formed on the silicon substrate, particularly the spiral inductor. I can't say. The thickness of the silicon on which the 50Ω strip line is formed is 100 μm, and this thickness is different from the thickness of the substrate in most high-frequency silicon semiconductor devices. Furthermore, since the high resistance substrate for forming the passive element and the semiconductor chip for forming the active element are flip-chip mounted, the inductive passive element and the semiconductor integrated circuit as in the present invention are mounted on the same silicon substrate. A similar method cannot be applied to the semiconductor device formed above.

  The present invention is for solving such problems, and can easily and accurately realize a semiconductor device capable of obtaining a desired performance for an inductive passive element, and has a highly accurate inductive passive with small variation in characteristics. An object of the present invention is to provide a semiconductor device and a manufacturing method from which an element can be obtained.

  In order to achieve such an object, a semiconductor device according to the present invention includes a high frequency integrated circuit formed on a silicon substrate, and the high frequency integrated circuit includes an inductive passive element, A silicon substrate, an insulating film formed on the silicon substrate, and a wiring that is formed on the insulating film and forms an inductive passive element. The silicon substrate has a specific resistance value of 2 kΩcm or more and 4 kΩcm. The following silicon substrate is used.

  At this time, a silicon substrate having a specific resistance value of approximately 3 kΩcm may be used as the silicon substrate.

According to another aspect of the present invention, there is provided a semiconductor device including a high frequency integrated circuit formed on a silicon substrate, the high frequency integrated circuit including an inductive passive element, the silicon substrate, and the silicon substrate An insulating film formed on the substrate, and a wiring that is formed on the insulating film and forms an inductive passive element. As a silicon substrate, the dielectric constant in vacuum is ε ₀ , and the relative dielectric constant of silicon is A silicon substrate having a specific resistance value ρ _Si obtained by ρ _Si = 20 / (2πfε ₀ ε _Si ), where ε _Si and the signal frequency is f, is used.

  According to another aspect of the present invention, there is provided a semiconductor device including a high frequency integrated circuit formed on a silicon substrate, the high frequency integrated circuit including an inductive passive element, the silicon substrate, and the silicon substrate A specific resistance value-Q value of an inductive passive element obtained in advance as a silicon substrate, comprising: an insulating film formed on the substrate; and a wiring formed on the insulating film and constituting an inductive passive element. A silicon substrate having a specific resistance value determined from a value characteristic and a desired Q value variation allowable range is used.

  In each of the semiconductor devices described above, a silicon substrate having a ground conductor layer and having a substrate thickness at which the distance between the ground conductor layer and the wiring is 200 μm or more may be used.

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device used when manufacturing the semiconductor device described above, and the interstitial oxygen concentration in the silicon substrate is 3 × 10 ¹⁷ cm ⁻³ or less. The process to control is provided.

  Another method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device used in manufacturing the semiconductor device described above, wherein the silicon substrate is subjected to heat treatment to generate oxygen donors in the silicon substrate. Up to a predetermined temperature that can be suppressed.

  Another method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device used when manufacturing the above-described semiconductor device, wherein a lattice in a silicon substrate is obtained by performing a heat treatment on the silicon substrate. A step of precipitating interstitial oxygen as minute defects.

In the present invention, when an inductive passive element is formed by wiring on an insulating film formed on a silicon substrate, the silicon substrate has a specific resistance value of 2 kΩcm or more and 4 kΩcm or less, and preferably a specific resistance value of approximately 3 kΩcm. Or a dielectric constant in vacuum, where ε _{0 is} the dielectric constant in vacuum, ε _Si is the relative dielectric constant of _silicon , and f is the signal frequency, the specific resistance determined by ρ _Si = 20 / (2πfε _Si ε ₀ ) as the silicon substrate. Since a substrate having a value is used, a semiconductor device capable of obtaining a desired performance with respect to an inductive passive element can be easily and accurately realized, and not only the inductance L but also the Q value has a small variation. Inductive passive elements can be obtained.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a front view showing the configuration of the semiconductor device according to the first embodiment of the present invention. 2 is a cross-sectional view taken along the line II-II in FIG.
The semiconductor device includes a silicon substrate 1, an element isolation insulating film 2 formed on the silicon substrate 1, and a spiral (vortex) formed on the element isolation insulating film 2 to form an inductive passive element, that is, an inductor. ) -Shaped wirings 3A to 3C.

This inductor structure includes a spiral upper layer wiring 3C, a lower layer wiring 3A for pulling out the inner end of the spiral to the outside, and a via 3B for connecting the upper layer wiring 3C and the lower layer wiring 3A. With this structure, a spiral inductor having two terminals is formed.
In the present embodiment, silicon having a specific resistance value of 2 kΩcm or more and 4 kΩcm or less is used as the silicon substrate 1 so that high performance can be obtained as inductor performance, particularly Q value (Quality Factor), and variation in Q value can be reduced. A substrate is used.

  A manufacturing process of the semiconductor device according to the present embodiment will be described with reference to FIGS. This semiconductor device is manufactured by using a known semiconductor device manufacturing technique, and detailed detailed processing steps are omitted. First, a silicon substrate 1 having a specific resistance value of 3 kΩcm to 10 kΩcm is prepared, and an element isolation insulating film 2 is formed on the region corresponding to the inductor structure, and then aluminum (Al), copper (Cu), or The lower layer wiring 3A for the lead pattern is formed of a metal such as an alloy (Al—Cu).

  Next, the interlayer insulating film 2A is formed so as to cover the element isolation insulating film 2 and the lower layer wiring 3A, and a through hole for the via 3B reaching the lower layer wiring 3A is provided in the interlayer insulating film 2A. Then, after forming a metal film using the same metal as described above so as to cover the through-hole and the interlayer insulating film 2A, the unnecessary portion is removed, so that the spiral upper layer wiring 3C and the upper layer wiring 3C and the lower layer are removed. Vias 3B for electrically connecting the wiring 3A are collectively formed. Thereafter, the insulating film 2B is formed so as to cover the interlayer insulating film 2A and the upper wiring 3C, and a series of manufacturing steps is completed.

The semiconductor device according to the present embodiment is not limited to the manufacturing process described above, and a semiconductor device having a similar structure may be manufactured using another manufacturing process.
Further, in FIG. 2, the upper layer wiring 3C and the lower layer wiring 3A are shown as an example in which each of the upper layer wiring 3C and the lower layer wiring 3A is constituted by one metal wiring layer. However, the structure and cross-sectional shape of each wiring layer are not limited. . For example, a structure in which two or more parallel wiring layers are connected to each other up and down can be regarded as a thick wiring, a structure in which a spiral structure is stacked up and down using two or more wiring layers, and the cross-sectional shape of the wiring layer is not rectangular. A structure such as a time-shaped shape or a structure having a letter shape may be used. In addition, for the separation of the wiring layer and the silicon substrate and the separation between the wiring layers, a case where a silicon oxide film is used is shown, but an insulating dielectric that can be used in a semiconductor manufacturing process is not necessarily used. Any body material may be used as long as it has insulating properties such as polyimide, low-k material, and organic insulating film.

[Determination of resistivity value by simulation]
Next, a method for determining the specific resistance value of the silicon substrate used in the present embodiment based on the simulation result will be described in detail. When determining the specific resistance value of the silicon substrate, the Q value of the inductor is used as an evaluation scale, and a specific resistance value that provides a high Q value with little variation may be selected. Therefore, in the simulation, it is necessary to perform an electromagnetic field simulation on the structure of the inductor and obtain a change in Q value when the specific resistance value is changed, that is, a specific resistance value-Q value characteristic. Note that the effect of increasing the resistance of the silicon substrate on the inductance characteristics is described in detail in Non-Patent Document 2, for example.

  In general, the Q value of an inductor is defined by the following equation 1, and it can be determined that the higher the Q value, the higher the performance as an inductive passive element. Specifically, the Q value is obtained from Equation 2 from the admittance parameter (Y parameter) of the inductor obtained by simulation. The definition, calculation method, and other relational expressions of the inductor Q values shown in Equations 1 and 2 are described in detail in Non-Patent Documents 3 and 4.

  Next, an actual simulation and its result will be described with reference to FIGS. FIG. 3 shows examples of various constants used in the simulation. FIG. 4 is a graph showing a specific resistance value-Q value characteristic obtained by simulation. Note that. A known electromagnetic field simulator may be used for the simulation. For example, the electromagnetic field simulator “Sonnet EM Suite” has been widely used for inductor design on silicon substrates, stripline design, etc., and the simulation results should be applied directly to the design of actual semiconductor devices. Can do.

  The structure of the inductor to be simulated was a simulation of the structure shown in FIGS. As a boundary condition for the simulation, a cavity (not shown) that determines the size of the simulation structure was a grounded ideal (infinite conductivity) metal. The dimension of the cavity viewed from above was set to 500 μm × 500 μm by taking a sufficient distance so that the cavity does not affect the inductor structure inside the cavity. The dimensions of the spiral viewed from above were such that the inner diameter was 100 μm, the width of the wiring was 20 μm, the space between the wirings was 5 μm, the number of turns of the spiral was 3.5 turns, and the outer diameter was about 300 μm.

The cross-sectional structure of the semiconductor device includes, in order from the lower layer (bottom) of the cavity, a silicon substrate 1 having a desired specific resistance value with a thickness of 500 μm, an element isolation insulating film 2 made of a silicon oxide film (SiO ₂ ) with a thickness of 1 μm, A lower layer wiring 3A having a desired thickness, a via 3B, and an upper layer wiring 3C having a desired thickness are laminated, and the periphery of each of the wirings 3A, 3C and the via 3B is an interlayer insulation made of a silicon oxide film (SiO ₂ ). The film 2A and the insulating film 2B are insulated.
The above structure models the structure of a spiral inductor formed on a silicon substrate for simulation. However, it reflects the structure of an actually fabricated inductor, and the simulation results are the same as the actual inductor structure. It can be regarded as a characteristic.

The material of the upper layer wiring 3C and the lower layer wiring 3A was modeled as aluminum (Al), and aluminum conductivity σ = 3.72 × 10 ⁷ Ω ⁻¹ m ⁻¹ was used. The wiring film thickness t reflects the actual inductor structure, and the thickness of the upper layer wiring 3C is 2 μm and the thickness of the lower layer wiring 3A is 0.5 μm. The specific resistance value ρ _Si of the silicon substrate 1 was changed from 10 Ωcm to 100 kΩcm.

Under the above conditions, an electromagnetic field simulation was performed on the spiral inductor structure of FIGS. 1 and 2, and the Q value of the inductor was calculated from the result, and the specific resistance value-Q value characteristic of FIG. 4 was obtained. In general, the Q value of the inductor varies depending on the signal frequency f. In FIG. 4, the maximum Q value Q _max obtained for each specific resistance value in the signal frequency range of 1 GHz to 5 GHz is plotted.
As is clear from the specific resistance value-Q value characteristic of FIG. 4, it can be seen that the Q _max of the spiral inductor is saturated when the specific resistance value of the silicon substrate is about 3 kΩcm or more and does not improve any further.

In general, silicon wafers for LSI manufacturing that are available as mass-produced products at the industrial product level have a variation of about ± 30% in terms of specific resistance values due to fluctuation factors such as intra-wafer fluctuation, inter-wafer fluctuation, and manufacturing time fluctuation. Yes. Further, if the specific resistance value is required to be more accurate than this variation, the wafer price rises, leading to an increase in the cost of the semiconductor device.
In the specific resistance value-Q value characteristic of FIG. 4, the change width ΔQ of Q _max when the specific resistance value changes by ± 30% is about 15% when the specific resistance value is about 200 Ωcm, and is the highest Q value. The change width becomes large, and when the specific resistance value is 3 kΩcm or more, the change width of the Q value becomes small as about 2%.

On the other hand, in the inductor, the inductance L and the Q value are the main performance indexes, and variation accuracy is required for each. In the case of a spiral inductor, the variation in the inductance L is determined by the accuracy with respect to the processing dimension of the planar shape seen from above. For example, the processing accuracy of a wiring having a width of 20 μm is usually 0.5 μm or less. Is 2-3%.
Here, when the specific resistance value is 200 Ωcm as described above, the Q value variation is 15%, which is much larger than the inductance L variation 2-3%, and a highly accurate inductor cannot be realized. On the other hand, when the specific resistance value is 3 kΩcm, the variation of the Q value is about 2%, which can be suppressed to substantially the same as the variation of the inductance L.

Further, from the specific resistance value-Q value characteristic of FIG. 4, when the specific resistance value is 3 kΩcm or more, the Q value is saturated, but the manufacturing cost of the silicon substrate tends to increase as the specific resistance value increases. Yes, the specific resistance value should be as low as possible.
Accordingly, when manufacturing variations with respect to the specific resistance value are expected from such conditions, a silicon substrate having a specific resistance value in the range of 3 kΩcm ± 30%, that is, in the range of 2 kΩcm to 4 kΩcm is used. Therefore, not only the inductance L but also the Q value has a small manufacturing variation, and a highly accurate inductor can be realized at a relatively low cost. In addition, it is desirable to use a silicon substrate having a specific resistance value of 3 kΩcm, so that it is possible to realize a relatively inexpensive and extremely accurate inductor.

Non-Patent Document 5 describes the development direction of analog-digital mixed-signal LSI based on the ITRS (International Technology Roadmap for Semiconductors) roadmap. This non-patent document 5 shows that the target value of the Q value required for the on-chip type inductor as in the present invention is about Q = 12 in 2001 and about Q = 16 in 2004.
According to the present embodiment, the above target value can be sufficiently achieved with a general and inexpensive process technology without requiring development of a high-level process technology.

[Other simulation examples]
Next, with reference to FIGS. 5 and 6, another simulation example for an inductor having the same structure as that of FIGS. FIG. 5 shows examples of various constants used in the simulation. FIG. 6 is a graph showing a specific resistance value-Q value characteristic obtained by simulation.
The structure of the inductor to be simulated was a simulation of the structure shown in FIGS. The shape parameters regarding the inductor and the semiconductor device are the same as those in the above-described simulation example, but the material parameters are different.

  Actually, when manufacturing a silicon semiconductor device, aluminum is rarely used as it is, and an alloy (Al—Cu alloy) in which copper is mixed with aluminum is frequently used because of demands on manufacturing and quality control. Further, since the thickness of the wiring layer is several μm, the effect as a thin film also appears, and the effective characteristics of the wiring layer differ from that when the thin film effect can be ignored. Therefore, the electrical characteristics of the wiring layer were modeled based on the actually measured values, and the characteristics of the spiral inductor were simulated using the values, and the specific resistance value-Q value characteristics as shown in FIG. 5 were obtained. .

This specific resistance value-Q value characteristic agrees well with the Q value actually measured by manufacturing a spiral inductor. In actual measurement, Q _max = 6.5 when the specific resistance value of the silicon substrate was 15 Ωcm, and Q _max = 11.2 when the specific resistance value was 3 kΩcm. From this specific resistance value-Q value characteristic, it is understood that the Q _max of the spiral inductor is saturated when the specific resistance value of the silicon substrate is about 3 kΩcm or more, as in FIG.

Also in this case, as in the case of the specific resistance value-Q value characteristic of FIG. 4 described above, by setting the specific resistance value to 3 kΩcm or more, the variation in the Q value is suppressed to 2% as in the case of the variation in the inductance L. Can do.
Therefore, in consideration of manufacturing variations with respect to the cost and specific resistance value of the silicon substrate, a silicon substrate having a specific resistance value in the range of 3 kΩcm ± 30%, that is, in the range of 2 kΩcm to 4 kΩcm may be used. It will be. Desirably, by using a silicon substrate having a specific resistance value of 3 kΩcm, it is possible to realize an inductor with relatively low cost and extremely high accuracy.

[Determination of specific resistance value by calculation formula]
Next, a method for determining the specific resistance value of the silicon substrate used in the present embodiment using a calculation formula will be described in detail. Non-Patent Document 6 details the theoretical expression and behavior when silicon is electromagnetically handled as a dielectric material, and describes the behavior of the dielectric as a general theory. Non-Patent Document 7 is available. The electromagnetic behavior of an isotropic dielectric material having no electrical conductivity, that is, having an infinite specific resistance value, can be derived from Maxwell's electromagnetic equation using the relative permittivity ε _r . The behavior of an isotropic dielectric material having conductivity can be described by extending the relative dielectric constant ε _r to a complex number and defining the complex dielectric constant ε. Here, the complex dielectric constant ε is expressed by Equation 3.

At this time, the real part ε ′ is the same as ε _{r in the} case of having no conductivity, and the imaginary part ε ″ is an attenuation term due to having a finite conductivity. Conductivity σ or specific resistance value The relationship with ρ is as shown in Equation 3. When this Equation 3 is applied to the case of silicon and silicon is viewed as a dielectric, the contribution of conductivity (or the contribution of resistivity) can be regarded as sufficiently small. Is obtained as long as the complex permittivity ε satisfies ε ′ >> ε ″, that is, the following equation (4).

If this equation 4 is modified and the fact that it is sufficiently large is represented by a coefficient S, the specific resistance value ρ _Si of the silicon substrate that can be considered that the contribution of conductivity can be ignored can be obtained by equation 5.

Next, a specific silicon specific resistance value for realizing the effect in the present embodiment is obtained from Equation 5. The coefficient of the signal frequency f is included in Equation 5, but the signal frequency f of the signal used in the high-frequency semiconductor device described in this embodiment is about 1 GHz to about 5 GHz, and the upper limit is about 10 GHz at most. It is. As numerical values used for the calculation, a relative dielectric constant ε _Si = 11.9 of silicon and a dielectric constant ε ₀ = 8.85 × 10 ¹² F / m in vacuum are used.

Further, as the value of the coefficient S, a magnification at which the contribution of conductivity can be considered to be negligible, that is, a general and sufficient value in practical terms from the range of error or variation in specific resistance value may be used. At this time, according to the above-described simulation, it is desirable that ρ _Si = 3.0 kΩcm as the specific resistance value, and use the strict f = 1 GHz as the signal frequency to be used as the signal frequency from 1 GHz to 5 GHz. Is calculated backward, S = 20 times (5%) is obtained.
When the specific resistance value ρ _Si is calculated using the coefficient S for a typical signal frequency, for example, when f = 1.0 GHz, ρ _Si = 3.0 kΩcm, and the ISM (Industrial, Science, Medical) band When f = 2.4 GHz, ρ _Si = 1.3 kΩcm, and when f = 5.0 GHz, ρ _Si = 0.6 kΩcm.

Therefore, when the range of about 1 GHz to 5 GHz is considered as the signal frequency to be used, the specific resistance value of silicon in which the effect of the present invention is remarkable can be calculated very easily from Equation 5. By using a silicon substrate having the obtained specific resistance value, it is possible to easily and accurately obtain the desired performance of the inductive passive element, and to obtain a highly accurate inductive passive element with small variation in characteristics. It is done.
In the above description, the use frequency is 1 GHz to 5 GHz, but this is a numerical value used for specifically explaining the effectiveness of the present invention, and does not limit the effective frequency range of the present invention. Even when the frequency range to be used is different, ρ _Si corresponding to the frequency range can be obtained from Equation 5 in the same manner as described above.

[Second Embodiment]
Next, a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a front view showing the configuration of the semiconductor device according to the second embodiment of the present invention. 8 is a cross-sectional view taken along the line VIII-VIII in FIG.
This semiconductor device includes a silicon substrate 1, an element isolation insulating film 2 formed on the silicon substrate 1, and a meander line (inductive passive element, that is, an inductor, formed on the element isolation insulating film 2. Meander line (meander line) -like wiring 3D.

This inductor structure is composed of a meander line wiring 3D. With this structure, a meander inductor having two terminals is formed.
In the present embodiment, as in the first embodiment described above, the silicon substrate 1 is provided so that a high value can be obtained as the performance of the inductor, particularly the Q value (Quality Factor), and the variation in the Q value can be reduced. A silicon substrate having a specific resistance value of 2 kΩcm or more and 4 kΩcm or less is used.

  A manufacturing process of the semiconductor device according to the present embodiment will be described with reference to FIGS. This semiconductor device is manufactured by using a known semiconductor device manufacturing technique, and detailed detailed processing steps are omitted. First, after preparing a silicon substrate 1 having a specific resistance value of 2 kΩcm to 4 kΩcm and forming an element isolation insulating film 2 thereon, aluminum (Al), copper (Cu), or an alloy thereof (Al-Cu), etc. The wiring 3D is formed of the above metal. And insulating film 2D is formed so that wiring 3D may be covered, and a series of manufacturing processes are complete | finished.

The semiconductor device according to the present embodiment is not limited to the manufacturing process described above, and a semiconductor device having a similar structure may be manufactured using another manufacturing process.
Further, in FIG. 8, the case where the wiring 3D is configured by one metal wiring layer is shown as an example, but the structure and cross-sectional shape of each wiring layer are not limited. For example, a structure in which two or more parallel wiring layers are connected to each other up and down can be regarded as a thick wiring, a structure in which two or more wiring layers are used to overlap a meander line structure, and the cross-sectional shape of the wiring layer is not rectangular A structure such as a U-shaped shape or a structure having a C-shaped shape may be used. In addition, for the separation of the wiring layer and the silicon substrate and the separation between the wiring layers, a case where a silicon oxide film is used is shown, but an insulating dielectric that can be used in a semiconductor manufacturing process is not necessarily used. Any body material may be used as long as it has insulating properties such as polyimide, low-k material, and organic insulating film.

[Determination of resistivity value by simulation]
Next, a method for determining the specific resistance value of the silicon substrate used in the present embodiment based on the simulation result will be described in detail with reference to FIGS. FIG. 9 shows various constant examples used in the simulation. FIG. 10 is a graph showing a specific resistance value-Q value characteristic obtained by simulation. For the simulation, a known electromagnetic field simulator may be used. For example, the electromagnetic field simulator “Sonnet EM Suite” has been widely used for inductor design on silicon substrates, stripline design, etc., and the simulation results should be applied directly to the design of actual semiconductor devices. Can do.

  As the structure of the inductor to be simulated, a structure simulating the structure shown in FIGS. As a boundary condition for the simulation, a cavity (not shown) that determines the size of the simulation structure was a grounded ideal (infinite conductivity) metal. The size of the cavity viewed from above was set to 380 μm × 500 μm by taking a sufficient distance so that the cavity did not affect the inductor structure inside. The wiring 3D has a wiring width of 20 μm, and the total length of the wiring is 1500 μm by meandering six times.

The cross-sectional structure of the semiconductor device includes a silicon substrate 1 having a desired specific resistance value of 500 μm in thickness, an element isolation insulating film 2 made of a silicon oxide film (SiO ₂ ) having a thickness of 1 μm, and a lower layer (bottom) of the cavity, and Wirings 3D having a desired thickness are stacked, and the periphery of the wiring 3D is insulated by an insulating film 2D made of a silicon oxide film (SiO ₂ ).
The above structure models the structure of a meander line inductor formed on a silicon substrate for simulation. However, it reflects the structure of the actually manufactured inductor, and the simulation results remain as they are. Can be regarded as a characteristic of

The material of the upper layer wiring 3C and the lower layer wiring 3A was modeled as copper (Cu), and copper conductivity σ = 5.80 × 10 ⁷ Ω ⁻¹ m ⁻¹ was used. The wiring film thickness t reflects the actual inductor structure, and the thickness of the wiring 3D is 2 μm. The specific resistance value ρ _Si of the silicon substrate 1 was changed from 10 Ωcm to 100 kΩcm.

Under the above conditions, an electromagnetic field simulation was performed on the meander-line inductor structure of FIGS. 7 and 8, and the Q value of the inductor was calculated from the result, and the specific resistance value-Q value characteristic of FIG. 10 was obtained. In general, the Q value of the inductor varies depending on the signal frequency f. In FIG. 10, the maximum Q value Q _max obtained for each specific resistance value in the range of the target signal frequency of 1 GHz to 5 GHz is plotted.
As is apparent from the specific resistance value-Q value characteristic of FIG. 10, the Q _max of the spiral inductor is saturated when the specific resistance value of the silicon substrate is 2 to 3 kΩcm or more, and is not improved further.

Also in this case, as in the case of the specific resistance value-Q value characteristic of FIG. 4 described above, by setting the specific resistance value to 3 kΩcm or more, the variation in the Q value is suppressed to 2% as in the case of the variation in the inductance L. Can do.
Therefore, in consideration of manufacturing variations with respect to the cost and specific resistance value of the silicon substrate, a silicon substrate having a specific resistance value in the range of 3 kΩcm ± 30%, that is, in the range of 2 kΩcm to 4 kΩcm may be used. It will be. Desirably, by using a silicon substrate having a specific resistance value of 3 kΩcm, it is possible to realize an inductor with relatively low cost and extremely high accuracy.

  In addition, according to this simulation, the same result as that of the spiral inductor can be obtained for the meander line inductor. It can be seen that the above-described effects can be obtained by using a material having a specific resistance of 3 kΩcm. That is, the specific resistance value at which the Q value of the inductor formed on the silicon substrate is saturated is almost determined only by the properties of the silicon substrate regardless of the material of the wiring layer and the shape of the inductor. It is in good agreement with the specific resistance value obtained from Equation 5 derived as a body.

[Third Embodiment]
Next, a semiconductor device according to a third embodiment of the present invention will be described. The semiconductor device according to the present embodiment is the same as the semiconductor device according to the first and second embodiments described above, except that silicon subjected to at least one of the following first to third oxygen donor formation suppression processes is applied. A substrate is used.
As described above, in the configuration of the semiconductor device of the present invention, it is important that the specific resistance value of the silicon substrate is a value derived from Equation 5 described above and simulation. The specific resistance value of the silicon substrate can be changed through the manufacturing process of the semiconductor integrated circuit. The causes include the contamination and activation of impurities into the silicon substrate and the donor formation of oxygen present in the silicon substrate.

  Impurities can be prevented from being mixed into the silicon substrate to some extent by managing the manufacturing process. However, since the oxygenation of oxygen in the substrate depends on the thermal history in the manufacturing process, it is necessary to apply the conditions for suppressing oxygenation as a process condition. Conditions for suppressing the oxygenation of oxygen in the substrate are widely known. For example, although detailed in Non-Patent Document 8, three oxygen donors that can be applied to the semiconductor device described in each embodiment of the present invention are described here. The suppression process will be described.

[First oxygen donor suppression treatment]
First, a method of using a silicon substrate in which the interstitial oxygen concentration in the silicon substrate is 3 × 10 ¹⁷ cm ⁻³ or less will be described as the first oxygen donor conversion suppressing process. In the CZ method (Czochralski method), which is most widely used as a method for manufacturing a silicon substrate, it is difficult to manufacture a silicon substrate having a low oxygen concentration as described above. This is because silicon is melted during the manufacturing process of the substrate. This is because oxygen enters from the quartz crucible. There are FZ method (Float Zone method), MCZ method (Magnetic field applied Czochralski method) and the like as methods for producing a low oxygen concentration silicon substrate, both of which have been put into practical use.

However, the silicon substrate manufactured by the FZ method has the merit that the oxygen concentration is very low, but 1) it is vulnerable to thermal stress during the process and is prone to slip and other defects. 2) Manufactured compared to the MCZ method. There are disadvantages such as high cost and 3) difficult application to large-diameter silicon substrates. If the MCZ method is used, it is possible to cope with an increase in diameter, and it is possible to control the oxygen concentration to 3 × 10 ¹⁷ cm ⁻³ or less, and an MCZ substrate that satisfies the conditions necessary for the present invention is commercially available at the present time. It can be purchased as a product. The CZ method, FZ method, and MCZ method are all well-known techniques, and details thereof are omitted here.

[Second Oxygen Donor Inhibition Treatment]
Next, as the second oxygen donor conversion suppression process, the thermal history in each manufacturing process of the semiconductor device is limited, and in any process, the heat treatment of the silicon substrate is set to 400 ° C. to 500 ° C. There is a method of suppressing the occurrence. It is widely known that interstitial oxygen in a silicon substrate is converted into a donor by heat treatment at 400 ° C. to 500 ° C., which is called a thermal donor (TD). Since this thermal donor has a property of decreasing or disappearing by heat treatment at 600 ° C. or higher, thermal donor generated during the manufacturing process can be suppressed by adding heat treatment at 600 ° C. or higher. In particular, in a sintering process in a hydrogen atmosphere, which is the final process of the manufacturing process, a heat treatment of about 450 ° C. is often performed. However, if the processing temperature and processing time are controlled, the generation of thermal donors is generated throughout the manufacturing process. Can be suppressed.

[Third Oxygen Donor Inhibition Treatment]
As a third oxygen donor formation suppressing process, there is a method of suppressing the generation of oxygen donors by precipitating interstitial oxygen as minute defects by a heat treatment at 500 ° C. to 700 ° C. on the silicon substrate. It is widely known that interstitial oxygen in a silicon substrate is precipitated by heat treatment at 500 ° C. to 700 ° C., which is called a micro defect (BMD). By precipitating interstitial oxygen as BMD at the stage of the substrate before the manufacturing process, the interstitial oxygen concentration can be kept low, and the generation of thermal donors can be suppressed. However, since the precipitated BMD has a property of being melted by high-temperature and long-time heat treatment, it is necessary to reduce the total processing time for the high-temperature process in the manufacturing process to a time at which BMD does not disappear.

[Fourth Embodiment]
Next, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. In the first to third embodiments described above, the case where the specific resistance of the silicon substrate is specified has been described, but in this embodiment, the thickness is specified in addition to the specific resistance of the silicon substrate. Is.
In other words, when a high-resistance silicon substrate is handled as a dielectric, the relationship between the wiring structure that constitutes the inductor and the ground conductor on the back of the silicon substrate is approximated by the behavior of the high-frequency signal of the microstrip line, and the wiring of the inductor A semiconductor device is configured by obtaining a guideline for conditions under which the influence of the ground conductor can be ignored on the structure and determining the thickness of the silicon substrate based on the guideline. The electromagnetic behavior of a high-resistance silicon substrate can be handled by regarding the substrate as a dielectric, and can be expressed by the relative dielectric constant ε _Si of the silicon substrate.

Next, a method for calculating a guideline regarding the thickness of the high-resistance silicon substrate in the present embodiment will be specifically described. In the calculation, a calculation formula relating to a microstrip line structure used for signal transmission in the microwave region is used. For example, Non-Patent Document 9 describes this microstrip line.
FIG. 11 shows a cross-sectional structure of the microstrip line. As shown in FIG. 11, the microstrip line has a cross-sectional structure in which a ground conductor 5 on the back surface of the substrate, a dielectric layer 6 having a thickness h having a relative dielectric constant ε _r , and a conductor line 7 having a width W are laminated. . The signal transmission mode can be approximated by a TEM wave (Transverse Electoro-Magnetic Wave).

From Non-Patent Document 9, the behavior of the microstrip line can be expressed by using an effective dielectric constant ε _W , and this ε _W can be approximated by the following equation (6). At this time, ε, h, W are the same as the parameters described in FIG. In Expression 6, when W → ∞, that is, when the ground conductor 5 is at infinity and does not affect the conductor line 7, ε _W is expressed by Expression 7.

This equation 7 is that the electric field spreads isotropically around the conductor line 7 without being influenced by the ground conductor 5, the upper half is air (relative permittivity 1), and the lower half is a dielectric layer (relative permittivity ε _r ). As the ground conductor 5 approaches, ε _W changes from the value of Equation 7, and as a result, the characteristics of the microstrip line and inductor formed by the conductor line 7 change. In Equation 6, the condition that the ground conductor 5 can be considered sufficiently far is Equation 8, and if the ground conductor 5 is sufficiently far from the conductor line 7 and expressed by a coefficient S, the dielectric layer necessary for the ground conductor 5 to be negligible. The thickness h of 6 can be obtained by Equation 9.

  Next, the thickness h of the silicon substrate for realizing the effect in the present invention is specifically obtained from Equation 9. Equation 6 includes the width W of the conductor line 7. The line width W used in the inductor described in the present invention is about 20 μm. When 100 (1%) is used as the value of the coefficient S, h = 200 μm can be obtained when W = 20 μm. Here, it is difficult to obtain the value of the practical coefficient S analytically, and it is necessary to determine it based on measured data of the inductor or a simulation described later.

From the above results, when the line width of the inductor is 20 μm, in order that the ground conductor 5 on the back surface of the silicon substrate 6 does not affect the characteristics of the inductor, the thickness of the silicon substrate should be thicker than about 200 μm. Is obtained.
Therefore, by using a silicon substrate having a thickness of 200 μm or more as the silicon substrate used in the first to third embodiments described above, an inductor having a high Q value and a small variation in Q value and a stable characteristic can be obtained. Can be realized.

[Determination of substrate thickness by simulation]
Next, a method for determining the thickness of the silicon substrate used in the present embodiment based on the simulation result will be described in detail with reference to FIGS. FIG. 12 is an explanatory diagram showing various constants used in the simulation. FIG. 13 is a graph showing specific resistance value-substrate thickness characteristics obtained by simulation. Note that. A known electromagnetic field simulator may be used for the simulation. For example, the electromagnetic simulator “Sonnet EM Suite” is widely used for inductor design on silicon substrates, stripline design, etc., and the simulation results should be applied directly to the design of actual semiconductor devices. Can do.

  The structure of the inductor to be simulated was a simulation of the structure shown in FIGS. As a boundary condition for the simulation, a cavity (not shown) that determines the size of the simulation structure was a grounded ideal (infinite conductivity) metal. The dimension of the cavity viewed from above was set to 500 μm × 500 μm by taking a sufficient distance so that the cavity does not affect the inductor structure inside the cavity. The dimensions of the spiral viewed from above were such that the inner diameter was 100 μm, the width of the wiring was 20 μm, the space between the wirings was 5 μm, the number of turns of the spiral was 3.5 turns, and the outer diameter was about 300 μm.

The cross-sectional structure of the semiconductor device is, in order from the lower layer (bottom) of the cavity, an element isolation insulation comprising a silicon substrate 1 having a desired specific resistance value ρ _Si with a thickness h _Si and a silicon oxide film (SiO ₂ ) having a thickness of 1 μm. A film 2, a lower layer wiring 3A having a desired thickness, a via 3B, and an upper layer wiring 3C having a desired thickness are stacked, and the periphery of each of the wirings 3A, 3C and the via 3B is made of a silicon oxide film (SiO ₂ ). It is insulated by the interlayer insulating film 2A and the insulating film 2B.
The above structure models the structure of a spiral inductor formed on a silicon substrate for simulation. However, it reflects the structure of an actually fabricated inductor, and the simulation results are the same as the actual inductor structure. It can be regarded as a characteristic.

The material of the upper layer wiring 3C and the lower layer wiring 3A was modeled as aluminum (Al), and aluminum conductivity σ = 3.72 × 10 ⁷ Ω ⁻¹ m ⁻¹ was used. The wiring film thickness t reflects the actual inductor structure, and the thickness of the upper layer wiring 3C is 2 μm and the thickness of the lower layer wiring 3A is 0.5 μm. The specific resistance value ρ _Si of the silicon substrate 1 was 3 kΩcm. Then, the thickness h _Si of the silicon substrate 1 was changed from 1000 μm to 10 μm.

Under the above conditions, an electromagnetic field simulation was performed on the spiral inductor structure of FIGS. 1 and 2, and the Q value of the inductor was calculated from the result to obtain the substrate thickness-Q value characteristic of FIG. In general, the Q value of the inductor varies depending on the signal frequency f. In FIG. 13, the maximum value Q _max of the Q value obtained for each substrate thickness in the range of the target signal frequency of 1 GHz to 5 GHz is plotted.
As is apparent from the substrate thickness-Q value characteristic of FIG. 13, it can be seen that the Q _max of the spiral inductor is saturated when the thickness of the silicon substrate is 200 μm or more and does not improve any further.

It can also be seen that when the silicon substrate is made thinner than 200 μm, the Q _{max of the} inductor tends to decrease. This is because the ground conductor on the back surface of the substrate affects the characteristics of the inductor due to the proximity of the inductor structure and the ground conductor on the back surface. This phenomenon can be explained in the same way as the influence of the ground conductor on the line conductor in the microstrip line. The simulation result that the substrate thickness in the spiral inductor is 200 μm and the guideline for the substrate thickness obtained from the microstrip line. The value of about 200 μm is in good agreement.

Therefore, by selecting the substrate having the above-described desired specific resistance as the silicon substrate and selecting the substrate thickness corresponding to the saturation region of the substrate thickness-Q value characteristic, an inductive passive device is obtained as an actual semiconductor device. The desired performance of the element can be obtained easily and accurately. Further, since the Q value is in the saturation region, the change in Q _max due to the variation in the substrate thickness is extremely small, and an inductive passive element having stable characteristics as a whole can be obtained.

  In each of the embodiments described above, the effect is shown for the spiral inductor and the meander line inductor. However, the shape of these inductors is not limited. For example, a distributed constant type such as a microstrip line, a stub is used. Even if the structure is formed as described above or is formed in a solenoid shape, the same effect as described above can be obtained if it is formed on a silicon substrate.

1 is a front view showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is II-II sectional drawing of the semiconductor device of FIG. It is an example of a simulation constant of the semiconductor device concerning the 1st embodiment of the present invention. It is a specific resistance value-Q value characteristic obtained by simulation of the semiconductor device concerning a 1st embodiment of the present invention. It is another example of simulation constants of the semiconductor device concerning the 1st embodiment of the present invention. It is a specific resistance value-Q value characteristic obtained by other simulation of the semiconductor device concerning a 1st embodiment of the present invention. It is a front view which shows the structure of the semiconductor device concerning the 2nd Embodiment of this invention. FIG. 8 is a VIII-VIII cross-sectional view of the semiconductor device of FIG. 7. It is an example of the simulation constant of the semiconductor device concerning the 2nd Embodiment of this invention. It is a specific resistance-Q value characteristic obtained by simulation of the semiconductor device concerning a 2nd embodiment of the present invention. It is a perspective view which shows a general microstrip line. It is a simulation constant example of the semiconductor device concerning the 4th Embodiment of this invention. It is the substrate thickness-Q value characteristic obtained by the simulation of the semiconductor device concerning the 4th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation insulating film, 2A ... Interlayer insulating film, 2B, 2D ... Insulating film, 3A ... Lower layer wiring, 3B ... Via, 3C ... Upper layer wiring (spiral shape), 3D ... Wiring (Meander line shape) 5) Ground conductor, 6 ... Dielectric layer, 7 ... Conductor line.

Claims (8)

A semiconductor device comprising a high frequency integrated circuit formed on a silicon substrate, the high frequency integrated circuit including an inductive passive element,
A silicon substrate;
An insulating film formed on the silicon substrate;
A wiring formed on the insulating film and constituting the inductive passive element;
2. The semiconductor device according to claim 1, wherein the silicon substrate comprises a silicon substrate having a specific resistance value of 2 kΩcm or more and 4 kΩcm or less. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the silicon substrate is a silicon substrate having a specific resistance value of approximately 3 kΩcm. A semiconductor device comprising a high frequency integrated circuit formed on a silicon substrate, the high frequency integrated circuit including an inductive passive element,
A silicon substrate;
An insulating film formed on the silicon substrate;
A wiring formed on the insulating film and constituting the inductive passive element;
The silicon substrate has a specific resistance value ρ _Si determined by ρ _Si = 20 / (2πfε ₀ ε _Si ), where ε _{0 is} the dielectric constant in vacuum, ε _Si is the relative dielectric constant of _silicon , and f is the signal frequency. A semiconductor device comprising a silicon substrate. A semiconductor device comprising a high frequency integrated circuit formed on a silicon substrate, the high frequency integrated circuit including an inductive passive element,
A silicon substrate;
An insulating film formed on the silicon substrate;
A wiring formed on the insulating film and constituting the inductive passive element;
The silicon substrate comprises a silicon substrate having a specific resistance value determined from a specific resistance value-Q value characteristic of the inductive passive element obtained in advance and a desired Q value variation allowable range. Semiconductor device. In the semiconductor device according to claim 1,
The silicon substrate has a ground conductor layer, and has a substrate thickness such that a distance between the ground conductor layer and the wiring is 200 μm or more. A method for manufacturing a semiconductor device used in manufacturing the semiconductor device according to claim 1, wherein the interstitial oxygen concentration in the silicon substrate is controlled to 3 × 10 ¹⁷ cm ⁻³ or less. A method for manufacturing a semiconductor device, comprising:   A method of manufacturing a semiconductor device used when manufacturing the semiconductor device according to claim 1, wherein the heat treatment for the silicon substrate is performed at a predetermined temperature at which generation of oxygen donors in the silicon substrate can be suppressed. The manufacturing method of the semiconductor device characterized by the above-mentioned. 6. A method of manufacturing a semiconductor device according to claim 1, wherein the interstitial oxygen in the silicon substrate is made minute by performing a heat treatment on the silicon substrate. A method of manufacturing a semiconductor device, comprising a step of depositing as a defect.

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