JP2005086087A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same which suppress contamination of a silicon layer of source/drain regions caused by the sidewall formation of the MOSFET and reduction of the thickness of the silicon layer even in an SOI layer. <P>SOLUTION: In an SOI substrate 11, a gate insulating film 14 on a P<SP>-</SP>region 13, a gate electrode 15, and a sidewall 16 are formed. Elevated S/D (Source/Drain) regions 17 include N<SP>-</SP>regions 171, highly doped N<SP>+</SP>regions 172, and silicon epitaxial layers 173 respectively formed on the N<SP>+</SP>regions 172 and arranged on both sides of the sidewall 16. A lower-level insulating film 161 of the sidewall 16 serves as a stopping layer in dry-etching the upper-level insulating film 162 as well as a protecting layer for the SOI substrate 11. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention particularly relates to a semiconductor device including an elevated S / D (source / drain) transistor formed on an SOI (Silicon On Insulator) substrate and a method for manufacturing the same.

  Elevated S / D (source / drain) transistors achieve the formation of shallow S / D regions and good contact properties to improve the short channel effect problem of MOSFETs. That is, the selective epitaxial technique of silicon is used to form the S / D region, and the surface of the S / D region is pushed up from the channel region to be high. As a result, the S / D region has a shallow junction depth and can secure a thickness that prevents contact penetration and high resistance.

It is important to clean the surface of the S / D region in order to make the surface easy to grow before epitaxial growth. Conventionally, at the time of MOSFET formation, after etching the sidewall, the damaged region on the Si surface is removed by CF-type chemical dry etching such as CF ₄ / O ₂ plasma. That is, the surface layer containing the carbon component and oxygen of the resist which is difficult to epitaxially grow is scraped off (see, for example, Patent Document 1).
Takumi Nakahata, et al. “Low thermal budget surface cleaning after dry etching for selective silicon epitaxialgrowth”, Journal of Crystal Growth, 226, p.443-450 (2001)

  Depending on the plasma non-uniformity and process fluctuation during the sidewall etching and chemical dry etching, there is a region where impurities remain in the surface of the S / D region, and a portion where normal epitaxial growth does not occur. Further, since the Si on the surface of the S / D region is scraped, the thickness of the Si layer in the S / D region is reduced in the SOI (Silicon On Insulator) layer. In particular, in a fully depleted SOI layer (FDSOI) in which the SOI layer has a thickness of several tens of nm, the Si layer in the S / D region can be completely eliminated. In this case, epitaxial growth does not occur because the base crystal disappears.

  The present invention has been made in view of the above circumstances, and a semiconductor device and a method of manufacturing the same for suppressing contamination and thickness reduction of the Si layer in the S / D region accompanying the formation of the sidewall of the MOSFET also in the SOI layer. It is something to be offered.

  A semiconductor device according to the present invention includes a first conductivity type silicon single crystal substrate on an insulating layer, a gate insulating film on the silicon single crystal substrate, a gate electrode on the gate insulating film, and a side of the gate electrode. First and second insulating films constituting a wall, and a second conductivity type impurity region including a silicon epitaxial layer disposed on both sides of the sidewall, wherein the first insulating film includes the first insulating film, It is located under the second insulating film and serves as a stopper layer for processing the second insulating film and also serves as a protective layer for the silicon single crystal substrate.

  A semiconductor device according to the present invention includes a first conductivity type silicon single crystal substrate on an insulating layer, a gate insulating film on the silicon single crystal substrate, a gate electrode on the gate insulating film, and a side of the gate electrode. First and second insulating films constituting a wall, and a second conductivity type impurity region including a silicon epitaxial layer disposed on both sides of the sidewall, wherein the first insulating film includes the first insulating film, The second insulating film is characterized in that it is arranged so as to be penetrated further in the lower layer.

According to each of the above semiconductor devices according to the present invention, the sidewall is constituted by the first and second insulating films. The first insulating film is a stopper layer at the time of processing the second insulating film, and serves as a protective layer for the silicon single crystal substrate forming the source / drain. As a result, the required thickness can be maintained even with a thin silicon single crystal substrate. The remaining form of the first insulating film is a form in which the first insulating film is disposed so as to be more inwardly in the lower layer with respect to the second insulating film.
Each of the semiconductor devices according to the present invention further includes a silicide on the silicon epitaxial layer.

  A semiconductor device according to the present invention includes a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode on the gate insulating film, and first and second insulating films constituting sidewalls of the gate electrode, And a source / drain region including an epitaxial layer disposed on both sides of the sidewall, wherein the first insulating film is located under the second insulating film and is processed in the second insulating film And a protective layer for the semiconductor substrate.

  A semiconductor device according to the present invention includes a semiconductor substrate, a gate insulating film on the semiconductor substrate, a gate electrode on the gate insulating film, and first and second insulating films constituting sidewalls of the gate electrode, And a source / drain region including an epitaxial growth layer disposed on both sides of the sidewall, and the first insulating film is more inwardly formed in a lower layer than the second insulating film. It is arranged.

According to each of the above semiconductor devices according to the present invention, the sidewall is constituted by the first and second insulating films. The first insulating film serves as a stopper layer for processing the second insulating film, and serves as a protective layer on the surface where the source / drain regions are formed. As a result, the required thickness can be maintained even with a thin silicon single crystal substrate. The remaining form of the first insulating film is a form in which the first insulating film is disposed so as to be more inwardly in the lower layer with respect to the second insulating film.
Each of the semiconductor devices according to the present invention further includes a silicide on the epitaxial growth layer.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film on a first conductivity type silicon single crystal substrate, a step of forming a gate electrode on the gate insulating film, and a region of the gate electrode. Using the mask as a mask, introducing a second conductivity type impurity onto the silicon single crystal substrate, forming a first insulating film covering the gate electrode and the silicon single crystal substrate, and the first insulation Forming a second insulating film having a different etching selectivity on the film; selectively anisotropically etching the second insulating film to form a sidewall of the gate electrode; and A step of selectively wet-etching the insulating film to leave only the sidewall portion; and a step of forming an epitaxial layer by selective epitaxial growth of silicon. And butterflies.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film on a first conductivity type silicon single crystal substrate, a step of forming a gate electrode on the gate insulating film, the gate electrode, Forming a first insulating film covering the silicon single crystal substrate; forming a second insulating film having a different etching selectivity on the first insulating film; and selecting the second insulating film Forming a sidewall of the gate electrode by anisotropic etching, a step of selectively wet-etching the first insulating film to leave only the sidewall portion, and an epitaxial layer formed by selective epitaxial growth of silicon. And a step of introducing a second conductivity type impurity onto the silicon single crystal substrate using the gate electrode and the sidewall region as a mask. When, characterized by comprising a.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film on a first conductivity type silicon single crystal substrate, a step of forming a gate electrode on the gate insulating film, the gate electrode, Forming a first insulating film covering the silicon single crystal substrate; forming a second insulating film having a different etching selectivity on the first insulating film; and selecting the second insulating film Forming a sidewall of the gate electrode by anisotropic etching, a step of selectively wet-etching the first insulating film to leave only the sidewall portion, and an epitaxial layer formed by selective epitaxial growth of silicon. And a step of introducing a second conductivity type impurity onto the silicon single crystal substrate using the gate electrode and the sidewall region as a mask. When, characterized by comprising a.

According to the method for manufacturing a semiconductor device according to the present invention, when the sidewall is formed by the second insulating film, the first insulating film having a different etching selectivity is used as a base to cover the silicon single crystal substrate. Yes. Thereafter, the first insulating film is selectively wet etched, so that the silicon single crystal substrate can be protected and kept clean.
In each of the above semiconductor device manufacturing methods according to the present invention, the first conductivity type silicon single crystal substrate uses an SOI substrate formed on an insulating layer. The method further includes the step of siliciding the surface of the epitaxial layer.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a region of the gate electrode as a mask on the semiconductor substrate. Forming a first impurity region to be a source / drain, a step of forming a first insulating film covering the gate electrode and the semiconductor substrate, and an etching selectivity ratio on the first insulating film. Forming a different second insulating film; selectively anisotropically etching the second insulating film to form sidewalls of the gate electrode; and selectively wet the first insulating film. Etching and remaining only in the sidewall portion; epitaxial growth step of forming an epitaxial growth layer; and masking the gate electrode and the sidewall region. Characterized by comprising a step of forming a second impurity region serving as the source / drain over the semiconductor substrate and

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a region of the gate electrode as a mask on the semiconductor substrate. Forming a source / drain impurity region on the gate, forming a first insulating film covering the gate electrode and the semiconductor substrate, and a second etching selectivity ratio on the first insulating film. Forming a second insulating film, selectively anisotropically etching the second insulating film to form sidewalls of the gate electrode, selectively wet-etching the first insulating film, and The method includes a step of remaining only in the sidewall portion and an epitaxial growth step of forming an epitaxial growth layer.

  A method for manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, and a first covering the gate electrode and the semiconductor substrate. Forming a second insulating film, forming a second insulating film having a different etching selectivity on the first insulating film, and selectively anisotropically etching the second insulating film to form the gate A step of forming a sidewall of the electrode, a step of selectively wet-etching the first insulating film to leave only the sidewall portion, an epitaxial growth step of forming an epitaxial growth layer, the gate electrode and the sidewall Forming an impurity region to be the source / drain on the semiconductor substrate using the region as a mask.

According to the method for manufacturing a semiconductor device according to the present invention, when the sidewall is formed by the second insulating film, the first insulating film having a different etching selectivity covers the semiconductor substrate as a base. Thereafter, the first insulating film is selectively wet etched, so that the semiconductor substrate can be protected and kept clean.
The semiconductor device manufacturing method according to the present invention further includes a step of siliciding the surface of the epitaxial growth layer.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a cross-sectional view showing the main configuration of the semiconductor device according to the first embodiment of the present invention. The SOI substrate 11 has a silicon single crystal substrate disposed on a buried insulating film 10 provided on a base substrate (not shown). The element region of the SOI substrate 11 is surrounded by the element isolation region 12. The SOI substrate 11 here is composed of a P ⁻ region 13 as a body into which a relatively low concentration P-type impurity is introduced. A gate insulating film 14 is formed on the P ⁻ region 13. A gate electrode 15 is formed on the gate insulating film 14. Side walls 16 are formed on the gate electrode 15. The sidewall 16 has a two-layer structure including a lower insulating film 161 and an upper insulating film 162 that can provide an etching selectivity. Elevated S / D (source / drain) regions 17 are formed on the substrate 11 on both sides of the gate electrode 15. The elevated S / D region 17 here includes a well-known LDD (Lightly Doped Drain) structure having a relatively low concentration N-type N ⁻ region 171 and a high concentration N-type N ⁺ region 172, and a sidewall 16. A silicon epitaxial layer 173 on the N ⁺ region 172 disposed on both sides is included. The silicon epitaxial layer 173 is also formed on the gate electrode 15 made of polysilicon.

  With respect to the sidewall 16, the lower insulating film 161 serves as a stopper layer during dry etching of the upper insulating film 162 and serves as a protective layer for the SOI substrate 11. The lower insulating film 161 is selectively wet etched after the sidewall shape processing of the upper insulating film 162. As a result, the lower insulating film 161 is arranged so as to be more inward of the upper insulating film 162.

A combination of the lower insulating film 161 and the upper insulating film 162 is not limited, but a material suitable for the above-described manufacturing method may be selected. For example, a SiN film can be considered as the lower insulating film 161 and a SiO ₂ film can be considered as the upper insulating film 162. In this case, the lower SiN film can be selectively wet etched with hot phosphoric acid. Conversely, a SiO ₂ film can be considered as the lower insulating film 161 and a SiN film can be considered as the upper insulating film 162. In this case, the lower SiO ₂ film can be selectively wet-etched with DHF (diluted hydrofluoric acid).

  According to the configuration of the above embodiment, the sidewall 16 has a two-layer structure. In addition, the lower insulating film 161 is a stopper layer during dry etching of the upper insulating film 162, and serves as a protective layer for the silicon single crystal substrate (SOI substrate 11) that forms the S / D region. Thereby, even if it is the thin SOI substrate 11, required thickness can be maintained. For example, PD (partially depleted type) SOI MOSFETs and FD (fully depleted type) SOI MOSFETs having a thin SOI layer of several tens of nanometers can be used. Since the lower insulating film 161 is wet-etched, the lower insulating film 161 is disposed so as to be more inwardly in the lower layer with respect to the upper insulating film 162.

2 to 4 are cross-sectional views showing the main part of the method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps. This is an example method for realizing the configuration shown in FIG. 1, and the same parts as those in FIG.
As shown in FIG. 2, an SOI substrate 11 having a P ⁻ region 13 as a body is formed on the buried insulating film 10. It is also conceivable that the P ⁻ region 13 is formed as a well region. A buried element isolation region 12 is formed on the SOI substrate 11. The element isolation region 12 includes a mask member including, for example, a nitride film and forms a trench having a predetermined pattern. Next, a CVD oxide film is deposited by a CVD (Chemical Vapor Deposition) technique using high density plasma through a sidewall oxidation process in the trench. Thereafter, a planarization process using a CMP (chemical mechanical polishing) technique and a mask member removal using wet etching are performed. Such an element isolation region 12 is to establish an element region in the SOI substrate 11. Further, instead of the buried element isolation region 12, the element isolation region may be formed by LOCOS (selective oxidation) isolation.

  Next, after forming a sacrificial oxide film (not shown), channel ion implantation of a predetermined conductivity type that also serves as a threshold (Vth) adjustment is performed. Here, ion implantation for N channel is performed. Next, after removing the sacrificial oxide film by wet etching or the like, the gate insulating film 14 is formed by using a wet oxidation method or the like. Next, a polysilicon film is deposited by, eg, CVD. Next, after ion implantation for obtaining predetermined conductivity, patterning is performed as a polysilicon electrode. Thereby, the gate electrode 15 is formed.

Next, impurity ions are implanted under a predetermined condition as an LDD structure so-called extension region using the region of the gate electrode 15 as a mask. As a result, a low concentration N ⁻ region 171 in the S / D region is formed in the figure. Next, a lower insulating film 161 such as a SiN film and an upper insulating film 162 such as a SiO ₂ film are deposited so as to cover the gate electrode 15 by CVD. Next, a CF-based gas that has a sufficient etching selectivity with the lower insulating film 161 is selected, and anisotropic dry etching of the upper insulating film 162 is performed. Thereby, a sidewall shape (16) is formed.

  Next, as shown in FIG. 3, a wet etching process using hot phosphoric acid is performed. As a result, the exposed lower insulating film 161 is selectively removed and remains only in the side wall 16 portion. Due to the formation of the sidewalls 16, the upper insulating film 162 is arranged so as to be more inwardly penetrated in the lower layer (16 U). Thereafter, a cleaning process is performed.

Next, as shown in FIG. 4, selective epitaxial growth of silicon is performed by a gas source CVD method or the like. Thereby, the epitaxial layer 173 is formed. Next, impurity ion implantation is performed under predetermined conditions as an S / D region using the region of the gate electrode 15 and the sidewall 16 as a mask. As a result, a high concentration N ⁺ region 172 is formed in the figure.

  According to the method of the above embodiment, when the sidewall is formed by processing the upper insulating film 162, the lower insulating film 161 having a different etching selection ratio is used as a base to cover the surface of the SOI substrate 11 of the silicon single crystal substrate. Thereafter, the lower insulating film 161 is selectively wet etched, so that the SOI substrate 11 can be protected and kept clean.

  FIG. 5 is a cross-sectional view showing the main configuration of a semiconductor device according to the third embodiment of the present invention, which is a configuration obtained by further performing a salicide process on the configuration of FIG. That is, a salicide process is performed in which the gate electrode 15 and the silicon epitaxial layer 173 in the S / D region are silicided in a self-aligning manner. Thereby, the low resistance layer (silicide layer) 20 is formed. Contributes to low resistance and high speed operation of devices.

FIG. 6 is a cross-sectional view showing a main configuration of a semiconductor device according to the fourth embodiment of the present invention. Compared with the first or second embodiment, the formation of the low concentration N ⁻ region 171 in the S / D region is omitted. Thus, after the formation of the silicon epitaxial layer 173, impurity ion implantation is performed as a S / D region under a predetermined condition to form an N-type region 272 having a necessary concentration. Such a configuration may also be a configuration that undergoes a salicide process as shown in FIG. 5 although not shown.

FIG. 7 is a cross-sectional view showing the main configuration of a semiconductor device according to the fifth embodiment of the present invention. FIG. 8 is a cross-sectional view showing an intermediate step for obtaining the configuration of FIG. Compared to the first or second embodiment, the ion implantation (172) after the formation of the silicon epitaxial layer 173 shown in FIG. 4 is not performed as the S / D region. For example, at the stage where the gate electrode 15 is formed, impurity ion implantation is performed under a predetermined condition in accordance with the low concentration N ⁻ region 171 to form an N type region 271 having a necessary concentration. Thereafter, in the same manner as in the method of the second embodiment, a sidewall 16 composed of a lower insulating film 161 and an upper insulating film 162 is formed (FIG. 8). Next, a silicon epitaxial layer (for example, a non-doped layer) 273 is formed. Thereafter, the silicon epitaxial layer 273 is entirely silicided through a salicide process as shown in FIG. 5 (FIG. 7).

  FIG. 9 is a cross-sectional view showing the main configuration of a semiconductor device according to the sixth embodiment of the present invention. For example, an impurity region 32 to be a source region or a drain region of the bulk MOSFET 31 is shown. Sidewalls 16 are formed of a lower insulating film 161 and an upper insulating film 162 similar to those in FIG. That is, when the sidewall is formed by processing the upper insulating film 162, the surface of the semiconductor substrate 30 is protected by using the lower insulating film 161 having a different etching selectivity as a base. When the impurity region 32 is shallow, the thickness of the impurity region 32 can be maintained, and high reliability can be obtained for the subsequent epitaxial growth and further silicidation.

As described above, according to the configuration and method of each embodiment, the sidewall has a two-layer structure, and the lower insulating film is a stopper layer in the upper insulating film dry etching process, and the S / D region is It becomes a protective layer of the silicon single crystal substrate (SOI substrate) to be formed. That is, the Si surface is not scraped off during the dry etching of the sidewall processing. In addition, the SOI substrate can be kept clean. Therefore, a PD (partially depleted type) SOI MOSFET and a thin SOI layer of an SOI layer can sufficiently cope with a process of forming an FD (fully depleted type) SOI MOSFET having several tens of nm. In each of the above embodiments, the N-channel MOSFET is shown, but the same effect can be obtained with the P-channel MOSFET.
Further, the epitaxial growth layer is not limited to silicon, and silicon germanium may be used. Therefore, the semiconductor substrate is not limited to a silicon single crystal, and other semiconductor substrates may be used. Further, the present invention can be applied not only to SOI substrates but also to bulk technologies. It is particularly useful for bulk MOSFETs having shallow source / drain regions.
As a result of such consideration, it is possible to provide a semiconductor device that suppresses contamination and thickness reduction of the Si layer in the S / D region accompanying the formation of the sidewall of the MOSFET in the SOI layer, and a manufacturing method thereof.

FIG. 3 is a cross-sectional view showing the main configuration of the semiconductor device according to the first embodiment. The 1st sectional view showing the manufacturing method of the semiconductor device concerning a 2nd embodiment in order of a process. FIG. 3 is a second cross-sectional view following FIG. 2. FIG. 4 is a third cross-sectional view following FIG. 3. Sectional drawing which shows the principal part structure of the semiconductor device which concerns on 3rd Embodiment. Sectional drawing which shows the principal part structure of the semiconductor device which concerns on 4th Embodiment. Sectional drawing which shows the principal part structure of the semiconductor device which concerns on 5th Embodiment. Sectional drawing which shows the intermediate | middle process for obtaining the structure of FIG. Sectional drawing which shows the principal part structure of the semiconductor device which concerns on 6th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Embedded insulating film, 11 ... SOI substrate, 12 ... Element isolation region, 13 ... P ^- region, 14 ... Gate insulating film, 15 ... Gate electrode, 16 ... Side wall, 161 ... Lower layer insulating film, 162 ... Upper layer insulating film , 17 ... elevate the S / D regions, 171 ... N ^- region, 172 ... ^{N +} region, 173,273 ... silicon epitaxial layer, 20 ... low-resistance layer (silicide layer), 271 and 272 ... N-type region, 30 ... Semiconductor substrate, 31... Bulk MOSFET, 32... Impurity region.

Claims (15)

A first conductivity type silicon single crystal substrate on an insulating layer;
A gate insulating film on the silicon single crystal substrate;
A gate electrode on the gate insulating film;
First and second insulating films constituting sidewalls of the gate electrode;
A second conductivity type impurity region including a silicon epitaxial layer disposed on both sides of the sidewall;
Comprising
The first insulating film is located below the second insulating film, serves as a stopper layer for processing the second insulating film, and serves as a protective layer for the silicon single crystal substrate. . A first conductivity type silicon single crystal substrate on an insulating layer;
A gate insulating film on the silicon single crystal substrate;
A gate electrode on the gate insulating film;
First and second insulating films constituting sidewalls of the gate electrode;
A second conductivity type impurity region including a silicon epitaxial layer disposed on both sides of the sidewall;
Comprising
The semiconductor device according to claim 1, wherein the first insulating film is arranged so as to be further inwardly formed in a lower layer with respect to the second insulating film. The semiconductor device according to claim 1, further comprising a silicide on the silicon epitaxial layer. A semiconductor substrate;
A gate insulating film on the semiconductor substrate;
A gate electrode on the gate insulating film;
First and second insulating films constituting sidewalls of the gate electrode;
A source / drain region including an epitaxial layer disposed on both sides of the sidewall;
Comprising
The semiconductor device according to claim 1, wherein the first insulating film is positioned below the second insulating film, serves as a stopper layer for processing the second insulating film, and serves as a protective layer for the semiconductor substrate. A semiconductor substrate;
A gate insulating film on the semiconductor substrate;
A gate electrode on the gate insulating film;
First and second insulating films constituting sidewalls of the gate electrode;
A source / drain region including an epitaxial growth layer disposed on both sides of the sidewall;
Comprising
The semiconductor device according to claim 1, wherein the first insulating film is arranged so as to be further inwardly formed in a lower layer with respect to the second insulating film. The semiconductor device according to claim 1, further comprising a silicide on the epitaxial growth layer. Forming a gate insulating film on the first conductivity type silicon single crystal substrate;
Forming a gate electrode on the gate insulating film;
Introducing a second conductivity type impurity onto the silicon single crystal substrate using the gate electrode region as a mask;
Forming a first insulating film covering the gate electrode and the silicon single crystal substrate;
Forming a second insulating film having a different etching selectivity on the first insulating film;
Selectively anisotropically etching the second insulating film to form sidewalls of the gate electrode;
Selectively wet-etching the first insulating film to leave only the sidewall portion;
Forming an epitaxial layer by selective epitaxial growth of silicon;
Introducing a second conductivity type impurity onto the silicon single crystal substrate using the gate electrode and the sidewall region as a mask;
A method for manufacturing a semiconductor device, comprising: Forming a gate insulating film on the first conductivity type silicon single crystal substrate;
Forming a gate electrode on the gate insulating film;
Introducing a second conductivity type impurity onto the silicon single crystal substrate using the gate electrode region as a mask;
Forming a first insulating film covering the gate electrode and the silicon single crystal substrate;
Forming a second insulating film having a different etching selectivity on the first insulating film;
Selectively anisotropically etching the second insulating film to form sidewalls of the gate electrode;
Selectively wet-etching the first insulating film to leave only the sidewall portion;
Forming an epitaxial layer by selective epitaxial growth of silicon;
A method for manufacturing a semiconductor device, comprising: Forming a gate insulating film on the first conductivity type silicon single crystal substrate;
Forming a gate electrode on the gate insulating film;
Forming a first insulating film covering the gate electrode and the silicon single crystal substrate;
Forming a second insulating film having a different etching selectivity on the first insulating film;
Selectively anisotropically etching the second insulating film to form sidewalls of the gate electrode;
Selectively wet-etching the first insulating film to leave only the sidewall portion;
Forming an epitaxial layer by selective epitaxial growth of silicon;
Introducing a second conductivity type impurity onto the silicon single crystal substrate using the gate electrode and the sidewall region as a mask;
A method for manufacturing a semiconductor device, comprising: 10. The method of manufacturing a semiconductor device according to claim 7, wherein an SOI substrate formed on an insulating layer is used as the first conductivity type silicon single crystal substrate. 11. The method for manufacturing a semiconductor device according to claim 7, further comprising a step of siliciding the surface of the epitaxial layer. Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a first impurity region to be a source / drain on the semiconductor substrate using the gate electrode region as a mask;
Forming a first insulating film covering the gate electrode and the semiconductor substrate;
Forming a second insulating film having a different etching selectivity on the first insulating film;
Selectively anisotropically etching the second insulating film to form sidewalls of the gate electrode;
Selectively wet-etching the first insulating film to leave only the sidewall portion;
An epitaxial growth step for forming an epitaxial layer;
Forming a second impurity region to be the source / drain on the semiconductor substrate using the gate electrode and the sidewall region as a mask;
A method for manufacturing a semiconductor device, comprising: Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a source / drain impurity region on the semiconductor substrate using the gate electrode region as a mask;
Forming a first insulating film covering the gate electrode and the semiconductor substrate;
Forming a second insulating film having a different etching selectivity on the first insulating film;
Selectively anisotropically etching the second insulating film to form sidewalls of the gate electrode;
Selectively wet-etching the first insulating film to leave only the sidewall portion;
An epitaxial growth step for forming an epitaxial layer;
A method for manufacturing a semiconductor device, comprising: Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a first insulating film covering the gate electrode and the semiconductor substrate;
Forming a second insulating film having a different etching selectivity on the first insulating film;
Selectively anisotropically etching the second insulating film to form sidewalls of the gate electrode;
Selectively wet-etching the first insulating film to leave only the sidewall portion;
An epitaxial growth step for forming an epitaxial layer;
Forming an impurity region to be the source / drain on the semiconductor substrate using the gate electrode and the sidewall region as a mask;
A method for manufacturing a semiconductor device, comprising: 15. The method of manufacturing a semiconductor device according to claim 12, further comprising a step of siliciding the surface of the epitaxial layer.

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